drivers: clk: Fix check for assigned-clock-rates index

Index should actually be strictly less than rate_len. Fix this which
might happen with the following description:

assigned-clock = <foo>, <bar

drivers: clk: Fix check for assigned-clock-rates index

Index should actually be strictly less than rate_len. Fix this which
might happen with the following description:

assigned-clock = <foo>, <bar>;
assigned-clock-parents = <foo_parent>, <bar_parent>;
assigned-clock-rates = <1000>;

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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core: dt_driver: allow parsing of phandle == 0

In Linux, it is allowed to specify a null phandle which means it should
be skipped. Add support for this specific case by simply skipping over
it. This

core: dt_driver: allow parsing of phandle == 0

In Linux, it is allowed to specify a null phandle which means it should
be skipped. Add support for this specific case by simply skipping over
it. This is needed to parse assigned-clock-parents which can use such
syntax. This is specified in the clock bindings [1] which says the
following:

To skip setting parent or rate of a clock its corresponding entry
should be set to 0, or can be omitted if it is not followed by any
non-zero entry

For example this is a valid device-tree description:

assigned-clocks = <foo>, <bar>;
assigned-clock-parents = <0> <bar_parent>;
assigned-clock-rates = <1000>;

Link: [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: imx: dump TZASC state after lockdown

Call the TZASC configuration dump after the region lockdown.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.fo

drivers: imx: dump TZASC state after lockdown

Call the TZASC configuration dump after the region lockdown.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: imx: tzc380: register TZC380 memory registers

Register TZASC memory registers for TZASC and eventually TZASC2.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissi

drivers: imx: tzc380: register TZC380 memory registers

Register TZASC memory registers for TZASC and eventually TZASC2.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: tzc380: fix the lockdown range register value

This register controls the range of regions that are locked down.
The number of regions to lockdown are defined in [1]:
lockdown_range[3:0] and

drivers: tzc380: fix the lockdown range register value

This register controls the range of regions that are locked down.
The number of regions to lockdown are defined in [1]:
lockdown_range[3:0] and its value goes from b0000 to b1111.

If the goal of tzc_regions_lockdown() is to lock all regions supported
by the platforms, then the value of lockdown_range[3:0] should be equal
to no_of_regions[3:0] of the configuration register [2].

Currently, tzc.num_regions is used to defined the lockdown range which
is incorrect because it has been incremented during initialization.
Fix the issue by decrementing tzc.num_regions before the configuration
of lockdown_range[3:0].

Link: [1] https://developer.arm.com/documentation/ddi0431/c/programmers-model/register-descriptions/lockdown-range-register
Link: [2] https://developer.arm.com/documentation/ddi0431/c/programmers-model/register-descriptions/configuration-register
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: add TZASC_SIZE for imx6, imx7 and imx8m

Add TZASC_SIZE value for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@lin

core: imx: add TZASC_SIZE for imx6, imx7 and imx8m

Add TZASC_SIZE value for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: fix use after free in tee_ta_open_session()

Fixes a use after free where the session pointer 's' was used after
tee_ta_close_session() while recovering from an error.

Fixes: 82061b8d7b34 ("co

core: fix use after free in tee_ta_open_session()

Fixes a use after free where the session pointer 's' was used after
tee_ta_close_session() while recovering from an error.

Fixes: 82061b8d7b34 ("core: store TA params in session struct")
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-versal: add support for Xilinx's Versal ACAP platform

Initial support for the Versal ACAP validated on the AI Core Series VKC190
Evaluation Kit.

The following BIF file is used by bootgen to ge

plat-versal: add support for Xilinx's Versal ACAP platform

Initial support for the Versal ACAP validated on the AI Core Series VKC190
Evaluation Kit.

The following BIF file is used by bootgen to generate the Versal boot.bin
image.

the_ROM_image:
{
image {
{ type=bootimage, file=vpl_gen_fixed.pdi }
{ type=bootloader, file=plm.elf }
{ core=psm, file=psmfw.elf }
}

image {
id = 0x1c000000, name=apu_subsystem
{ type=raw, load=0x00001000, file=system.dtb }
{ core=a72-0, exception_level=el-3, trustzone, file=bl31.elf }
{ core=a72-0, exception_level=el-2, file=u-boot.elf }
{ core=a72-0, exception_level=el-1, trustzone, file=tee.elf }
}
}

$ ./bootgen -arch versal -image boot.bif -o BOOT.BIN

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: John Linn <linnj@xilinx.com>
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp1: scmi: export some STPMIC1 regulators as voltage domains

Exposes STPMIC1 regulators through agent channel SCMI for platform
stm32mp1.

Acked-by: Jens Wiklander <jens.wiklander@linaro.o

plat-stm32mp1: scmi: export some STPMIC1 regulators as voltage domains

Exposes STPMIC1 regulators through agent channel SCMI for platform
stm32mp1.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: dt-bindings: stm32mp1: add IDs for STPMIC1 SCMI voltage regulators

Define the SCMI voltage domain IDs exposed by OP-TEE SCMI server on
stm32mp1.

Acked-by: Jens Wiklander <jens.wiklander@linar

core: dt-bindings: stm32mp1: add IDs for STPMIC1 SCMI voltage regulators

Define the SCMI voltage domain IDs exposed by OP-TEE SCMI server on
stm32mp1.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stpmic1: export regulators API in a specific header file

Split stpmic1.h in 2 parts, one specifically for STPMIC1 regulator
interface.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

drivers: stpmic1: export regulators API in a specific header file

Split stpmic1.h in 2 parts, one specifically for STPMIC1 regulator
interface.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: imx_i2c: add support for MX8MP

Add I2C driver support for iMX8MP.

Signed-off-by: Vanessa Maegima <vanessa.maegima@foundries.io>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jo

drivers: imx_i2c: add support for MX8MP

Add I2C driver support for iMX8MP.

Signed-off-by: Vanessa Maegima <vanessa.maegima@foundries.io>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

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plat-stm32mp1: fix apb3/4 iomem static mapping

Fixes APB3 device memory mapping size and adds APB4 device memory to
core static mapping.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Sig

plat-stm32mp1: fix apb3/4 iomem static mapping

Fixes APB3 device memory mapping size and adds APB4 device memory to
core static mapping.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-vexpress: Use the correct MACRO for TPM2

Replace CFG_TPM2_MMIO with CFG_DRIVERS_TPM2_MMIO.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@l

plat-vexpress: Use the correct MACRO for TPM2

Replace CFG_TPM2_MMIO with CFG_DRIVERS_TPM2_MMIO.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: io: add {get/put}_unaligned_le{16/32/64}()

Add 16, 32 and 64 bits put/get functions for little endian
unaligned access

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jen

core: io: add {get/put}_unaligned_le{16/32/64}()

Add 16, 32 and 64 bits put/get functions for little endian
unaligned access

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: FF-A: Map TPM event log for FF-A SPs

Enable passing the TPM event log to FF-A SPs if their manifest has an
"arm,tpm_event_log" compatible node. The event log is mapped to the
SP's address spac

core: FF-A: Map TPM event log for FF-A SPs

Enable passing the TPM event log to FF-A SPs if their manifest has an
"arm,tpm_event_log" compatible node. The event log is mapped to the
SP's address space and the address and size fields are updated in the
SP manifest.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Imre Kis <imre.kis@arm.com>

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core: Enable mapping DT from secure memory

Add CFG_MAP_EXT_DT_SECURE option to enable mapping the device tree from
the secure memory. As the device tree in the secure memory would only
have the even

core: Enable mapping DT from secure memory

Add CFG_MAP_EXT_DT_SECURE option to enable mapping the device tree from
the secure memory. As the device tree in the secure memory would only
have the event log address in the secure memory the property name is
changed from tpm_event_log_sm_addr to the standard tpm_event_log_addr
when CFG_MAP_EXT_DT_SECURE is enabled.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Imre Kis <imre.kis@arm.com>

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core: arm: spectre-bhb software workaround

Expands the config option CFG_CORE_WORKAROUND_SPECTRE_BP_SEC to cover
CVE-2022-23960 (aka Spectre-BHB) too since both have much in common.

Spectre-BHB is

core: arm: spectre-bhb software workaround

Expands the config option CFG_CORE_WORKAROUND_SPECTRE_BP_SEC to cover
CVE-2022-23960 (aka Spectre-BHB) too since both have much in common.

Spectre-BHB is another speculation attack on branch prediction. Further
details can be found at [1].

The software workaround added for CPUs vulnerable to Spectre-V2 covers
Spectre-BHB too. New software workaround is only needed for CPUs immune to
Spectre-V2, but not so to Spectre-BHB.

The Spectre-V2 workaround is to invalidate the entire branch predictor
table. Most new CPU immune to Spectre-V2 but vulnerable to Spectre-BHB
can avoid invalidating the entire branch predictor table, instead is
this invalidation replaced by a loop designed to exhaust the branch
predictor in a way that the exploit isn't possible any longer.

Link: [1] https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/spectre-bhb

Fixes: CVE-2022-23960
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: refactor spectre-v2 workarounds

Refactors the Spectre-V2 workarounds to make room for further workarounds.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wikl

core: refactor spectre-v2 workarounds

Refactors the Spectre-V2 workarounds to make room for further workarounds.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add arm cortex and neoverse CPU part numbers

Adds part numbers for a few Arm Cortex and Neoverse CPUs. Also adds
defines helping to extract Variant and Revision from MIDR or MIDR_EL1.

Acked-b

core: add arm cortex and neoverse CPU part numbers

Adds part numbers for a few Arm Cortex and Neoverse CPUs. Also adds
defines helping to extract Variant and Revision from MIDR or MIDR_EL1.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix unused set_core_local_kcode_offset() warning

When compiling with CFG_CORE_UNMAP_CORE_AT_EL0=n there's a warning:
core/arch/arm/kernel/thread.c:529:13: error: ‘set_core_local_kcode_offset’

core: fix unused set_core_local_kcode_offset() warning

When compiling with CFG_CORE_UNMAP_CORE_AT_EL0=n there's a warning:
core/arch/arm/kernel/thread.c:529:13: error: ‘set_core_local_kcode_offset’ defined but not used [-Werror=unused-function]

Fix this with by adding a __maybe_unused to the function.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: qemu: initialize TPM driver

QEMU implements a TPM emulation with TPM TIS/PTP interface. The PTP
interface is exposed via a memory mapped region to the TEE (MMIO
interface).

QEMU TPM

plat-vexpress: qemu: initialize TPM driver

QEMU implements a TPM emulation with TPM TIS/PTP interface. The PTP
interface is exposed via a memory mapped region to the TEE (MMIO
interface).

QEMU TPM emulation can be used with a virtualized TPM2.0 device
(sw-tpm).

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers/tpm2: Startup TPM when chip is registered

When tpm2 chip is registered, call the initialization
sequence of tpm to do self test and startup the tpm chip.

Signed-off-by: Ruchika Gupta <ruchi

drivers/tpm2: Startup TPM when chip is registered

When tpm2 chip is registered, call the initialization
sequence of tpm to do self test and startup the tpm chip.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers/tpm2: Add basic structure for commands

Add infrastructure for TPM2 commands based on [1].

Few basic commands like TPM2 Startup and Selftest. These
will be used by device driver during initi

drivers/tpm2: Add basic structure for commands

Add infrastructure for TPM2 commands based on [1].

Few basic commands like TPM2 Startup and Selftest. These
will be used by device driver during initialization.

[1] Trusted Platform Module Library Part 3: Commands
Family “2.0” Level 00 Revision 01.59

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers/tpm2: Add TPM2 MMIO driver

Add support for platforms that interface with TPM2 via
MMIO using FIFO protocol.

Co-developed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Victor Cho

drivers/tpm2: Add TPM2 MMIO driver

Add support for platforms that interface with TPM2 via
MMIO using FIFO protocol.

Co-developed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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