1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 #ifndef ARM64_H 6 #define ARM64_H 7 8 #include <compiler.h> 9 #include <sys/cdefs.h> 10 #include <stdint.h> 11 #include <util.h> 12 13 #define SCTLR_M BIT64(0) 14 #define SCTLR_A BIT64(1) 15 #define SCTLR_C BIT64(2) 16 #define SCTLR_SA BIT64(3) 17 #define SCTLR_I BIT64(12) 18 #define SCTLR_ENDB BIT64(13) 19 #define SCTLR_WXN BIT64(19) 20 #define SCTLR_SPAN BIT64(23) 21 #define SCTLR_ENDA BIT64(27) 22 #define SCTLR_ENIB BIT64(30) 23 #define SCTLR_ENIA BIT64(31) 24 #define SCTLR_BT0 BIT64(35) 25 #define SCTLR_BT1 BIT64(36) 26 27 #define TTBR_ASID_MASK U(0xff) 28 #define TTBR_ASID_SHIFT U(48) 29 30 #define CLIDR_LOUIS_SHIFT U(21) 31 #define CLIDR_LOC_SHIFT U(24) 32 #define CLIDR_FIELD_WIDTH U(3) 33 34 #define CSSELR_LEVEL_SHIFT U(1) 35 36 #define DAIFBIT_FIQ BIT32(0) 37 #define DAIFBIT_IRQ BIT32(1) 38 #define DAIFBIT_ABT BIT32(2) 39 #define DAIFBIT_DBG BIT32(3) 40 #define DAIFBIT_ALL (DAIFBIT_FIQ | DAIFBIT_IRQ | \ 41 DAIFBIT_ABT | DAIFBIT_DBG) 42 43 #define DAIF_F_SHIFT U(6) 44 #define DAIF_F BIT32(6) 45 #define DAIF_I BIT32(7) 46 #define DAIF_A BIT32(8) 47 #define DAIF_D BIT32(9) 48 #define DAIF_AIF (DAIF_A | DAIF_I | DAIF_F) 49 50 #define SPSR_MODE_RW_SHIFT U(4) 51 #define SPSR_MODE_RW_MASK U(0x1) 52 #define SPSR_MODE_RW_64 U(0x0) 53 #define SPSR_MODE_RW_32 U(0x1) 54 55 #define SPSR_64_MODE_SP_SHIFT U(0) 56 #define SPSR_64_MODE_SP_MASK U(0x1) 57 #define SPSR_64_MODE_SP_EL0 U(0x0) 58 #define SPSR_64_MODE_SP_ELX U(0x1) 59 60 #define SPSR_64_MODE_EL_SHIFT U(2) 61 #define SPSR_64_MODE_EL_MASK U(0x3) 62 #define SPSR_64_MODE_EL1 U(0x1) 63 #define SPSR_64_MODE_EL0 U(0x0) 64 65 #define SPSR_64_DAIF_SHIFT U(6) 66 #define SPSR_64_DAIF_MASK U(0xf) 67 68 #define SPSR_32_AIF_SHIFT U(6) 69 #define SPSR_32_AIF_MASK U(0x7) 70 71 #define SPSR_32_E_SHIFT U(9) 72 #define SPSR_32_E_MASK U(0x1) 73 #define SPSR_32_E_LITTLE U(0x0) 74 #define SPSR_32_E_BIG U(0x1) 75 76 #define SPSR_32_T_SHIFT U(5) 77 #define SPSR_32_T_MASK U(0x1) 78 #define SPSR_32_T_ARM U(0x0) 79 #define SPSR_32_T_THUMB U(0x1) 80 81 #define SPSR_32_MODE_SHIFT U(0) 82 #define SPSR_32_MODE_MASK U(0xf) 83 #define SPSR_32_MODE_USR U(0x0) 84 85 86 #define SPSR_64(el, sp, daif) \ 87 (SPSR_MODE_RW_64 << SPSR_MODE_RW_SHIFT | \ 88 ((el) & SPSR_64_MODE_EL_MASK) << SPSR_64_MODE_EL_SHIFT | \ 89 ((sp) & SPSR_64_MODE_SP_MASK) << SPSR_64_MODE_SP_SHIFT | \ 90 ((daif) & SPSR_64_DAIF_MASK) << SPSR_64_DAIF_SHIFT) 91 92 #define SPSR_32(mode, isa, aif) \ 93 (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT | \ 94 SPSR_32_E_LITTLE << SPSR_32_E_SHIFT | \ 95 ((mode) & SPSR_32_MODE_MASK) << SPSR_32_MODE_SHIFT | \ 96 ((isa) & SPSR_32_T_MASK) << SPSR_32_T_SHIFT | \ 97 ((aif) & SPSR_32_AIF_MASK) << SPSR_32_AIF_SHIFT) 98 99 100 #define TCR_T0SZ_SHIFT U(0) 101 #define TCR_EPD0 BIT64(7) 102 #define TCR_IRGN0_SHIFT U(8) 103 #define TCR_ORGN0_SHIFT U(10) 104 #define TCR_SH0_SHIFT U(12) 105 #define TCR_T1SZ_SHIFT U(16) 106 #define TCR_A1 BIT64(22) 107 #define TCR_EPD1 BIT64(23) 108 #define TCR_IRGN1_SHIFT U(24) 109 #define TCR_ORGN1_SHIFT U(26) 110 #define TCR_SH1_SHIFT U(28) 111 #define TCR_EL1_IPS_SHIFT U(32) 112 #define TCR_EL1_IPS_MASK UINT64_C(0x7) 113 #define TCR_TG1_4KB SHIFT_U64(2, 30) 114 #define TCR_RES1 BIT64(31) 115 116 117 /* Normal memory, Inner/Outer Non-cacheable */ 118 #define TCR_XRGNX_NC U(0x0) 119 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 120 #define TCR_XRGNX_WB U(0x1) 121 /* Normal memory, Inner/Outer Write-Through Cacheable */ 122 #define TCR_XRGNX_WT U(0x2) 123 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 124 #define TCR_XRGNX_WBWA U(0x3) 125 126 /* Non-shareable */ 127 #define TCR_SHX_NSH U(0x0) 128 /* Outer Shareable */ 129 #define TCR_SHX_OSH U(0x2) 130 /* Inner Shareable */ 131 #define TCR_SHX_ISH U(0x3) 132 133 #define ESR_EC_SHIFT U(26) 134 #define ESR_EC_MASK U(0x3f) 135 136 #define ESR_EC_UNKNOWN U(0x00) 137 #define ESR_EC_WFI U(0x01) 138 #define ESR_EC_AARCH32_CP15_32 U(0x03) 139 #define ESR_EC_AARCH32_CP15_64 U(0x04) 140 #define ESR_EC_AARCH32_CP14_MR U(0x05) 141 #define ESR_EC_AARCH32_CP14_LS U(0x06) 142 #define ESR_EC_FP_ASIMD U(0x07) 143 #define ESR_EC_AARCH32_CP10_ID U(0x08) 144 #define ESR_EC_PAUTH U(0x09) 145 #define ESR_EC_AARCH32_CP14_64 U(0x0c) 146 #define ESR_EC_BTI U(0x0d) 147 #define ESR_EC_ILLEGAL U(0x0e) 148 #define ESR_EC_AARCH32_SVC U(0x11) 149 #define ESR_EC_AARCH64_SVC U(0x15) 150 #define ESR_EC_AARCH64_SYS U(0x18) 151 #define ESR_EC_ERET U(0x1a) 152 #define ESR_EC_FPAC U(0x1c) 153 #define ESR_EC_IABT_EL0 U(0x20) 154 #define ESR_EC_IABT_EL1 U(0x21) 155 #define ESR_EC_PC_ALIGN U(0x22) 156 #define ESR_EC_DABT_EL0 U(0x24) 157 #define ESR_EC_DABT_EL1 U(0x25) 158 #define ESR_EC_SP_ALIGN U(0x26) 159 #define ESR_EC_AARCH32_FP U(0x28) 160 #define ESR_EC_AARCH64_FP U(0x2c) 161 #define ESR_EC_SERROR U(0x2f) 162 #define ESR_EC_BREAKPT_EL0 U(0x30) 163 #define ESR_EC_BREAKPT_EL1 U(0x31) 164 #define ESR_EC_SOFTSTP_EL0 U(0x32) 165 #define ESR_EC_SOFTSTP_EL1 U(0x33) 166 #define ESR_EC_WATCHPT_EL0 U(0x34) 167 #define ESR_EC_WATCHPT_EL1 U(0x35) 168 #define ESR_EC_AARCH32_BKPT U(0x38) 169 #define ESR_EC_AARCH64_BRK U(0x3c) 170 171 /* Combined defines for DFSC and IFSC */ 172 #define ESR_FSC_MASK U(0x3f) 173 #define ESR_FSC_SIZE_L0 U(0x00) 174 #define ESR_FSC_SIZE_L1 U(0x01) 175 #define ESR_FSC_SIZE_L2 U(0x02) 176 #define ESR_FSC_SIZE_L3 U(0x03) 177 #define ESR_FSC_TRANS_L0 U(0x04) 178 #define ESR_FSC_TRANS_L1 U(0x05) 179 #define ESR_FSC_TRANS_L2 U(0x06) 180 #define ESR_FSC_TRANS_L3 U(0x07) 181 #define ESR_FSC_ACCF_L1 U(0x09) 182 #define ESR_FSC_ACCF_L2 U(0x0a) 183 #define ESR_FSC_ACCF_L3 U(0x0b) 184 #define ESR_FSC_PERMF_L1 U(0x0d) 185 #define ESR_FSC_PERMF_L2 U(0x0e) 186 #define ESR_FSC_PERMF_L3 U(0x0f) 187 #define ESR_FSC_TAG_CHECK U(0x11) 188 #define ESR_FSC_ALIGN U(0x21) 189 190 /* WnR for DABT and RES0 for IABT */ 191 #define ESR_ABT_WNR BIT32(6) 192 193 #define CPACR_EL1_FPEN_SHIFT U(20) 194 #define CPACR_EL1_FPEN_MASK U(0x3) 195 #define CPACR_EL1_FPEN_NONE U(0x0) 196 #define CPACR_EL1_FPEN_EL1 U(0x1) 197 #define CPACR_EL1_FPEN_EL0EL1 U(0x3) 198 #define CPACR_EL1_FPEN(x) ((x) >> CPACR_EL1_FPEN_SHIFT \ 199 & CPACR_EL1_FPEN_MASK) 200 201 202 #define PAR_F BIT32(0) 203 #define PAR_PA_SHIFT U(12) 204 #define PAR_PA_MASK (BIT64(36) - 1) 205 206 #define TLBI_MVA_SHIFT U(12) 207 #define TLBI_ASID_SHIFT U(48) 208 #define TLBI_ASID_MASK U(0xff) 209 210 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 211 #define FEAT_BTI_IMPLEMENTED ULL(0x1) 212 213 #define ID_AA64PFR1_EL1_MTE_MASK UL(0xf) 214 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 215 #define FEAT_MTE_NOT_IMPLEMENTED U(0x0) 216 #define FEAT_MTE_IMPLEMENTED U(0x1) 217 #define FEAT_MTE2_IMPLEMENTED U(0x2) 218 #define FEAT_MTE3_IMPLEMENTED U(0x3) 219 220 #define ID_AA64ISAR1_GPI_SHIFT U(28) 221 #define ID_AA64ISAR1_GPI_MASK U(0xf) 222 #define ID_AA64ISAR1_GPI_NI U(0x0) 223 #define ID_AA64ISAR1_GPI_IMP_DEF U(0x1) 224 225 #define ID_AA64ISAR1_GPA_SHIFT U(24) 226 #define ID_AA64ISAR1_GPA_MASK U(0xf) 227 #define ID_AA64ISAR1_GPA_NI U(0x0) 228 #define ID_AA64ISAR1_GPA_ARCHITECTED U(0x1) 229 230 #define ID_AA64ISAR1_API_SHIFT U(8) 231 #define ID_AA64ISAR1_API_MASK U(0xf) 232 #define ID_AA64ISAR1_API_NI U(0x0) 233 #define ID_AA64ISAR1_API_IMP_DEF U(0x1) 234 #define ID_AA64ISAR1_API_IMP_DEF_EPAC U(0x2) 235 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2 U(0x3) 236 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC U(0x4) 237 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB U(0x5) 238 239 #define ID_AA64ISAR1_APA_SHIFT U(4) 240 #define ID_AA64ISAR1_APA_MASK U(0xf) 241 #define ID_AA64ISAR1_APA_NI U(0x0) 242 #define ID_AA64ISAR1_APA_ARCHITECTED U(0x1) 243 #define ID_AA64ISAR1_APA_ARCH_EPAC U(0x2) 244 #define ID_AA64ISAR1_APA_ARCH_EPAC2 U(0x3) 245 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC U(0x4) 246 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB U(0x5) 247 248 #ifndef __ASSEMBLER__ 249 static inline __noprof void isb(void) 250 { 251 asm volatile ("isb" : : : "memory"); 252 } 253 254 static inline __noprof void dsb(void) 255 { 256 asm volatile ("dsb sy" : : : "memory"); 257 } 258 259 static inline __noprof void dsb_ish(void) 260 { 261 asm volatile ("dsb ish" : : : "memory"); 262 } 263 264 static inline __noprof void dsb_ishst(void) 265 { 266 asm volatile ("dsb ishst" : : : "memory"); 267 } 268 269 static inline __noprof void sev(void) 270 { 271 asm volatile ("sev" : : : "memory"); 272 } 273 274 static inline __noprof void wfe(void) 275 { 276 asm volatile ("wfe" : : : "memory"); 277 } 278 279 static inline __noprof void wfi(void) 280 { 281 asm volatile ("wfi" : : : "memory"); 282 } 283 284 static inline __noprof void write_at_s1e1r(uint64_t va) 285 { 286 asm volatile ("at S1E1R, %0" : : "r" (va)); 287 } 288 289 static __always_inline __noprof uint64_t read_pc(void) 290 { 291 uint64_t val; 292 293 asm volatile ("adr %0, ." : "=r" (val)); 294 return val; 295 } 296 297 static __always_inline __noprof uint64_t read_fp(void) 298 { 299 uint64_t val; 300 301 asm volatile ("mov %0, x29" : "=r" (val)); 302 return val; 303 } 304 305 static inline __noprof uint64_t read_pmu_ccnt(void) 306 { 307 uint64_t val; 308 309 asm volatile("mrs %0, PMCCNTR_EL0" : "=r"(val)); 310 return val; 311 } 312 313 static inline __noprof void tlbi_vaae1is(uint64_t mva) 314 { 315 asm volatile ("tlbi vaae1is, %0" : : "r" (mva)); 316 } 317 318 static inline __noprof void tlbi_vale1is(uint64_t mva) 319 { 320 asm volatile ("tlbi vale1is, %0" : : "r" (mva)); 321 } 322 323 /* 324 * Templates for register read/write functions based on mrs/msr 325 */ 326 327 #define DEFINE_REG_READ_FUNC_(reg, type, asmreg) \ 328 static inline __noprof type read_##reg(void) \ 329 { \ 330 uint64_t val64 = 0; \ 331 \ 332 asm volatile("mrs %0, " #asmreg : "=r" (val64)); \ 333 return val64; \ 334 } 335 336 #define DEFINE_REG_WRITE_FUNC_(reg, type, asmreg) \ 337 static inline __noprof void write_##reg(type val) \ 338 { \ 339 uint64_t val64 = val; \ 340 \ 341 asm volatile("msr " #asmreg ", %0" : : "r" (val64)); \ 342 } 343 344 #define DEFINE_U32_REG_READ_FUNC(reg) \ 345 DEFINE_REG_READ_FUNC_(reg, uint32_t, reg) 346 347 #define DEFINE_U32_REG_WRITE_FUNC(reg) \ 348 DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg) 349 350 #define DEFINE_U32_REG_READWRITE_FUNCS(reg) \ 351 DEFINE_U32_REG_READ_FUNC(reg) \ 352 DEFINE_U32_REG_WRITE_FUNC(reg) 353 354 #define DEFINE_U64_REG_READ_FUNC(reg) \ 355 DEFINE_REG_READ_FUNC_(reg, uint64_t, reg) 356 357 #define DEFINE_U64_REG_WRITE_FUNC(reg) \ 358 DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg) 359 360 #define DEFINE_U64_REG_READWRITE_FUNCS(reg) \ 361 DEFINE_U64_REG_READ_FUNC(reg) \ 362 DEFINE_U64_REG_WRITE_FUNC(reg) 363 364 /* 365 * Define register access functions 366 */ 367 368 DEFINE_U32_REG_READWRITE_FUNCS(cpacr_el1) 369 DEFINE_U32_REG_READWRITE_FUNCS(daif) 370 DEFINE_U32_REG_READWRITE_FUNCS(fpcr) 371 DEFINE_U32_REG_READWRITE_FUNCS(fpsr) 372 373 DEFINE_U32_REG_READ_FUNC(ctr_el0) 374 #define read_ctr() read_ctr_el0() 375 DEFINE_U32_REG_READ_FUNC(contextidr_el1) 376 DEFINE_U64_REG_READ_FUNC(sctlr_el1) 377 378 /* ARM Generic timer functions */ 379 DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0) 380 DEFINE_REG_READ_FUNC_(cntvct, uint64_t, cntvct_el0) 381 DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0) 382 DEFINE_REG_READ_FUNC_(cntkctl, uint32_t, cntkctl_el1) 383 DEFINE_REG_WRITE_FUNC_(cntkctl, uint32_t, cntkctl_el1) 384 DEFINE_REG_READ_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1) 385 DEFINE_REG_WRITE_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1) 386 DEFINE_REG_READ_FUNC_(cntps_tval, uint32_t, cntps_tval_el1) 387 DEFINE_REG_WRITE_FUNC_(cntps_tval, uint32_t, cntps_tval_el1) 388 389 DEFINE_REG_READ_FUNC_(pmccntr, uint64_t, pmccntr_el0) 390 391 DEFINE_U64_REG_READWRITE_FUNCS(ttbr0_el1) 392 DEFINE_U64_REG_READWRITE_FUNCS(ttbr1_el1) 393 DEFINE_U64_REG_READWRITE_FUNCS(tcr_el1) 394 395 DEFINE_U64_REG_READ_FUNC(esr_el1) 396 DEFINE_U64_REG_READ_FUNC(far_el1) 397 DEFINE_U64_REG_READ_FUNC(mpidr_el1) 398 /* Alias for reading this register to avoid ifdefs in code */ 399 #define read_mpidr() read_mpidr_el1() 400 DEFINE_U64_REG_READ_FUNC(midr_el1) 401 /* Alias for reading this register to avoid ifdefs in code */ 402 #define read_midr() read_midr_el1() 403 DEFINE_U64_REG_READ_FUNC(par_el1) 404 405 DEFINE_U64_REG_WRITE_FUNC(mair_el1) 406 407 DEFINE_U64_REG_READ_FUNC(id_aa64pfr1_el1) 408 DEFINE_U64_REG_READ_FUNC(id_aa64isar1_el1) 409 DEFINE_REG_READ_FUNC_(apiakeylo, uint64_t, S3_0_c2_c1_0) 410 DEFINE_REG_READ_FUNC_(apiakeyhi, uint64_t, S3_0_c2_c1_1) 411 412 DEFINE_REG_WRITE_FUNC_(apibkeylo, uint64_t, S3_0_c2_c1_2) 413 DEFINE_REG_WRITE_FUNC_(apibkeyhi, uint64_t, S3_0_c2_c1_3) 414 415 DEFINE_REG_READ_FUNC_(apdakeylo, uint64_t, S3_0_c2_c2_0) 416 DEFINE_REG_READ_FUNC_(apdakeyhi, uint64_t, S3_0_c2_c2_1) 417 418 DEFINE_REG_WRITE_FUNC_(apdbkeylo, uint64_t, S3_0_c2_c2_2) 419 DEFINE_REG_WRITE_FUNC_(apdbkeyhi, uint64_t, S3_0_c2_c2_3) 420 421 DEFINE_REG_WRITE_FUNC_(apgakeylo, uint64_t, S3_0_c2_c3_0) 422 DEFINE_REG_WRITE_FUNC_(apgakeyhi, uint64_t, S3_0_c2_c3_1) 423 424 /* Register read/write functions for GICC registers by using system interface */ 425 DEFINE_REG_READ_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 426 DEFINE_REG_WRITE_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 427 DEFINE_REG_WRITE_FUNC_(icc_pmr, uint32_t, S3_0_C4_C6_0) 428 DEFINE_REG_READ_FUNC_(icc_iar0, uint32_t, S3_0_c12_c8_0) 429 DEFINE_REG_READ_FUNC_(icc_iar1, uint32_t, S3_0_c12_c12_0) 430 DEFINE_REG_WRITE_FUNC_(icc_eoir0, uint32_t, S3_0_c12_c8_1) 431 DEFINE_REG_WRITE_FUNC_(icc_eoir1, uint32_t, S3_0_c12_c12_1) 432 DEFINE_REG_WRITE_FUNC_(icc_igrpen0, uint32_t, S3_0_C12_C12_6) 433 DEFINE_REG_WRITE_FUNC_(icc_igrpen1, uint32_t, S3_0_C12_C12_7) 434 #endif /*__ASSEMBLER__*/ 435 436 #endif /*ARM64_H*/ 437 438