riscv: kernel: add console driver for S-Mode using SBI

Implements a generic console driver using legacy SBI extension.
This introduces a flag CFG_RISCV_SBI_CONSOLE to decide building
the driver or n

riscv: kernel: add console driver for S-Mode using SBI

Implements a generic console driver using legacy SBI extension.
This introduces a flag CFG_RISCV_SBI_CONSOLE to decide building
the driver or not. This allows using another UART driver instead.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: set author to be same as Signed-off-by:]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: kernel: sbi: add RISC-V SBI interface

Allow OP-TEE core running in S-Mode (supervisor) to interface with
Supervisor Execution Environment (SEE) through environmental calls (ecall).
Adds CFG_R

riscv: kernel: sbi: add RISC-V SBI interface

Allow OP-TEE core running in S-Mode (supervisor) to interface with
Supervisor Execution Environment (SEE) through environmental calls (ecall).
Adds CFG_RISCV_SBI flag to enable or disable it.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: set author to be same as Signed-off-by:]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: core: riscv.mk: select privilege mode of OP-TEE core

Introduce CFG_RISCV_M_MODE and CFG_RISCV_S_MODE flags to decide
in which privilege level OP-TEE OS will run, respectively, machine mode
or

riscv: core: riscv.mk: select privilege mode of OP-TEE core

Introduce CFG_RISCV_M_MODE and CFG_RISCV_S_MODE flags to decide
in which privilege level OP-TEE OS will run, respectively, machine mode
or supervisor mode.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: set author to be same as Signed-off-by:]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: kernel: spinlock.S: make __cpu_spin_trylock() visible

Function __cpu_spin_trylock() is need by trace_ext.c, therefore,
do not hide it.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp

riscv: kernel: spinlock.S: make __cpu_spin_trylock() visible

Function __cpu_spin_trylock() is need by trace_ext.c, therefore,
do not hide it.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kernel: move trace_ext.c to core/kernel

Functions in trace_ext.c are architecture independent, therefore, code
could be moved to core/kernel.

Signed-off-by: Marouene Boubakri <marouene.boubak

core: kernel: move trace_ext.c to core/kernel

Functions in trace_ext.c are architecture independent, therefore, code
could be moved to core/kernel.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: plat-spike: conf.mk: set CFG_TEE_CORE_LOG_LEVEL to default

Do not force CFG_TEE_CORE_LOG_LEVEL to zero in
core/arch/riscv/plat-spike/conf.mk

Signed-off-by: Marouene Boubakri <marouene.boubak

riscv: plat-spike: conf.mk: set CFG_TEE_CORE_LOG_LEVEL to default

Do not force CFG_TEE_CORE_LOG_LEVEL to zero in
core/arch/riscv/plat-spike/conf.mk

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: mm: tlb_helpers_rv.S: translation look-aside buffer invalidate

Implement tlbi_all(), tlbi_mva_allasid() and tlbi_asid() using supervisor
memory-management fence instruction SFENCE.VMA.

Signe

riscv: mm: tlb_helpers_rv.S: translation look-aside buffer invalidate

Implement tlbi_all(), tlbi_mva_allasid() and tlbi_asid() using supervisor
memory-management fence instruction SFENCE.VMA.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: plat-spike: conf.mk: set CFG_TEE_RAM_VA_SIZE to 4MB

Set CFG_TEE_RAM_VA_SIZE to 0x00400000 in core/arch/riscv/plat-spike/conf.mk

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
A

riscv: plat-spike: conf.mk: set CFG_TEE_RAM_VA_SIZE to 4MB

Set CFG_TEE_RAM_VA_SIZE to 0x00400000 in core/arch/riscv/plat-spike/conf.mk

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: include: riscv_macros.S: define RISC-V macro helpers

Add multiplication macro for RISC-V harts without M extension.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jer

riscv: include: riscv_macros.S: define RISC-V macro helpers

Add multiplication macro for RISC-V harts without M extension.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: kernel: add stub for tee_time_get_sys_time()

A stub implementation which returns TEE_ERROR_NOT_IMPLEMENTED for now.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jen

riscv: kernel: add stub for tee_time_get_sys_time()

A stub implementation which returns TEE_ERROR_NOT_IMPLEMENTED for now.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: kernel: idle.c: implement cpu_idle()

Required by panic() to abort current execution. It ensures memory
operations were complete and stalls the hart.

Signed-off-by: Marouene Boubakri <marouen

riscv: kernel: idle.c: implement cpu_idle()

Required by panic() to abort current execution. It ensures memory
operations were complete and stalls the hart.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: kernel: main.c: implement tee_otp_get_hw_unique_key()

Sets the hardware unique key to zero. To model OTP device, Spike introduce
the ability to write plugins in the form of shared object file

riscv: kernel: main.c: implement tee_otp_get_hw_unique_key()

Sets the hardware unique key to zero. To model OTP device, Spike introduce
the ability to write plugins in the form of shared object files that allow
user-defined Memory-Mapped-I/O behaviors.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: include: add core_mmu_arch.h

Add defines for MMU configuration and helper functions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere

riscv: include: add core_mmu_arch.h

Add defines for MMU configuration and helper functions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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riscv: include: add thread_arch.h

Minimalist version which defines contexts registers structures and
thread local structure. This to allow compiling for RISC-V architecture.

Signed-off-by: Marouene

riscv: include: add thread_arch.h

Minimalist version which defines contexts registers structures and
thread local structure. This to allow compiling for RISC-V architecture.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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riscv: include: add cache_helpers_arch.h

Nothing to define for now.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

riscv: core: define CFG_MAX_CACHE_LINE_SHIFT in riscv.mk

Define platform specific maximum cache line size in address lines.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Je

riscv: core: define CFG_MAX_CACHE_LINE_SHIFT in riscv.mk

Define platform specific maximum cache line size in address lines.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: include: cache_helpers.h: allow reusing architecture-dependent code

To allow reuse of architecture-dependent code, divide original
cache_helpers.h into two separate header files
core/$arch/inc

core: include: cache_helpers.h: allow reusing architecture-dependent code

To allow reuse of architecture-dependent code, divide original
cache_helpers.h into two separate header files
core/$arch/include/kernel/cache_helpers_arch.h and
core/include/kernel/cache_helpers.h

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
[jf: set author to be same as Signed-off-by:]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: include: kernel: add tee_l2cc_mutex.h

The tee_l2cc_mutex.h header file is required by core/mm/core_mmu.c
and core/mm/vm.c, therefore, add an empty one to pass compilation.

Signed-off-by: Mar

riscv: include: kernel: add tee_l2cc_mutex.h

The tee_l2cc_mutex.h header file is required by core/mm/core_mmu.c
and core/mm/vm.c, therefore, add an empty one to pass compilation.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: include: add misc_arch.h

Nothing to define for now.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

core: include: misc.h: divide into misc.h and misc_arch.h

get_core_pos() is architecture-independent function and could be re-used
by an arch implementation, therefore, move it to a separate header

core: include: misc.h: divide into misc.h and misc_arch.h

get_core_pos() is architecture-independent function and could be re-used
by an arch implementation, therefore, move it to a separate header file
core/include/kernel/misc.h, and, keep architecture-dependent code
in core/$arch/include/kernel/misc_arch.h

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: set author to be same as Signed-off-by:]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: add fault mitigations in ree_fs_ta_open()

Adds and enables fault mitigation in ree_fs_ta_open() to check the
signature of the TA before returning success.

Acked-by: Jerome Forissier <jerome.f

core: add fault mitigations in ree_fs_ta_open()

Adds and enables fault mitigation in ree_fs_ta_open() to check the
signature of the TA before returning success.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add fault mitigations in buf_ta_open()

Adds and enables fault mitigation in buf_ta_open() to check both the
signature of the TA and then also the hash of the TA before returning
success.

Acke

core: add fault mitigations in buf_ta_open()

Adds and enables fault mitigation in buf_ta_open() to check both the
signature of the TA and then also the hash of the TA before returning
success.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add fault mitigations to shdr_verify_signature*()

Adds fault mitigations to shdr_verify_signature() and
shdr_verify_signature2(). shdr_verify_signature() and
shdr_verify_signature2() are calle

core: add fault mitigations to shdr_verify_signature*()

Adds fault mitigations to shdr_verify_signature() and
shdr_verify_signature2(). shdr_verify_signature() and
shdr_verify_signature2() are called using the wrapper FTMN_CALL_FUNC()
which verifies that the correct function was called and that the return
value hasn't been tampered with.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: add stubbed fault mitigation in crypto_acipher_rsassa_verify()

Adds a stubbed fault mitigation for the drivers version of
crypto_acipher_rsassa_verify). End the function with FTMN_C

drivers: crypto: add stubbed fault mitigation in crypto_acipher_rsassa_verify()

Adds a stubbed fault mitigation for the drivers version of
crypto_acipher_rsassa_verify). End the function with FTMN_CALLEE_DONE()
to record that the function was indeed called and a redundant copy of
the return value.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ltc: add fault mitigation in crypto_acipher_rsassa_verify()

Adds fault mitigations in crypto_acipher_rsassa_verify() and dependent
functions in libTomCrypt in order to include the critical fin

core: ltc: add fault mitigation in crypto_acipher_rsassa_verify()

Adds fault mitigations in crypto_acipher_rsassa_verify() and dependent
functions in libTomCrypt in order to include the critical final
memcompare.

This fault mitigation is only enabled with the calling function enabled
fault mitigations and CFG_CORE_FAULT_MITIGATION is 'y'.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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