1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2021, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <config.h> 8 #include <drivers/stm32_bsec.h> 9 #include <io.h> 10 #include <kernel/delay.h> 11 #include <kernel/dt.h> 12 #include <kernel/boot.h> 13 #include <kernel/spinlock.h> 14 #include <libfdt.h> 15 #include <limits.h> 16 #include <mm/core_memprot.h> 17 #include <platform_config.h> 18 #include <stm32_util.h> 19 #include <string.h> 20 #include <tee_api_defines.h> 21 #include <types_ext.h> 22 #include <util.h> 23 24 #define BSEC_OTP_MASK GENMASK_32(4, 0) 25 #define BSEC_OTP_BANK_SHIFT U(5) 26 27 /* Permanent lock bitmasks */ 28 #define DATA_LOWER_OTP_PERLOCK_BIT U(3) 29 #define DATA_UPPER_OTP_PERLOCK_BIT U(1) 30 31 /* BSEC register offset */ 32 #define BSEC_OTP_CONF_OFF U(0x000) 33 #define BSEC_OTP_CTRL_OFF U(0x004) 34 #define BSEC_OTP_WRDATA_OFF U(0x008) 35 #define BSEC_OTP_STATUS_OFF U(0x00C) 36 #define BSEC_OTP_LOCK_OFF U(0x010) 37 #define BSEC_DEN_OFF U(0x014) 38 #define BSEC_FEN_OFF U(0x018) 39 #define BSEC_DISTURBED_OFF U(0x01C) 40 #define BSEC_DISTURBED1_OFF U(0x020) 41 #define BSEC_DISTURBED2_OFF U(0x024) 42 #define BSEC_ERROR_OFF U(0x034) 43 #define BSEC_ERROR1_OFF U(0x038) 44 #define BSEC_ERROR2_OFF U(0x03C) 45 #define BSEC_WRLOCK_OFF U(0x04C) 46 #define BSEC_WRLOCK1_OFF U(0x050) 47 #define BSEC_WRLOCK2_OFF U(0x054) 48 #define BSEC_SPLOCK_OFF U(0x064) 49 #define BSEC_SPLOCK1_OFF U(0x068) 50 #define BSEC_SPLOCK2_OFF U(0x06C) 51 #define BSEC_SWLOCK_OFF U(0x07C) 52 #define BSEC_SWLOCK1_OFF U(0x080) 53 #define BSEC_SWLOCK2_OFF U(0x084) 54 #define BSEC_SRLOCK_OFF U(0x094) 55 #define BSEC_SRLOCK1_OFF U(0x098) 56 #define BSEC_SRLOCK2_OFF U(0x09C) 57 #define BSEC_JTAG_IN_OFF U(0x0AC) 58 #define BSEC_JTAG_OUT_OFF U(0x0B0) 59 #define BSEC_SCRATCH_OFF U(0x0B4) 60 #define BSEC_OTP_DATA_OFF U(0x200) 61 #define BSEC_IPHW_CFG_OFF U(0xFF0) 62 #define BSEC_IPVR_OFF U(0xFF4) 63 #define BSEC_IP_ID_OFF U(0xFF8) 64 #define BSEC_IP_MAGIC_ID_OFF U(0xFFC) 65 66 /* BSEC_CONFIGURATION Register */ 67 #define BSEC_CONF_POWER_UP_MASK BIT(0) 68 #define BSEC_CONF_POWER_UP_SHIFT U(0) 69 #define BSEC_CONF_FRQ_MASK GENMASK_32(2, 1) 70 #define BSEC_CONF_FRQ_SHIFT U(1) 71 #define BSEC_CONF_PRG_WIDTH_MASK GENMASK_32(6, 3) 72 #define BSEC_CONF_PRG_WIDTH_SHIFT U(3) 73 #define BSEC_CONF_TREAD_MASK GENMASK_32(8, 7) 74 #define BSEC_CONF_TREAD_SHIFT U(7) 75 76 /* BSEC_CONTROL Register */ 77 #define BSEC_READ U(0x000) 78 #define BSEC_WRITE U(0x100) 79 #define BSEC_LOCK U(0x200) 80 81 /* BSEC_STATUS Register */ 82 #define BSEC_MODE_STATUS_MASK GENMASK_32(2, 0) 83 #define BSEC_MODE_BUSY_MASK BIT(3) 84 #define BSEC_MODE_PROGFAIL_MASK BIT(4) 85 #define BSEC_MODE_PWR_MASK BIT(5) 86 #define BSEC_MODE_BIST1_LOCK_MASK BIT(6) 87 #define BSEC_MODE_BIST2_LOCK_MASK BIT(7) 88 89 /* 90 * OTP Lock services definition 91 * Value must corresponding to the bit position in the register 92 */ 93 #define BSEC_LOCK_UPPER_OTP U(0x00) 94 #define BSEC_LOCK_DEBUG U(0x02) 95 #define BSEC_LOCK_PROGRAM U(0x04) 96 97 /* Timeout when polling on status */ 98 #define BSEC_TIMEOUT_US U(10000) 99 100 struct bsec_dev { 101 struct io_pa_va base; 102 unsigned int upper_base; 103 unsigned int max_id; 104 uint32_t *nsec_access; 105 }; 106 107 /* Only 1 instance of BSEC is expected per platform */ 108 static struct bsec_dev bsec_dev; 109 110 /* BSEC access protection */ 111 static unsigned int lock = SPINLOCK_UNLOCK; 112 113 static uint32_t bsec_lock(void) 114 { 115 return may_spin_lock(&lock); 116 } 117 118 static void bsec_unlock(uint32_t exceptions) 119 { 120 may_spin_unlock(&lock, exceptions); 121 } 122 123 static uint32_t otp_max_id(void) 124 { 125 return bsec_dev.max_id; 126 } 127 128 static uint32_t otp_upper_base(void) 129 { 130 return bsec_dev.upper_base; 131 } 132 133 static uint32_t otp_bank_offset(uint32_t otp_id) 134 { 135 assert(otp_id <= otp_max_id()); 136 137 return ((otp_id & ~BSEC_OTP_MASK) >> BSEC_OTP_BANK_SHIFT) * 138 sizeof(uint32_t); 139 } 140 141 static vaddr_t bsec_base(void) 142 { 143 return io_pa_or_va_secure(&bsec_dev.base, BSEC_IP_MAGIC_ID_OFF + 1); 144 } 145 146 static uint32_t bsec_status(void) 147 { 148 return io_read32(bsec_base() + BSEC_OTP_STATUS_OFF); 149 } 150 151 /* 152 * Check that BSEC interface does not report an error 153 * @otp_id : OTP number 154 * @check_disturbed: check only error (false) or all sources (true) 155 * Return a TEE_Result compliant value 156 */ 157 static TEE_Result check_no_error(uint32_t otp_id, bool check_disturbed) 158 { 159 uint32_t bit = BIT(otp_id & BSEC_OTP_MASK); 160 uint32_t bank = otp_bank_offset(otp_id); 161 162 if (io_read32(bsec_base() + BSEC_ERROR_OFF + bank) & bit) 163 return TEE_ERROR_GENERIC; 164 165 if (check_disturbed && 166 io_read32(bsec_base() + BSEC_DISTURBED_OFF + bank) & bit) 167 return TEE_ERROR_GENERIC; 168 169 return TEE_SUCCESS; 170 } 171 172 static TEE_Result power_up_safmem(void) 173 { 174 uint64_t timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 175 176 io_mask32(bsec_base() + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP_MASK, 177 BSEC_CONF_POWER_UP_MASK); 178 179 /* 180 * If a timeout is detected, test the condition again to consider 181 * cases where timeout is due to the executing TEE thread rescheduling. 182 */ 183 while (!timeout_elapsed(timeout_ref)) 184 if (bsec_status() & BSEC_MODE_PWR_MASK) 185 break; 186 187 if (bsec_status() & BSEC_MODE_PWR_MASK) 188 return TEE_SUCCESS; 189 190 return TEE_ERROR_GENERIC; 191 } 192 193 static TEE_Result power_down_safmem(void) 194 { 195 uint64_t timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 196 197 io_mask32(bsec_base() + BSEC_OTP_CONF_OFF, 0, BSEC_CONF_POWER_UP_MASK); 198 199 /* 200 * If a timeout is detected, test the condition again to consider 201 * cases where timeout is due to the executing TEE thread rescheduling. 202 */ 203 while (!timeout_elapsed(timeout_ref)) 204 if (!(bsec_status() & BSEC_MODE_PWR_MASK)) 205 break; 206 207 if (!(bsec_status() & BSEC_MODE_PWR_MASK)) 208 return TEE_SUCCESS; 209 210 return TEE_ERROR_GENERIC; 211 } 212 213 TEE_Result stm32_bsec_shadow_register(uint32_t otp_id) 214 { 215 TEE_Result result = 0; 216 uint32_t exceptions = 0; 217 uint64_t timeout_ref = 0; 218 bool locked = false; 219 220 /* Check if shadowing of OTP is locked, informative only */ 221 result = stm32_bsec_read_sr_lock(otp_id, &locked); 222 if (result) 223 return result; 224 225 if (locked) 226 DMSG("BSEC shadow warning: OTP locked"); 227 228 exceptions = bsec_lock(); 229 230 result = power_up_safmem(); 231 if (result) 232 goto out; 233 234 io_write32(bsec_base() + BSEC_OTP_CTRL_OFF, otp_id | BSEC_READ); 235 236 timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 237 while (!timeout_elapsed(timeout_ref)) 238 if (!(bsec_status() & BSEC_MODE_BUSY_MASK)) 239 break; 240 241 if (bsec_status() & BSEC_MODE_BUSY_MASK) 242 result = TEE_ERROR_BUSY; 243 else 244 result = check_no_error(otp_id, true /* check-disturbed */); 245 246 power_down_safmem(); 247 248 out: 249 bsec_unlock(exceptions); 250 251 return result; 252 } 253 254 TEE_Result stm32_bsec_read_otp(uint32_t *value, uint32_t otp_id) 255 { 256 if (otp_id > otp_max_id()) 257 return TEE_ERROR_BAD_PARAMETERS; 258 259 *value = io_read32(bsec_base() + BSEC_OTP_DATA_OFF + 260 (otp_id * sizeof(uint32_t))); 261 262 return TEE_SUCCESS; 263 } 264 265 TEE_Result stm32_bsec_shadow_read_otp(uint32_t *otp_value, uint32_t otp_id) 266 { 267 TEE_Result result = 0; 268 269 result = stm32_bsec_shadow_register(otp_id); 270 if (result) { 271 EMSG("BSEC %"PRIu32" Shadowing Error %#"PRIx32, otp_id, result); 272 return result; 273 } 274 275 result = stm32_bsec_read_otp(otp_value, otp_id); 276 if (result) 277 EMSG("BSEC %"PRIu32" Read Error %#"PRIx32, otp_id, result); 278 279 return result; 280 } 281 282 TEE_Result stm32_bsec_write_otp(uint32_t value, uint32_t otp_id) 283 { 284 TEE_Result result = 0; 285 uint32_t exceptions = 0; 286 vaddr_t otp_data_base = bsec_base() + BSEC_OTP_DATA_OFF; 287 bool locked = false; 288 289 /* Check if write of OTP is locked, informative only */ 290 result = stm32_bsec_read_sw_lock(otp_id, &locked); 291 if (result) 292 return result; 293 294 if (locked) 295 DMSG("BSEC write warning: OTP locked"); 296 297 exceptions = bsec_lock(); 298 299 io_write32(otp_data_base + (otp_id * sizeof(uint32_t)), value); 300 301 bsec_unlock(exceptions); 302 303 return TEE_SUCCESS; 304 } 305 306 #ifdef CFG_STM32_BSEC_WRITE 307 TEE_Result stm32_bsec_program_otp(uint32_t value, uint32_t otp_id) 308 { 309 TEE_Result result = 0; 310 uint32_t exceptions = 0; 311 uint64_t timeout_ref = 0; 312 bool locked = false; 313 314 /* Check if shadowing of OTP is locked, informative only */ 315 result = stm32_bsec_read_sp_lock(otp_id, &locked); 316 if (result) 317 return result; 318 319 if (locked) 320 DMSG("BSEC program warning: OTP locked"); 321 322 if (io_read32(bsec_base() + BSEC_OTP_LOCK_OFF) & BIT(BSEC_LOCK_PROGRAM)) 323 DMSG("BSEC program warning: GPLOCK activated"); 324 325 exceptions = bsec_lock(); 326 327 result = power_up_safmem(); 328 if (result) 329 goto out; 330 331 io_write32(bsec_base() + BSEC_OTP_WRDATA_OFF, value); 332 io_write32(bsec_base() + BSEC_OTP_CTRL_OFF, otp_id | BSEC_WRITE); 333 334 timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 335 while (!timeout_elapsed(timeout_ref)) 336 if (!(bsec_status() & BSEC_MODE_BUSY_MASK)) 337 break; 338 339 if (bsec_status() & BSEC_MODE_BUSY_MASK) 340 result = TEE_ERROR_BUSY; 341 else if (bsec_status() & BSEC_MODE_PROGFAIL_MASK) 342 result = TEE_ERROR_BAD_PARAMETERS; 343 else 344 result = check_no_error(otp_id, true /* check-disturbed */); 345 346 power_down_safmem(); 347 348 out: 349 bsec_unlock(exceptions); 350 351 return result; 352 } 353 #endif /*CFG_STM32_BSEC_WRITE*/ 354 355 TEE_Result stm32_bsec_permanent_lock_otp(uint32_t otp_id) 356 { 357 TEE_Result result = 0; 358 uint32_t data = 0; 359 uint32_t addr = 0; 360 uint32_t exceptions = 0; 361 vaddr_t base = bsec_base(); 362 uint64_t timeout_ref = 0; 363 uint32_t upper_base = otp_upper_base(); 364 365 if (otp_id > otp_max_id()) 366 return TEE_ERROR_BAD_PARAMETERS; 367 368 /* 369 * 2 bits per words for lower OTPs: 2:1 Redundancy 370 * 1 bit per word for upper OTPs : ECC support 371 * e.g with 32 lower and 64 upper OTPs: 372 * OTP word to be ADDR[6:0] WRDATA[31:0] 373 * locked 374 * 0 0x00 0x0000 0003 375 * 1 0x00 0x0000 000C 376 * ... ... ... 377 * 7 0x00 0x0000 C000 378 * 8 0x01 0x0000 0003 379 * ... ... ... 380 * 31 0x03 0x0000 C000 381 * 32 0x04 0x0000 0001 382 * 33 0x04 0x0000 0002 383 * 95 0x07 0x0000 8000 384 */ 385 if (otp_id < upper_base) { 386 addr = otp_id / 8U; 387 data = DATA_LOWER_OTP_PERLOCK_BIT << ((otp_id * 2U) & 0xF); 388 } else { 389 addr = upper_base / 8U + (otp_id - upper_base) / 16U; 390 data = DATA_UPPER_OTP_PERLOCK_BIT << (otp_id & 0xF); 391 } 392 393 exceptions = bsec_lock(); 394 395 result = power_up_safmem(); 396 if (result) 397 goto out; 398 399 io_write32(base + BSEC_OTP_WRDATA_OFF, data); 400 io_write32(base + BSEC_OTP_CTRL_OFF, addr | BSEC_WRITE | BSEC_LOCK); 401 402 timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 403 while (!timeout_elapsed(timeout_ref)) 404 if (!(bsec_status() & BSEC_MODE_BUSY_MASK)) 405 break; 406 407 if (bsec_status() & BSEC_MODE_BUSY_MASK) 408 result = TEE_ERROR_BUSY; 409 else if (bsec_status() & BSEC_MODE_PROGFAIL_MASK) 410 result = TEE_ERROR_BAD_PARAMETERS; 411 else 412 result = check_no_error(otp_id, false /* not-disturbed */); 413 414 power_down_safmem(); 415 416 out: 417 bsec_unlock(exceptions); 418 419 return result; 420 } 421 422 #ifdef CFG_STM32_BSEC_WRITE 423 TEE_Result stm32_bsec_write_debug_conf(uint32_t value) 424 { 425 TEE_Result result = TEE_ERROR_GENERIC; 426 uint32_t exceptions = 0; 427 428 exceptions = bsec_lock(); 429 430 io_write32(bsec_base() + BSEC_DEN_OFF, value); 431 432 if ((io_read32(bsec_base() + BSEC_DEN_OFF) ^ value) == 0U) 433 result = TEE_SUCCESS; 434 435 bsec_unlock(exceptions); 436 437 return result; 438 } 439 #endif /*CFG_STM32_BSEC_WRITE*/ 440 441 uint32_t stm32_bsec_read_debug_conf(void) 442 { 443 return io_read32(bsec_base() + BSEC_DEN_OFF); 444 } 445 446 static TEE_Result set_bsec_lock(uint32_t otp_id, size_t lock_offset) 447 { 448 uint32_t bank = otp_bank_offset(otp_id); 449 uint32_t otp_mask = BIT(otp_id & BSEC_OTP_MASK); 450 vaddr_t lock_addr = bsec_base() + bank + lock_offset; 451 uint32_t exceptions = 0; 452 453 if (otp_id > STM32MP1_OTP_MAX_ID) 454 return TEE_ERROR_BAD_PARAMETERS; 455 456 exceptions = bsec_lock(); 457 458 io_write32(lock_addr, otp_mask); 459 460 bsec_unlock(exceptions); 461 462 return TEE_SUCCESS; 463 } 464 465 TEE_Result stm32_bsec_set_sr_lock(uint32_t otp_id) 466 { 467 return set_bsec_lock(otp_id, BSEC_SRLOCK_OFF); 468 } 469 470 TEE_Result stm32_bsec_set_sw_lock(uint32_t otp_id) 471 { 472 return set_bsec_lock(otp_id, BSEC_SWLOCK_OFF); 473 } 474 475 TEE_Result stm32_bsec_set_sp_lock(uint32_t otp_id) 476 { 477 return set_bsec_lock(otp_id, BSEC_SPLOCK_OFF); 478 } 479 480 static TEE_Result read_bsec_lock(uint32_t otp_id, bool *locked, 481 size_t lock_offset) 482 { 483 uint32_t bank = otp_bank_offset(otp_id); 484 uint32_t otp_mask = BIT(otp_id & BSEC_OTP_MASK); 485 vaddr_t lock_addr = bsec_base() + bank + lock_offset; 486 487 if (otp_id > STM32MP1_OTP_MAX_ID) 488 return TEE_ERROR_BAD_PARAMETERS; 489 490 *locked = (io_read32(lock_addr) & otp_mask) != 0; 491 492 return TEE_SUCCESS; 493 } 494 495 TEE_Result stm32_bsec_read_sr_lock(uint32_t otp_id, bool *locked) 496 { 497 return read_bsec_lock(otp_id, locked, BSEC_SRLOCK_OFF); 498 } 499 500 TEE_Result stm32_bsec_read_sw_lock(uint32_t otp_id, bool *locked) 501 { 502 return read_bsec_lock(otp_id, locked, BSEC_SWLOCK_OFF); 503 } 504 505 TEE_Result stm32_bsec_read_sp_lock(uint32_t otp_id, bool *locked) 506 { 507 return read_bsec_lock(otp_id, locked, BSEC_SPLOCK_OFF); 508 } 509 510 TEE_Result stm32_bsec_read_permanent_lock(uint32_t otp_id, bool *locked) 511 { 512 return read_bsec_lock(otp_id, locked, BSEC_WRLOCK_OFF); 513 } 514 515 TEE_Result stm32_bsec_otp_lock(uint32_t service) 516 { 517 vaddr_t addr = bsec_base() + BSEC_OTP_LOCK_OFF; 518 519 switch (service) { 520 case BSEC_LOCK_UPPER_OTP: 521 io_write32(addr, BIT(BSEC_LOCK_UPPER_OTP)); 522 break; 523 case BSEC_LOCK_DEBUG: 524 io_write32(addr, BIT(BSEC_LOCK_DEBUG)); 525 break; 526 case BSEC_LOCK_PROGRAM: 527 io_write32(addr, BIT(BSEC_LOCK_PROGRAM)); 528 break; 529 default: 530 return TEE_ERROR_BAD_PARAMETERS; 531 } 532 533 return TEE_SUCCESS; 534 } 535 536 static size_t nsec_access_array_size(void) 537 { 538 size_t upper_count = otp_max_id() - otp_upper_base() + 1; 539 540 return ROUNDUP_DIV(upper_count, BSEC_BITS_PER_WORD); 541 } 542 543 static bool nsec_access_granted(unsigned int index) 544 { 545 uint32_t *array = bsec_dev.nsec_access; 546 547 return array && 548 (index / BSEC_BITS_PER_WORD) < nsec_access_array_size() && 549 array[index / BSEC_BITS_PER_WORD] & 550 BIT(index % BSEC_BITS_PER_WORD); 551 } 552 553 bool stm32_bsec_nsec_can_access_otp(uint32_t otp_id) 554 { 555 return otp_id < otp_upper_base() || 556 nsec_access_granted(otp_id - otp_upper_base()); 557 } 558 559 struct nvmem_layout { 560 char *name; 561 uint32_t otp_id; 562 size_t bit_len; 563 }; 564 565 static struct nvmem_layout *nvmem_layout; 566 static size_t nvmem_layout_count; 567 568 TEE_Result stm32_bsec_find_otp_in_nvmem_layout(const char *name, 569 uint32_t *otp_id, 570 size_t *otp_bit_len) 571 { 572 size_t i = 0; 573 574 if (!name) 575 return TEE_ERROR_BAD_PARAMETERS; 576 577 for (i = 0; i < nvmem_layout_count; i++) { 578 if (!nvmem_layout[i].name || strcmp(name, nvmem_layout[i].name)) 579 continue; 580 581 if (otp_id) 582 *otp_id = nvmem_layout[i].otp_id; 583 584 if (otp_bit_len) 585 *otp_bit_len = nvmem_layout[i].bit_len; 586 587 DMSG("nvmem %s = %zu: %"PRId32" %zu", name, i, 588 nvmem_layout[i].otp_id, nvmem_layout[i].bit_len); 589 590 return TEE_SUCCESS; 591 } 592 593 DMSG("nvmem %s failed", name); 594 595 return TEE_ERROR_ITEM_NOT_FOUND; 596 } 597 598 #ifdef CFG_EMBED_DTB 599 static void enable_nsec_access(unsigned int otp_id) 600 { 601 unsigned int idx = (otp_id - otp_upper_base()) / BSEC_BITS_PER_WORD; 602 603 if (otp_id < otp_upper_base()) 604 return; 605 606 if (otp_id > otp_max_id() || stm32_bsec_shadow_register(otp_id)) 607 panic(); 608 609 bsec_dev.nsec_access[idx] |= BIT(otp_id % BSEC_BITS_PER_WORD); 610 } 611 612 static void bsec_dt_otp_nsec_access(void *fdt, int bsec_node) 613 { 614 int bsec_subnode = 0; 615 616 bsec_dev.nsec_access = calloc(nsec_access_array_size(), 617 sizeof(*bsec_dev.nsec_access)); 618 if (!bsec_dev.nsec_access) 619 panic(); 620 621 fdt_for_each_subnode(bsec_subnode, fdt, bsec_node) { 622 unsigned int reg_offset = 0; 623 unsigned int reg_size = 0; 624 unsigned int otp_id = 0; 625 unsigned int i = 0; 626 size_t size = 0; 627 628 reg_offset = _fdt_reg_base_address(fdt, bsec_subnode); 629 reg_size = _fdt_reg_size(fdt, bsec_subnode); 630 631 assert(reg_offset != DT_INFO_INVALID_REG && 632 reg_size != DT_INFO_INVALID_REG_SIZE); 633 634 otp_id = reg_offset / sizeof(uint32_t); 635 636 if (otp_id < STM32MP1_UPPER_OTP_START) { 637 unsigned int otp_end = 638 ROUNDUP_DIV(reg_offset + reg_size, 639 sizeof(uint32_t)); 640 641 if (otp_end > STM32MP1_UPPER_OTP_START) { 642 /* 643 * OTP crosses Lower/Upper boundary, consider 644 * only the upper part. 645 */ 646 otp_id = STM32MP1_UPPER_OTP_START; 647 reg_size -= (STM32MP1_UPPER_OTP_START * 648 sizeof(uint32_t)) - reg_offset; 649 reg_offset = STM32MP1_UPPER_OTP_START * 650 sizeof(uint32_t); 651 652 DMSG("OTP crosses Lower/Upper boundary"); 653 } else { 654 continue; 655 } 656 } 657 658 if (!fdt_getprop(fdt, bsec_subnode, "st,non-secure-otp", NULL)) 659 continue; 660 661 if ((reg_offset % sizeof(uint32_t)) || 662 (reg_size % sizeof(uint32_t))) 663 panic("Unaligned non-secure OTP"); 664 665 size = reg_size / sizeof(uint32_t); 666 667 if (otp_id + size > STM32MP1_OTP_MAX_ID) 668 panic("OTP range oversized"); 669 670 for (i = otp_id; i < otp_id + size; i++) 671 enable_nsec_access(i); 672 } 673 } 674 675 static void save_dt_nvmem_layout(void *fdt, int bsec_node) 676 { 677 int cell_max = 0; 678 int cell_cnt = 0; 679 int node = 0; 680 681 fdt_for_each_subnode(node, fdt, bsec_node) 682 cell_max++; 683 if (!cell_max) 684 return; 685 686 nvmem_layout = calloc(cell_max, sizeof(*nvmem_layout)); 687 if (!nvmem_layout) 688 panic(); 689 690 fdt_for_each_subnode(node, fdt, bsec_node) { 691 unsigned int reg_offset = 0; 692 unsigned int reg_length = 0; 693 const char *string = NULL; 694 const char *s = NULL; 695 int len = 0; 696 struct nvmem_layout *layout_cell = &nvmem_layout[cell_cnt]; 697 698 string = fdt_get_name(fdt, node, &len); 699 if (!string || !len) 700 continue; 701 702 reg_offset = _fdt_reg_base_address(fdt, node); 703 reg_length = _fdt_reg_size(fdt, node); 704 705 if (reg_offset == DT_INFO_INVALID_REG || 706 reg_length == DT_INFO_INVALID_REG_SIZE) { 707 DMSG("Malformed nvmem %s: ignored", string); 708 continue; 709 } 710 711 if (reg_offset % sizeof(uint32_t)) { 712 DMSG("Misaligned nvmem %s: ignored", string); 713 continue; 714 } 715 layout_cell->otp_id = reg_offset / sizeof(uint32_t); 716 layout_cell->bit_len = reg_length * CHAR_BIT; 717 718 s = strchr(string, '@'); 719 if (s) 720 len = s - string; 721 722 layout_cell->name = strndup(string, len); 723 if (!layout_cell->name) 724 panic(); 725 cell_cnt++; 726 DMSG("nvmem[%d] = %s %"PRId32" %zu", cell_cnt, 727 layout_cell->name, layout_cell->otp_id, 728 layout_cell->bit_len); 729 } 730 731 if (cell_cnt != cell_max) { 732 nvmem_layout = realloc(nvmem_layout, 733 cell_cnt * sizeof(*nvmem_layout)); 734 if (!nvmem_layout) 735 panic(); 736 } 737 738 nvmem_layout_count = cell_cnt; 739 } 740 741 static void initialize_bsec_from_dt(void) 742 { 743 void *fdt = NULL; 744 int node = 0; 745 struct dt_node_info bsec_info = { }; 746 747 fdt = get_embedded_dt(); 748 node = fdt_node_offset_by_compatible(fdt, 0, "st,stm32mp15-bsec"); 749 if (node < 0) 750 panic(); 751 752 _fdt_fill_device_info(fdt, &bsec_info, node); 753 754 if (bsec_info.reg != bsec_dev.base.pa || 755 !(bsec_info.status & DT_STATUS_OK_SEC)) 756 panic(); 757 758 bsec_dt_otp_nsec_access(fdt, node); 759 760 save_dt_nvmem_layout(fdt, node); 761 } 762 #else 763 static void initialize_bsec_from_dt(void) 764 { 765 } 766 #endif /*CFG_EMBED_DTB*/ 767 768 static TEE_Result initialize_bsec(void) 769 { 770 struct stm32_bsec_static_cfg cfg = { }; 771 772 stm32mp_get_bsec_static_cfg(&cfg); 773 774 bsec_dev.base.pa = cfg.base; 775 bsec_dev.upper_base = cfg.upper_start; 776 bsec_dev.max_id = cfg.max_id; 777 778 if (IS_ENABLED(CFG_EMBED_DTB)) 779 initialize_bsec_from_dt(); 780 781 return TEE_SUCCESS; 782 } 783 784 early_init(initialize_bsec); 785