core: riscv: sbi.h: expose sbi_ecall helper in public header

Move `sbi_ecall()` and `struct sbiret` to sbi.h to allow reuse across
individual SBI extension implementations. This prepares for modular

core: riscv: sbi.h: expose sbi_ecall helper in public header

Move `sbi_ecall()` and `struct sbiret` to sbi.h to allow reuse across
individual SBI extension implementations. This prepares for modularizing
each SBI extension (e.g., HSM, MPXY) into its own file while
centralizing the ecall interface.

Removes the now-duplicated inline definition from sbi.c.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: sbi.h: add SBI_EXT_MPXY definition

Added `SBI_EXT_MPXY` (0x4D505859) as per latest RISC-V SBI extensions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvi

core: riscv: sbi.h: add SBI_EXT_MPXY definition

Added `SBI_EXT_MPXY` (0x4D505859) as per latest RISC-V SBI extensions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: sbi.h: extend SBI error codes

Add more SBI error codes to synchronize with SBI specification.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alv

core: riscv: sbi.h: extend SBI error codes

Add more SBI error codes to synchronize with SBI specification.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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plat-vexpress: add QEMU sbsa-ref platform

Add support for the QEMU sbsa-ref platform. This platform is similar to
the QEMU virt platform, but with different memory configuration and
device addresses

plat-vexpress: add QEMU sbsa-ref platform

Add support for the QEMU sbsa-ref platform. This platform is similar to
the QEMU virt platform, but with different memory configuration and
device addresses.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: discover non-secure memory from manifest

If an FF-A manifest is available, try to discover non-secure memory from
the manifest.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: ffa: discover non-secure memory from manifest

If an FF-A manifest is available, try to discover non-secure memory from
the manifest.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: tpm: fix TPM log address parsing to use full 64-bit address

Remove ARM32-specific address parsing that only used the lower 32 bits
of the TPM event log address. ARM32 systems can have 64-bit p

core: tpm: fix TPM log address parsing to use full 64-bit address

Remove ARM32-specific address parsing that only used the lower 32 bits
of the TPM event log address. ARM32 systems can have 64-bit physical
addresses, so the full 64-bit address from the device tree property
should be parsed regardless of architecture.

The fix ensures both ARM32 and ARM64 architectures use the same
64-bit address construction: (property[0] << 32) | property[1],
preventing potential address truncation issues on ARM32 systems
with 64-bit physical address spaces.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: tpm: fix TPM log area zeroing condition to avoid manifest DT write fault

Change the condition for zeroing TPM event log address in device tree
from CFG_CORE_SEL1_SPMC to CFG_CORE_FFA. When CFG

core: tpm: fix TPM log area zeroing condition to avoid manifest DT write fault

Change the condition for zeroing TPM event log address in device tree
from CFG_CORE_SEL1_SPMC to CFG_CORE_FFA. When CFG_CORE_FFA is enabled,
the device tree comes from the manifest DT which is mapped as read-only,
not from the external device tree. Attempting to zero the
tpm_event_log_addr property in the manifest DT would cause a write
permission fault exception.

The fix prevents this fault by ensuring the zeroing operation only occurs
when using the external device tree (CFG_CORE_FFA=n), where write access
is permitted.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: boot: fix TPM log area mapping to use correct device tree source

Change the conditional compilation for TPM log area mapping from
CFG_CORE_SEL1_SPMC to CFG_CORE_FFA. This ensures the correct d

core: boot: fix TPM log area mapping to use correct device tree source

Change the conditional compilation for TPM log area mapping from
CFG_CORE_SEL1_SPMC to CFG_CORE_FFA. This ensures the correct device
tree source is used:

- When CFG_CORE_FFA is enabled: use manifest DT (get_manifest_dt())
- When CFG_CORE_FFA is disabled: use external DT (get_external_dt())

The fix aligns the device tree source selection with the broader FFA
configuration, ensuring TPM log area mapping works correctly across
all FFA-enabled platforms regardless of the specific SPMC variant
(S-EL1, S-EL2, or EL3).

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: mx8mp_phyboard_pollux: reduce DDR_SIZE

Set pollux CFG_DDR_SIZE to 1GiB to let the conf.mk automatically set the
TZDRAM_START (to a valid address for 1GiB variants).

Acked-by: Sahil Malho

core: imx: mx8mp_phyboard_pollux: reduce DDR_SIZE

Set pollux CFG_DDR_SIZE to 1GiB to let the conf.mk automatically set the
TZDRAM_START (to a valid address for 1GiB variants).

Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>

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core: imx: add imx8mp-libra-fpsc

The Libra i.MX 8M Plus FPSC is a development board utilizing the FPSC
standard paired with the i.MX 8M Plus FPSC System-on-Module [1].
It shares RAM configuration wi

core: imx: add imx8mp-libra-fpsc

The Libra i.MX 8M Plus FPSC is a development board utilizing the FPSC
standard paired with the i.MX 8M Plus FPSC System-on-Module [1].
It shares RAM configuration with the phyBOARD-Pollux i.MX 8M Plus of
1-4GiB.
Set pollux CFG_DDR_SIZE to 1GiB to let the conf.mk automatically set the
TZDRAM_START (to a valid address for 1GiB variants).

Link: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/ [1]
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>

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plat-imx: add phytec imx8mm based boards

phyGATE-Tauri-L i.MX 8M Mini [1] and phyBOARD-Polis i.MX8M Mini [2] are
SBCs based on the i.MX 8M Mini SoC. Add the boards to the
mx8mm-flavorlist and set bo

plat-imx: add phytec imx8mm based boards

phyGATE-Tauri-L i.MX 8M Mini [1] and phyBOARD-Polis i.MX8M Mini [2] are
SBCs based on the i.MX 8M Mini SoC. Add the boards to the
mx8mm-flavorlist and set board specific configs.
phyGATE-Tauri-L has 2 GiB of main memory, while phyBOARD-Polis has
1-4GiB depending on variant of the System-on-Module populated on the
board.

Link: https://www.phytec.eu/en/produkte/fertige-geraete-oem/phygate-tauri-l/ [1]
Link: https://www.phytec.eu/en/produkte/single-board-computer/phyboard-polis-imx8m-mini/ [2]
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>

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core: asan: mark redzones as inaccessible for globals

For read-only globals (e.g. in .rodata), ASan marks the entire region as
accessible. This could hide buffer overflows, if redzones are not used.

core: asan: mark redzones as inaccessible for globals

For read-only globals (e.g. in .rodata), ASan marks the entire region as
accessible. This could hide buffer overflows, if redzones are not used.

Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add ASan test for read-only global overflow

Adds a test case that triggers an out-of-bounds read on a read-only
global buffer to verify that ASan properly detects overflows on .rodata.

Signed

core: add ASan test for read-only global overflow

Adds a test case that triggers an out-of-bounds read on a read-only
global buffer to verify that ASan properly detects overflows on .rodata.

Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Add TRNG driver support in AM62L

AM62L contains the EIP76D TRNG IP which was also present in the previous
K3 devices inside the SA2UL accelerator, so the same driver is being
re-us

plat-k3: drivers: Add TRNG driver support in AM62L

AM62L contains the EIP76D TRNG IP which was also present in the previous
K3 devices inside the SA2UL accelerator, so the same driver is being
re-used here. But the AM62L does not have SA2UL. The SoC specific
configurations are being set here for AM62L for enabling TRNG.

Signed-off-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Move RNG platform error from SA2UL to RNG defines

The error define for RNG base address being not defined for a platform
when software PRNG is disabled, is currently handled as a c

plat-k3: drivers: Move RNG platform error from SA2UL to RNG defines

The error define for RNG base address being not defined for a platform
when software PRNG is disabled, is currently handled as a case with
SA2UL platform config definitions. This is not appropriate as RNG is not
needed to be tied up to SA2UL. Moving it to be placed with RNG platform
configs where it is more apt.

Signed-off-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Refactor SA2UL driver

The EIP76D TRNG IP being used in current K3 devices is not unique to
SA2UL/SA3UL. The RNG driver can be reused in other devices containing
the same TRNG IP ou

plat-k3: drivers: Refactor SA2UL driver

The EIP76D TRNG IP being used in current K3 devices is not unique to
SA2UL/SA3UL. The RNG driver can be reused in other devices containing
the same TRNG IP outside of SA2UL/SA3UL.

Refactor the SA2UL and RNG driver to make EIP76D TRNG driver independent
of SA2UL.

Signed-off-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: qemu-v8: fix CFG_CORE_CLUSTER_SHIFT

QEMU virt puts 8 or 16 CPUs in each cluster, depending on the GIC
configuration [1]. So set CFG_CORE_CLUSTER_SHIFT to match the GIC
configuration t

plat-vexpress: qemu-v8: fix CFG_CORE_CLUSTER_SHIFT

QEMU virt puts 8 or 16 CPUs in each cluster, depending on the GIC
configuration [1]. So set CFG_CORE_CLUSTER_SHIFT to match the GIC
configuration to calculate core position correctly for more than 16
CPUs.

Link: https://gitlab.com/qemu-project/qemu/-/blob/v10.0.0/hw/arm/virt.c?ref_type=tags#L1785-1789 [1]
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)

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dts: stm32: add stm32mp257f-dk board support

Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC,
with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo,
DSI HDMI, LV

dts: stm32: add stm32mp257f-dk board support

Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC,
with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo,
DSI HDMI, LVDS connector ...

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: conf: add stm32mp257f-dk board support

Add support for the stm32mp257f-dk board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thom

plat-stm32mp2: conf: add stm32mp257f-dk board support

Add support for the stm32mp257f-dk board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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core: drivers: allow to configure RIF for GPIO not on the SoC package

The number of GPIO physically accessible depends on package.
Some GPIO pins might not be accessible but it is still possible to

core: drivers: allow to configure RIF for GPIO not on the SoC package

The number of GPIO physically accessible depends on package.
Some GPIO pins might not be accessible but it is still possible to write
RIF registers to block access.

The assert(nb_rif_conf <= bank->ngpios) mandate to have less or the same
number of RIF configuration than the number of GPIO pin describe with
the property gpio-ranges to have the same number.

Remove the assert and replace() it with MIN() to be less restrictive.

Fixes: bd03c8c3d70f ("drivers: stm32_gpio: add stm32mp25x support")
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: enable watchdog SMC service

Enable Arm watchdog SMC service using function ID 0xbc000000.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Gof

plat-stm32mp2: enable watchdog SMC service

Enable Arm watchdog SMC service using function ID 0xbc000000.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: conf: default enable CFG_STM32_IWDG

Default enable STM32 IWDG driver on STM32MP2 platforms.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le G

plat-stm32mp2: conf: default enable CFG_STM32_IWDG

Default enable STM32 IWDG driver on STM32MP2 platforms.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: enable IWDG1 on stm32mp215f-dk board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevall

dts: stm32: enable IWDG1 on stm32mp215f-dk board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: enable IWDG1 on stm32mp257f-ev1 board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.cheval

dts: stm32: enable IWDG1 on stm32mp257f-ev1 board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add IWDG[1-2] nodes in stm32mp21x soc device-tree

Add support for IWDG[1-2] in stm32mp21x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gat

dts: stm32: add IWDG[1-2] nodes in stm32mp21x soc device-tree

Add support for IWDG[1-2] in stm32mp21x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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