1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2025 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/clock/stm32mp13-clksrc.h> 9#include <dt-bindings/firewall/stm32mp13-etzpc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 12#include <dt-bindings/reset/stm32mp13-resets.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a7"; 24 device_type = "cpu"; 25 reg = <0>; 26 clocks = <&rcc CK_MPU>; 27 clock-names = "cpu"; 28 operating-points-v2 = <&cpu0_opp_table>; 29 nvmem-cells = <&part_number_otp>; 30 nvmem-cell-names = "part_number"; 31 }; 32 }; 33 34 cpu0_opp_table: cpu0-opp-table { 35 compatible = "operating-points-v2"; 36 37 /* Non‑overdrive OPP mission profile */ 38 opp-650000000 { 39 opp-hz = /bits/ 64 <650000000>; 40 opp-microvolt = <1250000>; 41 opp-supported-hw = <0x3>; 42 st,opp-default; 43 }; 44 45 /* Overdrive OPP: 10‑year life activity @100% activity rate */ 46 opp-900000000 { 47 opp-hz = /bits/ 64 <900000000>; 48 opp-microvolt = <1350000>; 49 opp-supported-hw = <0x2>; 50 st,opp-default; 51 }; 52 53 /* Overdrive OPP: 10‑year life activity @25% activity rate */ 54 opp-1000000000 { 55 opp-hz = /bits/ 64 <1000000000>; 56 opp-microvolt = <1350000>; 57 opp-supported-hw = <0x2>; 58 }; 59 }; 60 61 hse_monitor: hse-monitor { 62 compatible = "st,freq-monitor"; 63 counter = <&lptimer3 1 1 0 0>; 64 status = "disabled"; 65 }; 66 67 intc: interrupt-controller@a0021000 { 68 compatible = "arm,cortex-a7-gic"; 69 #interrupt-cells = <3>; 70 interrupt-controller; 71 reg = <0xa0021000 0x1000>, 72 <0xa0022000 0x2000>; 73 }; 74 75 psci { 76 compatible = "arm,psci-1.0"; 77 method = "smc"; 78 }; 79 80 clocks { 81 clk_hse: clk-hse { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <24000000>; 85 }; 86 87 clk_hsi: clk-hsi { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <64000000>; 91 }; 92 93 clk_lse: clk-lse { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <32768>; 97 }; 98 99 clk_lsi: clk-lsi { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <32000>; 103 }; 104 105 clk_csi: clk-csi { 106 #clock-cells = <0>; 107 compatible = "fixed-clock"; 108 clock-frequency = <4000000>; 109 }; 110 111 clk_i2sin: clk-i2sin { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 clock-frequency = <19000000>; 115 }; 116 117 }; 118 119 sdmmc1_io: sdmmc1_io { 120 compatible = "st,stm32mp13-iod"; 121 regulator-name = "sdmmc1_io"; 122 regulator-always-on; 123 }; 124 125 sdmmc2_io: sdmmc2_io { 126 compatible = "st,stm32mp13-iod"; 127 regulator-name = "sdmmc2_io"; 128 regulator-always-on; 129 }; 130 131 soc { 132 compatible = "simple-bus"; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 interrupt-parent = <&intc>; 136 ranges; 137 138 usart3: serial@4000f000 { 139 compatible = "st,stm32h7-uart"; 140 reg = <0x4000f000 0x400>; 141 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&rcc USART3_K>; 143 resets = <&rcc USART3_R>; 144 status = "disabled"; 145 }; 146 147 uart4: serial@40010000 { 148 compatible = "st,stm32h7-uart"; 149 reg = <0x40010000 0x400>; 150 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&rcc UART4_K>; 152 resets = <&rcc UART4_R>; 153 status = "disabled"; 154 }; 155 156 uart5: serial@40011000 { 157 compatible = "st,stm32h7-uart"; 158 reg = <0x40011000 0x400>; 159 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&rcc UART5_K>; 161 resets = <&rcc UART5_R>; 162 status = "disabled"; 163 }; 164 165 uart7: serial@40018000 { 166 compatible = "st,stm32h7-uart"; 167 reg = <0x40018000 0x400>; 168 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&rcc UART7_K>; 170 resets = <&rcc UART7_R>; 171 status = "disabled"; 172 }; 173 174 uart8: serial@40019000 { 175 compatible = "st,stm32h7-uart"; 176 reg = <0x40019000 0x400>; 177 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&rcc UART8_K>; 179 resets = <&rcc UART8_R>; 180 status = "disabled"; 181 }; 182 183 usart6: serial@44003000 { 184 compatible = "st,stm32h7-uart"; 185 reg = <0x44003000 0x400>; 186 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&rcc USART6_K>; 188 resets = <&rcc USART6_R>; 189 status = "disabled"; 190 }; 191 192 rcc: rcc@50000000 { 193 compatible = "st,stm32mp13-rcc", "syscon"; 194 reg = <0x50000000 0x1000>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 #clock-cells = <1>; 198 #reset-cells = <1>; 199 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>; 200 clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin"; 201 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 202 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 203 secure-interrupt-names = "wakeup"; 204 }; 205 206 pwr_regulators: pwr@50001000 { 207 compatible = "st,stm32mp1,pwr-reg"; 208 reg = <0x50001000 0x10>; 209 210 reg11: reg11 { 211 regulator-name = "reg11"; 212 regulator-min-microvolt = <1100000>; 213 regulator-max-microvolt = <1100000>; 214 }; 215 216 reg18: reg18 { 217 regulator-name = "reg18"; 218 regulator-min-microvolt = <1800000>; 219 regulator-max-microvolt = <1800000>; 220 }; 221 222 usb33: usb33 { 223 regulator-name = "usb33"; 224 regulator-min-microvolt = <3300000>; 225 regulator-max-microvolt = <3300000>; 226 }; 227 }; 228 229 pwr_irq: pwr@50001010 { 230 compatible = "st,stm32mp1,pwr-irq"; 231 status = "disabled"; 232 }; 233 234 exti: interrupt-controller@5000d000 { 235 compatible = "st,stm32mp1-exti"; 236 interrupt-controller; 237 #interrupt-cells = <2>; 238 reg = <0x5000d000 0x400>; 239 interrupts-extended = 240 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 241 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 242 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 243 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 244 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 245 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 246 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 247 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 248 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 249 <&intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 250 <&intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 251 <&intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 252 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 253 <&intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 254 <&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 255 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 256 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 257 <0>, 258 <&intc GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 259 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 260 <0>, /* EXTI_20 */ 261 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 262 <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 263 <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 264 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 265 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 266 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 267 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 268 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 269 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 270 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 271 <&intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 272 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 273 <&intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 274 <0>, 275 <0>, 276 <0>, 277 <0>, 278 <0>, 279 <0>, 280 <0>, /* EXTI_40 */ 281 <0>, 282 <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 283 <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 284 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 285 <0>, 286 <0>, 287 <&intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 288 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 289 <0>, 290 <&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 291 <0>, 292 <&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 293 <&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 294 <0>, 295 <0>, 296 <0>, 297 <0>, 298 <0>, 299 <0>, 300 <0>, /* EXTI_60 */ 301 <0>, 302 <0>, 303 <0>, 304 <0>, 305 <0>, 306 <0>, 307 <0>, 308 <&intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 309 <0>, 310 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 311 }; 312 313 syscfg: syscon@50020000 { 314 compatible = "st,stm32mp157-syscfg", "syscon"; 315 reg = <0x50020000 0x400>; 316 }; 317 318 iwdg2: watchdog@5a002000 { 319 compatible = "st,stm32mp1-iwdg"; 320 reg = <0x5a002000 0x400>; 321 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 323 clock-names = "pclk", "lsi"; 324 status = "disabled"; 325 }; 326 327 rtc: rtc@5c004000 { 328 compatible = "st,stm32mp13-rtc"; 329 reg = <0x5c004000 0x400>; 330 clocks = <&rcc RTCAPB>, <&rcc RTC>; 331 clock-names = "pclk", "rtc_ck"; 332 status = "disabled"; 333 }; 334 335 bsec: efuse@5c005000 { 336 compatible = "st,stm32mp13-bsec"; 337 reg = <0x5c005000 0x400>; 338 #address-cells = <1>; 339 #size-cells = <1>; 340 341 cfg0_otp: cfg0_otp@0 { 342 reg = <0x0 0x2>; 343 }; 344 part_number_otp: part_number_otp@4 { 345 reg = <0x4 0x2>; 346 bits = <0 12>; 347 }; 348 monotonic_otp: monotonic_otp@10 { 349 reg = <0x10 0x4>; 350 }; 351 nand_otp: cfg9_otp@24 { 352 reg = <0x24 0x4>; 353 }; 354 uid_otp: uid_otp@34 { 355 reg = <0x34 0xc>; 356 }; 357 hw2_otp: hw2_otp@48 { 358 reg = <0x48 0x4>; 359 }; 360 ts_cal1: calib@5c { 361 reg = <0x5c 0x2>; 362 }; 363 ts_cal2: calib@5e { 364 reg = <0x5e 0x2>; 365 }; 366 pkh_otp: pkh_otp@60 { 367 reg = <0x60 0x20>; 368 }; 369 ethernet_mac1_address: mac1@e4 { 370 reg = <0xe4 0xc>; 371 st,non-secure-otp; 372 }; 373 oem_enc_key: oem_enc_key@170 { 374 reg = <0x170 0x10>; 375 }; 376 }; 377 378 tzc400: tzc@5c006000 { 379 compatible = "st,stm32mp1-tzc"; 380 reg = <0x5c006000 0x1000>; 381 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 382 st,mem-map = <0xc0000000 0x40000000>; 383 clocks = <&rcc TZC>; 384 }; 385 386 tamp: tamp@5c00a000 { 387 compatible = "st,stm32mp13-tamp"; 388 reg = <0x5c00a000 0x400>; 389 interrupts-extended = <&exti 18 IRQ_TYPE_EDGE_RISING>; 390 clocks = <&rcc RTCAPB>; 391 st,backup-zones = <10 5 17>; 392 }; 393 394 pinctrl: pin-controller@50002000 { 395 #address-cells = <1>; 396 #size-cells = <1>; 397 compatible = "st,stm32mp135-pinctrl"; 398 ranges = <0 0x50002000 0x8400>; 399 400 gpioa: gpio@50002000 { 401 gpio-controller; 402 #gpio-cells = <2>; 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 #access-controller-cells = <1>; 406 clocks = <&rcc GPIOA>; 407 reg = <0x0 0x400>; 408 st,bank-name = "GPIOA"; 409 ngpios = <16>; 410 gpio-ranges = <&pinctrl 0 0 16>; 411 }; 412 413 gpiob: gpio@50003000 { 414 gpio-controller; 415 #gpio-cells = <2>; 416 interrupt-controller; 417 #interrupt-cells = <2>; 418 #access-controller-cells = <1>; 419 clocks = <&rcc GPIOB>; 420 reg = <0x1000 0x400>; 421 st,bank-name = "GPIOB"; 422 ngpios = <16>; 423 gpio-ranges = <&pinctrl 0 16 16>; 424 }; 425 426 gpioc: gpio@50004000 { 427 gpio-controller; 428 #gpio-cells = <2>; 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 #access-controller-cells = <1>; 432 clocks = <&rcc GPIOC>; 433 reg = <0x2000 0x400>; 434 st,bank-name = "GPIOC"; 435 ngpios = <16>; 436 gpio-ranges = <&pinctrl 0 32 16>; 437 }; 438 439 gpiod: gpio@50005000 { 440 gpio-controller; 441 #gpio-cells = <2>; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 #access-controller-cells = <1>; 445 clocks = <&rcc GPIOD>; 446 reg = <0x3000 0x400>; 447 st,bank-name = "GPIOD"; 448 ngpios = <16>; 449 gpio-ranges = <&pinctrl 0 48 16>; 450 }; 451 452 gpioe: gpio@50006000 { 453 gpio-controller; 454 #gpio-cells = <2>; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 #access-controller-cells = <1>; 458 clocks = <&rcc GPIOE>; 459 reg = <0x4000 0x400>; 460 st,bank-name = "GPIOE"; 461 ngpios = <16>; 462 gpio-ranges = <&pinctrl 0 64 16>; 463 }; 464 465 gpiof: gpio@50007000 { 466 gpio-controller; 467 #gpio-cells = <2>; 468 interrupt-controller; 469 #interrupt-cells = <2>; 470 #access-controller-cells = <1>; 471 clocks = <&rcc GPIOF>; 472 reg = <0x5000 0x400>; 473 st,bank-name = "GPIOF"; 474 ngpios = <16>; 475 gpio-ranges = <&pinctrl 0 80 16>; 476 }; 477 478 gpiog: gpio@50008000 { 479 gpio-controller; 480 #gpio-cells = <2>; 481 interrupt-controller; 482 #interrupt-cells = <2>; 483 #access-controller-cells = <1>; 484 clocks = <&rcc GPIOG>; 485 reg = <0x6000 0x400>; 486 st,bank-name = "GPIOG"; 487 ngpios = <16>; 488 gpio-ranges = <&pinctrl 0 96 16>; 489 }; 490 491 gpioh: gpio@50009000 { 492 gpio-controller; 493 #gpio-cells = <2>; 494 interrupt-controller; 495 #interrupt-cells = <2>; 496 #access-controller-cells = <1>; 497 clocks = <&rcc GPIOH>; 498 reg = <0x7000 0x400>; 499 st,bank-name = "GPIOH"; 500 ngpios = <15>; 501 gpio-ranges = <&pinctrl 0 112 15>; 502 }; 503 504 gpioi: gpio@5000a000 { 505 gpio-controller; 506 #gpio-cells = <2>; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 #access-controller-cells = <1>; 510 clocks = <&rcc GPIOI>; 511 reg = <0x8000 0x400>; 512 st,bank-name = "GPIOI"; 513 ngpios = <8>; 514 gpio-ranges = <&pinctrl 0 128 8>; 515 }; 516 }; 517 518 etzpc: etzpc@5c007000 { 519 compatible = "st,stm32-etzpc", "simple-bus"; 520 reg = <0x5C007000 0x400>; 521 clocks = <&rcc TZPC>; 522 #address-cells = <1>; 523 #size-cells = <1>; 524 #access-controller-cells = <1>; 525 526 adc_2: adc@48004000 { 527 reg = <0x48004000 0x400>; 528 compatible = "st,stm32mp13-adc-core"; 529 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 531 clock-names = "bus", "adc"; 532 interrupt-controller; 533 #interrupt-cells = <1>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 access-controllers = <&etzpc STM32MP1_ETZPC_ADC2_ID>; 537 status = "disabled"; 538 539 adc2: adc@0 { 540 compatible = "st,stm32mp13-adc"; 541 reg = <0x0>; 542 #io-channel-cells = <1>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 interrupt-parent = <&adc_2>; 546 interrupts = <0>; 547 status = "disabled"; 548 549 channel@13 { 550 reg = <13>; 551 label = "vrefint"; 552 }; 553 554 channel@14 { 555 reg = <14>; 556 label = "vddcore"; 557 }; 558 559 channel@16 { 560 reg = <16>; 561 label = "vddcpu"; 562 }; 563 564 channel@17 { 565 reg = <17>; 566 label = "vddq_ddr"; 567 }; 568 }; 569 }; 570 571 usart1: serial@4c000000 { 572 compatible = "st,stm32h7-uart"; 573 reg = <0x4c000000 0x400>; 574 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&rcc USART1_K>; 576 resets = <&rcc USART1_R>; 577 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 578 status = "disabled"; 579 }; 580 581 usart2: serial@4c001000 { 582 compatible = "st,stm32h7-uart"; 583 reg = <0x4c001000 0x400>; 584 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&rcc USART2_K>; 586 resets = <&rcc USART2_R>; 587 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 588 status = "disabled"; 589 }; 590 591 i2c3: i2c@4c004000 { 592 compatible = "st,stm32mp13-i2c"; 593 reg = <0x4c004000 0x400>; 594 clocks = <&rcc I2C3_K>; 595 resets = <&rcc I2C3_R>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 st,syscfg-fmp = <&syscfg 0x4 0x4>; 599 i2c-analog-filter; 600 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 601 status = "disabled"; 602 }; 603 604 i2c4: i2c@4c005000 { 605 compatible = "st,stm32mp13-i2c"; 606 reg = <0x4c005000 0x400>; 607 clocks = <&rcc I2C4_K>; 608 resets = <&rcc I2C4_R>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 st,syscfg-fmp = <&syscfg 0x4 0x8>; 612 i2c-analog-filter; 613 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 614 status = "disabled"; 615 }; 616 617 i2c5: i2c@4c006000 { 618 compatible = "st,stm32mp13-i2c"; 619 reg = <0x4c006000 0x400>; 620 clocks = <&rcc I2C5_K>; 621 resets = <&rcc I2C5_R>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 st,syscfg-fmp = <&syscfg 0x4 0x10>; 625 i2c-analog-filter; 626 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 627 status = "disabled"; 628 }; 629 630 timers12: timer@4c007000 { 631 #address-cells = <1>; 632 #size-cells = <0>; 633 compatible = "st,stm32-timers"; 634 reg = <0x4c007000 0x400>; 635 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&rcc TIM12_K>; 637 clock-names = "int"; 638 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 639 status = "disabled"; 640 641 counter { 642 compatible = "st,stm32-timer-counter"; 643 status = "disabled"; 644 }; 645 }; 646 647 timers13: timer@4c008000 { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 compatible = "st,stm32-timers"; 651 reg = <0x4c008000 0x400>; 652 clocks = <&rcc TIM13_K>; 653 clock-names = "int"; 654 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 655 status = "disabled"; 656 }; 657 658 timers14: timer@4c009000 { 659 #address-cells = <1>; 660 #size-cells = <0>; 661 compatible = "st,stm32-timers"; 662 reg = <0x4c009000 0x400>; 663 clocks = <&rcc TIM14_K>; 664 clock-names = "int"; 665 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 666 status = "disabled"; 667 }; 668 669 timers15: timer@4c00a000 { 670 #address-cells = <1>; 671 #size-cells = <0>; 672 compatible = "st,stm32-timers"; 673 reg = <0x4c00a000 0x400>; 674 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&rcc TIM15_K>; 676 clock-names = "int"; 677 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 678 status = "disabled"; 679 680 counter { 681 compatible = "st,stm32-timer-counter"; 682 status = "disabled"; 683 }; 684 }; 685 686 timers16: timer@4c00b000 { 687 #address-cells = <1>; 688 #size-cells = <0>; 689 compatible = "st,stm32-timers"; 690 reg = <0x4c00b000 0x400>; 691 clocks = <&rcc TIM16_K>; 692 clock-names = "int"; 693 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 694 status = "disabled"; 695 }; 696 697 timers17: timer@4c00c000 { 698 #address-cells = <1>; 699 #size-cells = <0>; 700 compatible = "st,stm32-timers"; 701 reg = <0x4c00c000 0x400>; 702 clocks = <&rcc TIM17_K>; 703 clock-names = "int"; 704 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 705 status = "disabled"; 706 }; 707 708 lptimer2: timer@50021000 { 709 #address-cells = <1>; 710 #size-cells = <0>; 711 compatible = "st,stm32-lptimer"; 712 reg = <0x50021000 0x400>; 713 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&rcc LPTIM2_K>; 715 clock-names = "mux"; 716 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 717 status = "disabled"; 718 }; 719 720 lptimer3: timer@50022000 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 compatible = "st,stm32-lptimer"; 724 reg = <0x50022000 0x400>; 725 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&rcc LPTIM3_K>; 727 clock-names = "mux"; 728 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 729 status = "disabled"; 730 731 counter { 732 compatible = "st,stm32-lptimer-counter"; 733 status = "disabled"; 734 }; 735 }; 736 737 vrefbuf: vrefbuf@50025000 { 738 compatible = "st,stm32mp13-vrefbuf"; 739 reg = <0x50025000 0x8>; 740 regulator-name = "vrefbuf"; 741 regulator-min-microvolt = <1650000>; 742 regulator-max-microvolt = <2500000>; 743 clocks = <&rcc VREF>; 744 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 745 status = "disabled"; 746 }; 747 748 hash: hash@54003000 { 749 compatible = "st,stm32mp13-hash"; 750 reg = <0x54003000 0x400>; 751 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&rcc HASH1>; 753 resets = <&rcc HASH1_R>; 754 access-controllers = <&etzpc STM32MP1_ETZPC_HASH_ID>; 755 status = "disabled"; 756 }; 757 758 rng: rng@54004000 { 759 compatible = "st,stm32mp13-rng"; 760 reg = <0x54004000 0x400>; 761 clocks = <&rcc RNG1_K>; 762 resets = <&rcc RNG1_R>; 763 access-controllers = <&etzpc STM32MP1_ETZPC_RNG_ID>; 764 status = "disabled"; 765 }; 766 767 iwdg1: watchdog@5c003000 { 768 compatible = "st,stm32mp1-iwdg"; 769 reg = <0x5C003000 0x400>; 770 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 772 clock-names = "pclk", "lsi"; 773 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 774 status = "disabled"; 775 }; 776 777 stgen: stgen@5c008000 { 778 compatible = "st,stm32-stgen"; 779 reg = <0x5C008000 0x1000>; 780 access-controllers = <&etzpc STM32MP1_ETZPC_STGENC_ID>; 781 }; 782 }; 783 }; 784}; 785