| 2fd102eb | 06-Jun-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: stm32_gpio: panic on clock enable error
Changes stm32_gpio.c to panic on bank clock gating error.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carrier
drivers: stm32_gpio: panic on clock enable error
Changes stm32_gpio.c to panic on bank clock gating error.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 1001585e | 26-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: stm32_gpio: remove GPIO access specific API functions
Removes stm32_gpio API functions to access GPIOs as the driver has moved to the generic GPIO framework and consumer driver should use t
drivers: stm32_gpio: remove GPIO access specific API functions
Removes stm32_gpio API functions to access GPIOs as the driver has moved to the generic GPIO framework and consumer driver should use the generic API to access GPIOs. The driver now expects CFG_DRIVERS_GPIO is enabled.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| ca1a94a1 | 30-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: enable CFG_DRIVERS_GPIO
Enables CFG_DRIVERS_GPIO for platform stm32mp1.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@
plat-stm32mp1: enable CFG_DRIVERS_GPIO
Enables CFG_DRIVERS_GPIO for platform stm32mp1.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 420a32c5 | 26-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: stm32_gpio: support CFG_DRIVERS_GPIO
Changes stm32_gpio driver to register GPIO provider resources for each GPIO bank registered when CFG_DRIVERS_GPIO is enabled.
Acked-by: Gatien Chevalli
drivers: stm32_gpio: support CFG_DRIVERS_GPIO
Changes stm32_gpio driver to register GPIO provider resources for each GPIO bank registered when CFG_DRIVERS_GPIO is enabled.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| a009881d | 05-Feb-2023 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: interrupt: add inline descriptions
Adds inline description comments in interrupt.h and fix an indentation.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carri
core: interrupt: add inline descriptions
Adds inline description comments in interrupt.h and fix an indentation.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 3475549b | 05-Feb-2023 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: interrupt: rename internal itr_chip to itr_main_chip
Renames local variable itr_chip into itr_main_chip to emphasize it is the CPU main interrupt controller.
Reviewed-by: Jens Wiklander <jens
core: interrupt: rename internal itr_chip to itr_main_chip
Renames local variable itr_chip into itr_main_chip to emphasize it is the CPU main interrupt controller.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| e050e0a7 | 31-May-2023 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: interrupt: interrupt_get_main_chip() returns main controller
Adds helper function interrupt_get_main_chip() to get the struct itr_chip reference of the CPU main interrupt controller (e.g. the
core: interrupt: interrupt_get_main_chip() returns main controller
Adds helper function interrupt_get_main_chip() to get the struct itr_chip reference of the CPU main interrupt controller (e.g. the GIC). This function helps adapting a generic interrupt controller framework to consider CPU main interrupt controller specific reference.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 145953d5 | 25-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: remove unused gpio bank base address helper function
Removes stm32mp1 platform helper function stm32_get_gpio_bank_base().
Acked-by: Lionel Debieve <lionel.debieve@foss.st.com> Acked
plat-stm32mp1: remove unused gpio bank base address helper function
Removes stm32mp1 platform helper function stm32_get_gpio_bank_base().
Acked-by: Lionel Debieve <lionel.debieve@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 7c67e9ca | 25-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: remove unused gpio bank clock helper functions
Removes stm32mp1 platform helper functions stm32_get_gpio_bank_clock() and stm32_get_gpio_bank_clk().
Acked-by: Lionel Debieve <lionel.
plat-stm32mp1: remove unused gpio bank clock helper functions
Removes stm32mp1 platform helper functions stm32_get_gpio_bank_clock() and stm32_get_gpio_bank_clk().
Acked-by: Lionel Debieve <lionel.debieve@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 98dfceda | 31-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: stm32_gpio: don't mask interrupt during clock gating
Swaps interrupt masking and clock gating instructions to move GPIO bank gating sequence outside of the time window when interrupt are ma
drivers: stm32_gpio: don't mask interrupt during clock gating
Swaps interrupt masking and clock gating instructions to move GPIO bank gating sequence outside of the time window when interrupt are masked when the GPIO spinlock is locked.
Acked-by: Lionel Debieve <lionel.debieve@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| bed4582f | 30-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: stm32_gpio: use SHIFT_U32() where applicable
Replaces 32bit operand raw left shift with use of SHIFT_U32() macro.
Acked-by: Lionel Debieve <lionel.debieve@foss.st.com> Acked-by: Gatien Che
drivers: stm32_gpio: use SHIFT_U32() where applicable
Replaces 32bit operand raw left shift with use of SHIFT_U32() macro.
Acked-by: Lionel Debieve <lionel.debieve@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 077d486e | 25-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: stm32_gpio: add helper function stm32_gpio_get_bank()
Adds helper function stm32_gpio_get_bank() in stm32_gpio to retrieve a GPIO bank instance from the bank ID. This change will allow a la
drivers: stm32_gpio: add helper function stm32_gpio_get_bank()
Adds helper function stm32_gpio_get_bank() in stm32_gpio to retrieve a GPIO bank instance from the bank ID. This change will allow a later change to remove now useless platform helper functions stm32_get_gpio_bank_base() and stm32_get_gpio_bank_clk().
This changes removes the verification of GPIO banks clock reference against platform data (in ckeck_gpio_bank()) which is not really useful as we can consider embedded DTB data are reliable.
Checks clk_enable() return value to panic on failure.
Acked-by: Lionel Debieve <lionel.debieve@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| f12b4ead | 02-Jun-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: pinctrl: pinctrl name may not be found
Changes pinctrl_get_state_by_name() to return TEE_ERROR_ITEM_NOT_FOUND instead of TEE_ERROR_GENERIC when an pinctrl state index is not found in the DT
drivers: pinctrl: pinctrl name may not be found
Changes pinctrl_get_state_by_name() to return TEE_ERROR_ITEM_NOT_FOUND instead of TEE_ERROR_GENERIC when an pinctrl state index is not found in the DT.
Fixes: 9aec039ec0d7 ("drivers: pinctrl: add pinctrl support") Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 52c31eb0 | 04-May-2023 |
Clement Faure <clement.faure@nxp.com> |
drivers: ele: use the new derive key API for HUK generation
Use the derive key ELE API to generate the OPTEE HUK based on an input pattern. This change might break backward compatibility with pre-pr
drivers: ele: use the new derive key API for HUK generation
Use the derive key ELE API to generate the OPTEE HUK based on an input pattern. This change might break backward compatibility with pre-production firmware revisions.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 92c2884f | 04-May-2023 |
Clement Faure <clement.faure@nxp.com> |
drivers: ele: change RNG command ID
Change ELE API command ID for the RNG to 0xCD. This change might break backward compatibility with pre-production firmware revisions.
Signed-off-by: Clement Faur
drivers: ele: change RNG command ID
Change ELE API command ID for the RNG to 0xCD. This change might break backward compatibility with pre-production firmware revisions.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 322cf9e3 | 23-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: stm32_gpio: consider DT output data configuration
Get output data pin configuration from DT node property "output-high" and "output-low".
Acked-by: Jerome Forissier <jerome.forissier@linar
drivers: stm32_gpio: consider DT output data configuration
Get output data pin configuration from DT node property "output-high" and "output-low".
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| ba69abea | 16-Feb-2023 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
arm: Add Aspeed AST2700 platform support
Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 CPU. This patch adds the platform support for AST2700 to execute 64-bits OP-TEE on top of ARMv8 TrustZo
arm: Add Aspeed AST2700 platform support
Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 CPU. This patch adds the platform support for AST2700 to execute 64-bits OP-TEE on top of ARMv8 TrustZone features.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 2e5a3b0d | 26-May-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Implement function to print kernel stack
Implement the function to print the kernel stack. The code is referenced from ARM architecture.
Signed-off-by: Alvin Chang <alvinga@andestech.c
core: riscv: Implement function to print kernel stack
Implement the function to print the kernel stack. The code is referenced from ARM architecture.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 4450510c | 26-May-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Add read_fp() and read_pc()
Implement inline functions to read PC and FP. This is required to trace back the kernel stack.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by:
core: riscv: Add read_fp() and read_pc()
Implement inline functions to read PC and FP. This is required to trace back the kernel stack.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| b498b831 | 26-May-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Update the kernel mode unwinding
The data structure for RISC-V does not have sp, remove it in the function. Also the function and structure are renamed.
Signed-off-by: Alvin Chang <alv
core: riscv: Update the kernel mode unwinding
The data structure for RISC-V does not have sp, remove it in the function. Also the function and structure are renamed.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 27be144d | 26-May-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Add core compiler flags for stack unwinding
When the CFG_UNWIND is enabled, the frame pointer should not be omitted by compiler. Add "-fno-omit-frame-pointer" compiler flag when we enab
core: riscv: Add core compiler flags for stack unwinding
When the CFG_UNWIND is enabled, the frame pointer should not be omitted by compiler. Add "-fno-omit-frame-pointer" compiler flag when we enable the CFG_UNWIND to let compiler not to omit the frame pointer.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 37a778a5 | 26-May-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Save and restore register s0 when trap occurs
In RISC-V the frame pointer is stored into register s0. It is necessary to save/restore s0 when we enable CFG_UNWIND to process stack unwin
core: riscv: Save and restore register s0 when trap occurs
In RISC-V the frame pointer is stored into register s0. It is necessary to save/restore s0 when we enable CFG_UNWIND to process stack unwinding.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| aeee5d74 | 30-May-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Correct sp before boot_init_primary_late()
Fix the stack pointer according to mentioned commits. The sp should be assigned as thread#0's stack pointer, and the flag that indicates usage
core: riscv: Correct sp before boot_init_primary_late()
Fix the stack pointer according to mentioned commits. The sp should be assigned as thread#0's stack pointer, and the flag that indicates usage of the temporary stack must be cleared before boot_init_primary_late() is called. After boot_init_primary_late() is returned, we restore the previous sp and set the flag again.
Fixes: 59ac3801b756 ("core: split boot_init_primary()") Fixes: 1d88c0c03f3b ("core: clear temporary stack flag before entering boot_init_primary_late()")' Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 28a029b5 | 23-May-2023 |
Margarita Glushkin <rutigl@gmail.com> |
core: add plat-nuvoton
Adds support to Nuvoton npcm845x
Co-developed-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com> Signed-off-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com> Signed-off-
core: add plat-nuvoton
Adds support to Nuvoton npcm845x
Co-developed-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com> Signed-off-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com> Signed-off-by: Margarita Glushkin <rutigl@gmail.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| f7a5c21e | 29-May-2023 |
Jerome Forissier <jerome.forissier@linaro.org> |
arm64: memtag: strip tag from crash dumps
The MTE tag is not really useful when displaying a crash dump. In fact it makes it more complicated for tools like script/symbolize.py to retrieve the actua
arm64: memtag: strip tag from crash dumps
The MTE tag is not really useful when displaying a crash dump. In fact it makes it more complicated for tools like script/symbolize.py to retrieve the actual (untagged) virtual address, especially as we now support non-Arm architectures and therefore blindly stripping the MTE bits is not possible.
This commit strips the tag in call stacks displayed by print_stack_arm64(). It also removes it from the virtual address shown on abort (__print_abort_info()) since symbolize.py does try to resolve the address as symbol + offset ; but in this case the tagged address is printed as well, because it can be helpful to diagnose tag check faults.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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