1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8 9flavor_dts_file-135F_DK = stm32mp135f-dk.dts 10 11flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 12 $(flavor_dts_file-135F_DK) 13 14flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 15 16flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 17 $(flavor_dts_file-157C_ED1) \ 18 $(flavor_dts_file-157C_EV1) 19 20flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 21 22flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 23 $(flavorlist-no_cryp-1G) 24 25flavorlist-512M = $(flavorlist-cryp-512M) \ 26 $(flavorlist-no_cryp-512M) 27 28flavorlist-1G = $(flavorlist-cryp-1G) \ 29 $(flavorlist-no_cryp-1G) 30 31flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 32 $(flavor_dts_file-157C_DK2) \ 33 $(flavor_dts_file-157C_ED1) \ 34 $(flavor_dts_file-157C_EV1) 35 36flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 37 $(flavor_dts_file-157A_DK1) \ 38 $(flavor_dts_file-157C_DHCOM_PDK2) \ 39 $(flavor_dts_file-157C_DK2) \ 40 $(flavor_dts_file-157C_ED1) \ 41 $(flavor_dts_file-157C_EV1) 42 43flavorlist-MP13 = $(flavor_dts_file-135F_DK) 44 45ifneq ($(PLATFORM_FLAVOR),) 46ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 47$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 48endif 49CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 50endif 51CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 52 53ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 54$(call force,CFG_STM32_CRYP,n) 55endif 56 57ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 58$(call force,CFG_HWRNG_PTA,n) 59$(call force,CFG_WITH_SOFTWARE_PRNG,y) 60endif 61 62ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 63CFG_STM32MP15_HUK ?= y 64CFG_STM32_HUK_FROM_DT ?= y 65endif 66 67ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 68$(call force,CFG_STM32MP13,y) 69endif 70 71ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 72$(call force,CFG_STM32MP15,y) 73endif 74 75# CFG_STM32MP1x switches are exclusive. 76# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 77# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 78ifeq ($(CFG_STM32MP13),y) 79$(call force,CFG_STM32MP15,n) 80else 81$(call force,CFG_STM32MP15,y) 82$(call force,CFG_STM32MP13,n) 83endif 84ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 85$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 86endif 87ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 88$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 89endif 90 91include core/arch/arm/cpu/cortex-a7.mk 92 93$(call force,CFG_DRIVERS_CLK,y) 94$(call force,CFG_DRIVERS_CLK_DT,y) 95$(call force,CFG_DRIVERS_GPIO,y) 96$(call force,CFG_GIC,y) 97$(call force,CFG_INIT_CNTVOFF,y) 98$(call force,CFG_PSCI_ARM32,y) 99$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 100$(call force,CFG_SM_PLATFORM_HANDLER,y) 101$(call force,CFG_STM32_SHARED_IO,y) 102 103ifeq ($(CFG_STM32MP13),y) 104$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 105$(call force,CFG_CORE_RESERVED_SHM,n) 106$(call force,CFG_DRIVERS_CLK_FIXED,y) 107$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 108$(call force,CFG_STM32_GPIO,y) 109$(call force,CFG_STM32MP_CLK_CORE,y) 110$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 111$(call force,CFG_STM32MP13_CLK,y) 112$(call force,CFG_TEE_CORE_NB_CORE,1) 113$(call force,CFG_WITH_NSEC_GPIOS,n) 114CFG_EXTERNAL_DT ?= n 115CFG_STM32MP_OPP_COUNT ?= 2 116CFG_WITH_PAGER ?= n 117endif # CFG_STM32MP13 118 119ifeq ($(CFG_STM32MP15),y) 120$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 121$(call force,CFG_DRIVERS_CLK_FIXED,n) 122$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 123$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 124$(call force,CFG_STM32MP15_CLK,y) 125CFG_CORE_RESERVED_SHM ?= y 126CFG_EXTERNAL_DT ?= y 127CFG_STM32_BSEC_SIP ?= y 128CFG_TEE_CORE_NB_CORE ?= 2 129CFG_WITH_PAGER ?= y 130CFG_WITH_SOFTWARE_PRNG ?= y 131endif # CFG_STM32MP15 132 133ifeq ($(CFG_WITH_PAGER),y) 134CFG_WITH_LPAE ?= n 135endif 136CFG_WITH_LPAE ?= y 137CFG_MMAP_REGIONS ?= 23 138CFG_DTB_MAX_SIZE ?= (256 * 1024) 139CFG_CORE_ASLR ?= n 140 141ifneq ($(CFG_WITH_LPAE),y) 142# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 143CFG_TEE_RAM_VA_SIZE ?= 0x00200000 144endif 145 146ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 147CFG_TZDRAM_START ?= 0xde000000 148CFG_DRAM_SIZE ?= 0x20000000 149endif 150 151CFG_DRAM_BASE ?= 0xc0000000 152CFG_DRAM_SIZE ?= 0x40000000 153 154# CFG_STM32MP1_SCMI_SHM_BASE and CFG_STM32MP1_SCMI_SHM_SIZE define the 155# device memory mapped SRAM used for SCMI message transfers. 156# When CFG_STM32MP1_SCMI_SHM_BASE is set to 0, the platform uses OP-TEE 157# native shared memory for SCMI communication instead of SRAM. 158CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000 159CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000 160 161ifeq ($(CFG_STM32MP15),y) 162CFG_TZDRAM_START ?= 0xfe000000 163ifeq ($(CFG_CORE_RESERVED_SHM),y) 164CFG_TZDRAM_SIZE ?= 0x01e00000 165else 166CFG_TZDRAM_SIZE ?= 0x02000000 167endif 168CFG_TZSRAM_START ?= 0x2ffc0000 169CFG_TZSRAM_SIZE ?= 0x0003f000 170ifeq ($(CFG_CORE_RESERVED_SHM),y) 171CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 172CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 173endif 174else 175CFG_TZDRAM_SIZE ?= 0x02000000 176CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 177endif #CFG_STM32MP15 178 179CFG_STM32_BSEC ?= y 180CFG_STM32_CRYP ?= y 181CFG_STM32_ETZPC ?= y 182CFG_STM32_GPIO ?= y 183CFG_STM32_I2C ?= y 184CFG_STM32_IWDG ?= y 185CFG_STM32_RNG ?= y 186CFG_STM32_RSTCTRL ?= y 187CFG_STM32_TAMP ?= y 188CFG_STM32_UART ?= y 189CFG_STPMIC1 ?= y 190CFG_TZC400 ?= y 191 192CFG_WITH_SOFTWARE_PRNG ?= n 193ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 194$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 195endif 196 197ifeq ($(CFG_STPMIC1),y) 198$(call force,CFG_STM32_I2C,y) 199$(call force,CFG_STM32_GPIO,y) 200endif 201 202# if any crypto driver is enabled, enable the crypto-framework layer 203ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y) 204$(call force,CFG_STM32_CRYPTO_DRIVER,y) 205endif 206 207CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 208$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 209 210CFG_WDT ?= $(CFG_STM32_IWDG) 211 212# Platform specific configuration 213CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 214 215# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 216ifneq ($(CFG_SCMI_SCPFW),y) 217CFG_SCMI_MSG_DRIVERS ?= y 218endif 219 220# SiP/OEM service for non-secure world 221CFG_STM32_BSEC_SIP ?= n 222CFG_STM32MP1_SCMI_SIP ?= n 223ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 224$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 225$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 226$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 227endif 228 229# Enable BSEC PTA for fuses access management 230CFG_STM32_BSEC_PTA ?= y 231ifeq ($(CFG_STM32_BSEC_PTA),y) 232$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 233endif 234 235# Default enable SCMI PTA support 236CFG_SCMI_PTA ?= y 237ifeq ($(CFG_SCMI_PTA),y) 238ifneq ($(CFG_SCMI_SCPFW),y) 239$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 240CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 241CFG_SCMI_MSG_SHM_MSG ?= y 242CFG_SCMI_MSG_SMT ?= y 243endif # !CFG_SCMI_SCPFW 244endif # CFG_SCMI_PTA 245 246CFG_SCMI_SCPFW ?= n 247ifeq ($(CFG_SCMI_SCPFW),y) 248$(call force,CFG_SCMI_SCPFW_PRODUCT,optee-stm32mp1) 249endif 250 251CFG_SCMI_MSG_DRIVERS ?= n 252ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 253$(call force,CFG_SCMI_MSG_CLOCK,y) 254$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 255CFG_SCMI_MSG_SHM_MSG ?= y 256CFG_SCMI_MSG_SMT ?= y 257CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 258$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 259endif 260 261ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 262CFG_HWRNG_PTA ?= y 263endif 264ifeq ($(CFG_HWRNG_PTA),y) 265$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 266$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 267$(call force,CFG_HWRNG_QUALITY,1024) 268endif 269 270# Provision enough threads to pass xtest 271ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 272ifeq ($(CFG_WITH_PAGER),y) 273CFG_NUM_THREADS ?= 3 274else 275CFG_NUM_THREADS ?= 10 276endif 277endif 278 279# Default enable some test facitilites 280CFG_ENABLE_EMBEDDED_TESTS ?= y 281CFG_WITH_STATS ?= y 282 283# Enable OTP update with BSEC driver 284CFG_STM32_BSEC_WRITE ?= y 285 286# Default disable some support for pager memory size constraint 287ifeq ($(CFG_WITH_PAGER),y) 288CFG_TEE_CORE_DEBUG ?= n 289CFG_UNWIND ?= n 290CFG_LOCKDEP ?= n 291CFG_TA_BGET_TEST ?= n 292# Default disable early TA compression to support a smaller HEAP size 293CFG_EARLY_TA_COMPRESS ?= n 294CFG_CORE_HEAP_SIZE ?= 49152 295endif 296 297# Non-secure UART and GPIO/pinctrl for the output console 298CFG_WITH_NSEC_GPIOS ?= y 299CFG_WITH_NSEC_UARTS ?= y 300# UART instance used for early console (0 disables early console) 301CFG_STM32_EARLY_CONSOLE_UART ?= 4 302 303# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 304# Disable the HUK by default as it requires a product specific configuration. 305# 306# Configuration must provide OTP indices where HUK is loaded. 307# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 308# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 309# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 310# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 311# 312# Configuration must provide the HUK generation scheme. The following switches 313# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 314# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 315# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 316# content derived with the device UID fuses content. See derivation scheme 317# in stm32mp15_huk.c implementation. 318CFG_STM32MP15_HUK ?= n 319CFG_STM32_HUK_FROM_DT ?= n 320 321ifeq ($(CFG_STM32MP15_HUK),y) 322ifneq ($(CFG_STM32_HUK_FROM_DT),y) 323ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 324$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 325$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 326$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 327$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 328endif 329ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 330$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 331endif 332ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 333$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 334endif 335ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 336$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 337endif 338ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 339$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 340endif 341endif # CFG_STM32_HUK_FROM_DT 342 343CFG_STM32MP15_HUK_BSEC_KEY ?= y 344CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 345ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 346$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 347else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 348$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 349endif 350endif # CFG_STM32MP15_HUK 351 352CFG_TEE_CORE_DEBUG ?= y 353CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 354 355# Sanity on choice config switches 356ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 357$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 358endif 359