core: imx: move PSCI SNVS operation to the driver

Create imx_snvs_shutdown() to use during psci_system_off() call.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jen

core: imx: move PSCI SNVS operation to the driver

Create imx_snvs_shutdown() to use during psci_system_off() call.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: fix IOMUXC GPR5 register read

Define IOMUXC_SIZE value for imx7 platforms and re-work the way the GPR
register is read.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jen

core: imx: fix IOMUXC GPR5 register read

Define IOMUXC_SIZE value for imx7 platforms and re-work the way the GPR
register is read.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: re-work SRC driver

Encapsulate all SRC register operations in dedicated functions.
Move SRC register offsets and values to SRC source file.
Define SRC_SIZE for i.MX6 and i.MX7 platforms.

core: imx: re-work SRC driver

Encapsulate all SRC register operations in dedicated functions.
Move SRC register offsets and values to SRC source file.
Define SRC_SIZE for i.MX6 and i.MX7 platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: move SRC driver to pm directory

Move the SRC driver to pm sub-directory since it is related to the power
management PSCI features.
Rename it from imx_src.c to src.c.
Create a local header

core: imx: move SRC driver to pm directory

Move the SRC driver to pm sub-directory since it is related to the power
management PSCI features.
Rename it from imx_src.c to src.c.
Create a local header file.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: remove PSCI_CPU_SUSPEND capability

Remove the PSCI_CPU_SUSPEND capability as it is not supported.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wikl

core: imx: remove PSCI_CPU_SUSPEND capability

Remove the PSCI_CPU_SUSPEND capability as it is not supported.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: remove power management code for imx7d platforms

The code for suspend and cpuidle is not functioning properly,
outdated and unmaintained.
Remove these two features and associated code.

S

core: imx: remove power management code for imx7d platforms

The code for suspend and cpuidle is not functioning properly,
outdated and unmaintained.
Remove these two features and associated code.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: use monotonic counter for secure storage without RPMB

If OP-TEE is configured without RPMB (CFG_REE_FS_INTEGRITY_RPMB=n), use
the non-volatile monotonic counter interface instead to protect ag

core: use monotonic counter for secure storage without RPMB

If OP-TEE is configured without RPMB (CFG_REE_FS_INTEGRITY_RPMB=n), use
the non-volatile monotonic counter interface instead to protect against
rollback of the REE FS base secure storage.

If configured without CFG_WARN_INSECURE=y, accept
TEE_ERROR_NOT_IMPLEMENTED error from nv_counter_get_ree_fs() and
nv_counter_incr_ree_fs_to() and warn once to make clear that the
configuration isn't secure.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add non-volatile monotonic counter interface

Adds a stubbed non-volatile monotonic counter interface with a REE FS
counter. Platforms or drivers overrides the weak functions
nv_counter_get_ree

core: add non-volatile monotonic counter interface

Adds a stubbed non-volatile monotonic counter interface with a REE FS
counter. Platforms or drivers overrides the weak functions
nv_counter_get_ree_fs() and nv_counter_incr_ree_fs_to() to provide a
non-stubbed implementation of the counter.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: tee: add entry_fast.c

This commit adds an implementation of fast call handers. It copies
the original implementation replacing thread_smc_args structures
with thread_abi_args counterpar

core: riscv: tee: add entry_fast.c

This commit adds an implementation of fast call handers. It copies
the original implementation replacing thread_smc_args structures
with thread_abi_args counterparts. tee_entry_fastcall_l2cc_mutex()
has been modified to return OPTEE_ABI_RETURN_UNKNOWN_FUNCTION.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: add thread_optee_abi.c

This commit just copies thread_optee_smc.c from ARM and renames
smc/SMC to abi/ABI.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alv

core: riscv: add thread_optee_abi.c

This commit just copies thread_optee_smc.c from ARM and renames
smc/SMC to abi/ABI.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: include: add tee/teeabi_opteed_macros.h

This commit just copies teesmc_opteed_macros.h from ARM and renames
smc/SMC to abi/ABI.
All unused and ARM-related macros are removed.

Signed-of

core: riscv: include: add tee/teeabi_opteed_macros.h

This commit just copies teesmc_opteed_macros.h from ARM and renames
smc/SMC to abi/ABI.
All unused and ARM-related macros are removed.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: include: add tee/teeabi_opteed.h

This commit just copies teesmc_opteed.h from ARM and renames
smc/SMC to abi/ABI.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-

core: riscv: include: add tee/teeabi_opteed.h

This commit just copies teesmc_opteed.h from ARM and renames
smc/SMC to abi/ABI.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: include: add tee/optee_abi.h

This commit just copies optee_smc.h from ARM and renames
smc/SMC to abi/ABI.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvi

core: riscv: include: add tee/optee_abi.h

This commit just copies optee_smc.h from ARM and renames
smc/SMC to abi/ABI.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: include: add tee/entry_fast.h

This commit just copies entry_fast.h from ARM and renames
thread_smc_args to thread_abi_args.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>

core: riscv: include: add tee/entry_fast.h

This commit just copies entry_fast.h from ARM and renames
thread_smc_args to thread_abi_args.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: move TEE ABI handlers from thread_rv.S to thread_optee_abi_rv.S

This commits moves the following functions from thread_rv.S to a separate
file thread_optee_abi_rv.S:

- thread_return_fr

core: riscv: move TEE ABI handlers from thread_rv.S to thread_optee_abi_rv.S

This commits moves the following functions from thread_rv.S to a separate
file thread_optee_abi_rv.S:

- thread_return_from_nsec_call()
- thread_std_smc_entry() -> renamed to thread_std_abi_entry()
- thread_rpc()

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: thread_arch.c: Use of ABI structure instead of SMC structure

SMC is an ARM-related keyword, make use thread_std_abi_entry instead of
thread_std_smc_entry.

Signed-off-by: Marouene Bouba

core: riscv: thread_arch.c: Use of ABI structure instead of SMC structure

SMC is an ARM-related keyword, make use thread_std_abi_entry instead of
thread_std_smc_entry.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: thread_private_arch.h: add std and fast calls prototypes

This commit adds the following prototypes to thread_private_arch.h:
- thread_std_abi_entry()
- __thread_std_abi_entry()
- thread

core: riscv: thread_private_arch.h: add std and fast calls prototypes

This commit adds the following prototypes to thread_private_arch.h:
- thread_std_abi_entry()
- __thread_std_abi_entry()
- thread_handle_fast_abi()
- thread_handle_std_abi()

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: thread_arch.h: rename thread_smc_args to thread_abi_args

SMC is an ARM-related keyword referring to Secure Monitor Call.
This commit renames thread_smc_args to thread_abi_args in
thread

core: riscv: thread_arch.h: rename thread_smc_args to thread_abi_args

SMC is an ARM-related keyword referring to Secure Monitor Call.
This commit renames thread_smc_args to thread_abi_args in
thread_arch.h and keeps the same members to guarantee compatibility
with the existing secure and non-secure domain communication protocol.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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plat-k3: Default to 2 core per cluster only for AM65x

All other SoCs have 4 cores per cluster, which is the default, or
they only have one cluster in which case this value is unimportant.

Signed-of

plat-k3: Default to 2 core per cluster only for AM65x

All other SoCs have 4 cores per cluster, which is the default, or
they only have one cluster in which case this value is unimportant.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: sp: fix raw binary format SP loader

Loading a compressed raw binary format SP fails when read_compressed()
in embedded_ts.c is trying to allocate memory using bb_alloc(), since
the bounce buff

core: sp: fix raw binary format SP loader

Loading a compressed raw binary format SP fails when read_compressed()
in embedded_ts.c is trying to allocate memory using bb_alloc(), since
the bounce buffer in this user_mode_ctx is uninitialized. For ELF format
SPs ldelf is taking care of this, let's add the necessary initialization
to the raw binary format loader too.

Fixes: ef44161f847b ("core: update ts_store API with user space buffer")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: tpm: don't write to SPMC manifest

If "CFG_CORE_SEL1_SPMC=y" the TPM event log info is read from the SPMC
manifest instead of the external DT. The TPM event log handler code is
setting the even

core: tpm: don't write to SPMC manifest

If "CFG_CORE_SEL1_SPMC=y" the TPM event log info is read from the SPMC
manifest instead of the external DT. The TPM event log handler code is
setting the event log's address to zero in the DT, which fails since the
SPMC manifest is mapped as read-only. Remove this zeroing for the S-EL1
SPMC use case, it has no added security benefits since the SPMC manifest
DT itself is always in secure memory anyways.

Fixes: 722c618f0dfa ("core: map manifest using MEM_AREA_MANIFEST_DT")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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zynqmp: remove redundant platform config code

The hardware description is identical in all the platforms, there is no
need for specific ultra96 code to define base addresses.

Signed-off-by: Ibai Er

zynqmp: remove redundant platform config code

The hardware description is identical in all the platforms, there is no
need for specific ultra96 code to define base addresses.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: unconditionally support manifest DT with FF-A

When configured for FF-A (CFG_CORE_FFA=y) unconditionally support
receiving at manifest device tree. This also makes CFG_DT=y mandatory
with FF-A.

core: unconditionally support manifest DT with FF-A

When configured for FF-A (CFG_CORE_FFA=y) unconditionally support
receiving at manifest device tree. This also makes CFG_DT=y mandatory
with FF-A.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Leisen <leisen1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: always save manifest DT with CFG_CORE_SEL2_SPMC=y

With CFG_CORE_SEL2_SPMC=y the manifest device tree is passed via boot
info from the SPMC at S-EL2. This manifest can contain configuration
nee

core: always save manifest DT with CFG_CORE_SEL2_SPMC=y

With CFG_CORE_SEL2_SPMC=y the manifest device tree is passed via boot
info from the SPMC at S-EL2. This manifest can contain configuration
needed later during boot, so save it always regardless of
CFG_CORE_PHYS_RELOCATABLE.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Leisen <leisen1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: make core_mmu_set_secure_memory() available

Makes core_mmu_set_secure_memory() unconditionally available, but add a
runtime_assert() to protect against calls without
CFG_CORE_PHYS_RELOCATABLE=

core: make core_mmu_set_secure_memory() available

Makes core_mmu_set_secure_memory() unconditionally available, but add a
runtime_assert() to protect against calls without
CFG_CORE_PHYS_RELOCATABLE=y.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Leisen <leisen1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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