1PLATFORM_FLAVOR ?= ls1012ardb 2 3$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 4$(call force,CFG_GIC,y) 5$(call force,CFG_16550_UART,y) 6$(call force,CFG_LS,y) 7 8$(call force,CFG_DRAM0_BASE,0x80000000) 9$(call force,CFG_TEE_OS_DRAM0_SIZE,0x4000000) 10 11CFG_ENABLE_EMBEDDED_TESTS ?= y 12 13CFG_CORE_HEAP_SIZE ?= 131072 14 15ifeq ($(PLATFORM_FLAVOR),ls1012ardb) 16include core/arch/arm/cpu/cortex-armv8-0.mk 17$(call force,CFG_TEE_CORE_NB_CORE,1) 18$(call force,CFG_DRAM0_SIZE,0x40000000) 19$(call force,CFG_CORE_CLUSTER_SHIFT,2) 20CFG_NUM_THREADS ?= 2 21CFG_SHMEM_SIZE ?= 0x00200000 22endif 23 24ifeq ($(PLATFORM_FLAVOR),ls1043ardb) 25include core/arch/arm/cpu/cortex-armv8-0.mk 26$(call force,CFG_TEE_CORE_NB_CORE,4) 27$(call force,CFG_DRAM0_SIZE,0x80000000) 28$(call force,CFG_CORE_CLUSTER_SHIFT,2) 29CFG_SHMEM_SIZE ?= 0x00200000 30endif 31 32ifeq ($(PLATFORM_FLAVOR),ls1046ardb) 33include core/arch/arm/cpu/cortex-armv8-0.mk 34$(call force,CFG_TEE_CORE_NB_CORE,4) 35$(call force,CFG_DRAM0_SIZE,0x80000000) 36$(call force,CFG_CORE_CLUSTER_SHIFT,2) 37CFG_SHMEM_SIZE ?= 0x00200000 38endif 39 40ifeq ($(PLATFORM_FLAVOR),ls1088ardb) 41include core/arch/arm/cpu/cortex-armv8-0.mk 42$(call force,CFG_TEE_CORE_NB_CORE,8) 43$(call force,CFG_DRAM0_SIZE,0x80000000) 44$(call force,CFG_CORE_CLUSTER_SHIFT,2) 45$(call force,CFG_ARM_GICV3,y) 46CFG_SHMEM_SIZE ?= 0x00200000 47endif 48 49ifeq ($(PLATFORM_FLAVOR),ls2088ardb) 50include core/arch/arm/cpu/cortex-armv8-0.mk 51$(call force,CFG_TEE_CORE_NB_CORE,8) 52$(call force,CFG_DRAM0_SIZE,0x80000000) 53$(call force,CFG_CORE_CLUSTER_SHIFT,1) 54$(call force,CFG_ARM_GICV3,y) 55CFG_SHMEM_SIZE ?= 0x00200000 56endif 57 58ifeq ($(PLATFORM_FLAVOR),lx2160aqds) 59include core/arch/arm/cpu/cortex-armv8-0.mk 60$(call force,CFG_TEE_CORE_NB_CORE,16) 61$(call force,CFG_DRAM0_SIZE,0x80000000) 62$(call force,CFG_DRAM1_BASE,0x2080000000) 63$(call force,CFG_DRAM1_SIZE,0x1F80000000) 64$(call force,CFG_CORE_CLUSTER_SHIFT,1) 65$(call force,CFG_ARM_GICV3,y) 66$(call force,CFG_PL011,y) 67$(call force,CFG_CORE_ARM64_PA_BITS,48) 68$(call force,CFG_EMBED_DTB,y) 69$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-qds.dts) 70CFG_LS_I2C ?= y 71CFG_LS_GPIO ?= y 72CFG_LS_DSPI ?= y 73CFG_SHMEM_SIZE ?= 0x00200000 74endif 75 76ifeq ($(PLATFORM_FLAVOR),lx2160ardb) 77include core/arch/arm/cpu/cortex-armv8-0.mk 78$(call force,CFG_TEE_CORE_NB_CORE,16) 79$(call force,CFG_DRAM0_SIZE,0x80000000) 80$(call force,CFG_DRAM1_BASE,0x2080000000) 81$(call force,CFG_DRAM1_SIZE,0x1F80000000) 82$(call force,CFG_CORE_CLUSTER_SHIFT,1) 83$(call force,CFG_ARM_GICV3,y) 84$(call force,CFG_PL011,y) 85$(call force,CFG_CORE_ARM64_PA_BITS,48) 86$(call force,CFG_EMBED_DTB,y) 87$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-rdb.dts) 88CFG_LS_I2C ?= y 89CFG_LS_GPIO ?= y 90CFG_LS_DSPI ?= y 91CFG_SHMEM_SIZE ?= 0x00200000 92endif 93 94ifeq ($(PLATFORM_FLAVOR),ls1028ardb) 95include core/arch/arm/cpu/cortex-armv8-0.mk 96$(call force,CFG_TEE_CORE_NB_CORE,2) 97$(call force,CFG_DRAM0_SIZE,0x80000000) 98$(call force,CFG_CORE_CLUSTER_SHIFT,1) 99$(call force,CFG_ARM_GICV3,y) 100CFG_SHMEM_SIZE ?= 0x00200000 101endif 102 103ifeq ($(platform-flavor-armv8),1) 104$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 105CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 106CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - CFG_SHMEM_SIZE) 107#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 108CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_SHMEM_SIZE) 109$(call force,CFG_ARM64_core,y) 110CFG_USER_TA_TARGETS ?= ta_arm64 111else 112#In ARMv7 platform CFG_SHMEM_SIZE is different to that of ARMv8 platforms. 113CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 114CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - (2*CFG_SHMEM_SIZE)) 115#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 116CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - (2*CFG_SHMEM_SIZE)) 117endif 118 119#Keeping Number of TEE thread equal to number of cores on the SoC 120CFG_NUM_THREADS ?= $(CFG_TEE_CORE_NB_CORE) 121 122ifneq ($(CFG_ARM64_core),y) 123$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 124endif 125 126CFG_CRYPTO_SIZE_OPTIMIZATION ?= n 127 128# NXP CAAM support is not enabled by default and can be enabled 129# on the command line 130CFG_NXP_CAAM ?= n 131