| d98ee310 | 17-Oct-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: remove unnecessary header file
Remove #include <io.h>
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> |
| c354668a | 19-Oct-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: ffa: fix spmc_retrieve_req() buffer
Prior to this patch when retrieving a shared memory block the memory transaction descriptor (struct ffa_mem_transaction_1_1 or struct ffa_mem_transaction_1_
core: ffa: fix spmc_retrieve_req() buffer
Prior to this patch when retrieving a shared memory block the memory transaction descriptor (struct ffa_mem_transaction_1_1 or struct ffa_mem_transaction_1_0) was read from the TX buffer instead of the RX buffer where the actual memory transaction is supplied. Fix this by changing to read the memory transaction descriptor from the RX buffer.
This used to work somewhat by chance since OP-TEE before the call to FFA_MEM_RETRIEVE_REQ_32 filled in a memory transaction descriptor of what we expect to retrieve in the TX buffer.
Fixes: f49f23f781e3 ("core: ffa: rename nw_rxtx to my_rxtx") Fixes: a1c53023cc80 ("core: spmc: support FF-A 1.1") Suggested-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Balint Dobszay <balint.dobszay@arm.com>
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| 117fe695 | 11-Oct-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: scmi_server: enable boot on regulators
During SCMI server initialization, enable regulators that have a boot-on property enabled.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.
plat-stm32mp1: scmi_server: enable boot on regulators
During SCMI server initialization, enable regulators that have a boot-on property enabled.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 7ee4daa9 | 13-Sep-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: scmi_server: deny access to regulators not probed
SCMI server denies access to regulators that are not initialized hence cannot be exposed.
Acked-by: Gatien Chevallier <gatien.cheval
plat-stm32mp1: scmi_server: deny access to regulators not probed
SCMI server denies access to regulators that are not initialized hence cannot be exposed.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 8f99d932 | 06-Sep-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: scmi_server: regulator supported levels
Implements stm32mp1 platform SCMI voltage domain level list based on regulator_supported_voltages().
Acked-by: Gatien Chevallier <gatien.cheva
plat-stm32mp1: scmi_server: regulator supported levels
Implements stm32mp1 platform SCMI voltage domain level list based on regulator_supported_voltages().
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 23e20062 | 27-Jun-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: scmi_server: use registered regulators
Changes stm32mp1 platform SCMI server to use regulators registered in the regulator framework instead of local handlers. Getting the supported v
plat-stm32mp1: scmi_server: use registered regulators
Changes stm32mp1 platform SCMI server to use regulators registered in the regulator framework instead of local handlers. Getting the supported voltage list still uses a local function until the regulator framework provides a suitable API function for that purpose.
Stubbed regulators are still handled locally until their driver is implemented.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 8c49825d | 06-Sep-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: stm32mp1_pmic: regulators voltage list
Implements operator supported_voltages for stm32mp1 PMIC regulators driver. A voltage list array is allocated during initialization and freed up
plat-stm32mp1: stm32mp1_pmic: regulators voltage list
Implements operator supported_voltages for stm32mp1 PMIC regulators driver. A voltage list array is allocated during initialization and freed upon core initialization completion. This prevents wasting heap when the list is queried only during boot time.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| c610605d | 25-Jun-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: stm32mp1_pmic: register pmic regulators
Ports stm32mp1 PMIC driver to the regulator framework and register regulators from the secure DT content.
Acked-by: Gatien Chevallier <gatien.
plat-stm32mp1: stm32mp1_pmic: register pmic regulators
Ports stm32mp1 PMIC driver to the regulator framework and register regulators from the secure DT content.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 94dfdd29 | 23-Jun-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: stm32mp1_pwr: register regulators
Changes stm32mp1_pwr driver to be probed on from dt_driver framework and register PWR regulators to the regulator framework.
Acked-by: Gatien Cheval
plat-stm32mp1: stm32mp1_pwr: register regulators
Changes stm32mp1_pwr driver to be probed on from dt_driver framework and register PWR regulators to the regulator framework.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 312d4476 | 07-Sep-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: regulator: stm32_vrefbuf
Implements and enable STM32 VREFBUF regulator driver for stm32mp1 platform.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carr
drivers: regulator: stm32_vrefbuf
Implements and enable STM32 VREFBUF regulator driver for stm32mp1 platform.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 7db0e3c9 | 29-Sep-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: enable support for fixed regulators
Enables support for fixed regulators on platform stm32mp1.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carr
plat-stm32mp1: enable support for fixed regulators
Enables support for fixed regulators on platform stm32mp1.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| b69e72f2 | 17-Oct-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: regulator: change regu_dt_desc::name to const
Adds const attribute to regu_dt_desc::name.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.c
drivers: regulator: change regu_dt_desc::name to const
Adds const attribute to regu_dt_desc::name.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| b7de9d8c | 05-May-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: remove unused mobj_mm_alloc()
Removes the now unused mobj_mm_alloc(), struct mobj_mm, and friends.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienn
core: remove unused mobj_mm_alloc()
Removes the now unused mobj_mm_alloc(), struct mobj_mm, and friends.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| b6f1536c | 05-May-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: remove deprecated vm_add_rwmem() and vm_rem_rwmem()
Removes the two deprecated and now also unused functions vm_add_rwmem() and vm_rem_rwmem().
Signed-off-by: Jens Wiklander <jens.wiklander@l
core: remove deprecated vm_add_rwmem() and vm_rem_rwmem()
Removes the two deprecated and now also unused functions vm_add_rwmem() and vm_rem_rwmem().
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| ce014b00 | 05-May-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: remove unused mobj_seccpy_shm_alloc()
Removes the now unused mobj_seccpy_shm_alloc(), struct mobj_seccpy_shm, and friends.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by:
core: remove unused mobj_seccpy_shm_alloc()
Removes the now unused mobj_seccpy_shm_alloc(), struct mobj_seccpy_shm, and friends.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 1e9c1b80 | 05-May-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: remove temp memory allocation for TA invoke
Remove the temporary memory allocation used if a TA invokes another TA with a private memory buffer. This has not been in used with TAs compiled sin
core: remove temp memory allocation for TA invoke
Remove the temporary memory allocation used if a TA invokes another TA with a private memory buffer. This has not been in used with TAs compiled since commit ef305e54eac8 ("libutee: allocate temp secmem for invoke") or OP-TEE version 3.6.0.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| d5cb0882 | 13-Oct-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: crypto: stm32: lower verbosity on SAES use
Changes SAES context allocation/release trace message from debug level to flow level otherwise each access to the secure storage emits debug messa
drivers: crypto: stm32: lower verbosity on SAES use
Changes SAES context allocation/release trace message from debug level to flow level otherwise each access to the secure storage emits debug messages.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| dc9540cb | 11-Oct-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: regulator: consider DT property regulator-boot-on
Defines regulator flag REGULATOR_BOOT_ON for regulators with the regulator-boot-on property in their DT node.
Acked-by: Gatien Chevallier
drivers: regulator: consider DT property regulator-boot-on
Defines regulator flag REGULATOR_BOOT_ON for regulators with the regulator-boot-on property in their DT node.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 0a75d408 | 13-Oct-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: fix data abort during ftrace
With commit c10e3fa93d24 ("core: fix race in handling TA panic") the resources of a panicked TAs are released as early as possible, including the user space mapped
core: fix data abort during ftrace
With commit c10e3fa93d24 ("core: fix race in handling TA panic") the resources of a panicked TAs are released as early as possible, including the user space mapped ftrace buffer. However, the pointer to the ftrace buffer is stored in the ts_session for quick and easy access. The ftrace buffer is always retrieved with get_fbuf() that already have a few other checks to see if the buffer is currently available. So add a check to see that the TA hasn't panicked also.
Fixes: c10e3fa93d24 ("core: fix race in handling TA panic") Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)
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| ed89e939 | 11-Oct-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Fix logic of thread_{get/set}_exceptions()
In ARM, the bits in DAIF register are used to mask the interrupts. While in RISC-V, the bits in CSR XIE are used to enable(unmask) correspondi
core: riscv: Fix logic of thread_{get/set}_exceptions()
In ARM, the bits in DAIF register are used to mask the interrupts. While in RISC-V, the bits in CSR XIE are used to enable(unmask) corresponding interrupt sources.
To not modify the function of thread_get_exceptions(), we invert the bits after reading the value of CSR XIE, as mask.
To not modify the function of thread_set_exceptions(), we invert the bits in given "exceptions" before writing "exceptions" into CSR XIE. Therefore, the intended masked exception bits will be cleared when we write the final value into CSR XIE to mask those interrupts.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 470aadc6 | 11-Oct-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Register thread_vector_table in primary CPU initialization
When primary CPU has initialized everything, it registers the address of thread_vector_table into higher privileged software v
core: riscv: Register thread_vector_table in primary CPU initialization
When primary CPU has initialized everything, it registers the address of thread_vector_table into higher privileged software via a1 register.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 0cbfd093 | 11-Oct-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Implement thread_vector_table for ABI and FIQ entries
Implement thread_vector_table which only includes entries for standard ABI, fast ABI, and foreign interrupts. Most of code is refer
core: riscv: Implement thread_vector_table for ABI and FIQ entries
Implement thread_vector_table which only includes entries for standard ABI, fast ABI, and foreign interrupts. Most of code is referenced from ARM architecture. The thread_vector_table will be registered into higher privileged software, such as M-mode firmware. The higher privileged software can jump(mret) to OP-TEE based on this vector table.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 0fb22936 | 11-Oct-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Implement SBI based protocol
Rename thread_return_from_nsec_call() to thread_return_to_ree() for more general behavior, since TEE might not only be called by REE, but also do something
core: riscv: Implement SBI based protocol
Rename thread_return_from_nsec_call() to thread_return_to_ree() for more general behavior, since TEE might not only be called by REE, but also do something on its own initiative (e.g., handle secure interrupts).
This commit also implements SBI based protocol used to return control to REE. The register a7 encodes SBI TEE extension ID, which is temporarily defined here. We may have ratified SBI TEE extension in the future and we can apply ratified ID at that time. The register a6 is unused and encoded as 0. The returned arguments are encoded into registers a0~a5 and should be provided by the caller.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| d7b20c1e | 11-Oct-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Implement panic_at_abi_return as guard of ABI call
The ABI call to REE domain should not return. We implement panic_at_abi_return macro as guard of ABI call. When the ABI call return il
core: riscv: Implement panic_at_abi_return as guard of ABI call
The ABI call to REE domain should not return. We implement panic_at_abi_return macro as guard of ABI call. When the ABI call return illegally, the system will enter panic or an infinite loop.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| af06edb5 | 09-Oct-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: ffa: use FFA_NORMAL_WORLD_RESUME
Prior to this FFA_INTERRUPT was always completed using FFA_MSG_WAIT, but at S-EL1 FFA_NORMAL_WORLD_RESUME should be used instead. So fix this by completing a s
core: ffa: use FFA_NORMAL_WORLD_RESUME
Prior to this FFA_INTERRUPT was always completed using FFA_MSG_WAIT, but at S-EL1 FFA_NORMAL_WORLD_RESUME should be used instead. So fix this by completing a secure interrupt that has preempted the normal world with FFA_NORMAL_WORLD_RESUME if configured with SPMC at S-EL1.
Fixes: 67fec989b586 ("core: ffa: correct response to FFA_INTERRUPT") Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Balint Dobszay <balint.dobszay@arm.com>
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