1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8 9flavor_dts_file-135F_DK = stm32mp135f-dk.dts 10 11flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 12 $(flavor_dts_file-135F_DK) 13 14flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 15 16flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 17 $(flavor_dts_file-157C_ED1) \ 18 $(flavor_dts_file-157C_EV1) 19 20flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 21 22flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 23 $(flavorlist-no_cryp-1G) 24 25flavorlist-512M = $(flavorlist-cryp-512M) \ 26 $(flavorlist-no_cryp-512M) 27 28flavorlist-1G = $(flavorlist-cryp-1G) \ 29 $(flavorlist-no_cryp-1G) 30 31flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 32 $(flavor_dts_file-157C_DK2) \ 33 $(flavor_dts_file-157C_ED1) \ 34 $(flavor_dts_file-157C_EV1) 35 36flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 37 $(flavor_dts_file-157A_DK1) \ 38 $(flavor_dts_file-157C_DHCOM_PDK2) \ 39 $(flavor_dts_file-157C_DK2) \ 40 $(flavor_dts_file-157C_ED1) \ 41 $(flavor_dts_file-157C_EV1) 42 43flavorlist-MP13 = $(flavor_dts_file-135F_DK) 44 45ifneq ($(PLATFORM_FLAVOR),) 46ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 47$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 48endif 49CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 50endif 51CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 52 53ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 54$(call force,CFG_STM32_CRYP,n) 55$(call force,CFG_STM32_SAES,n) 56endif 57 58ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 59$(call force,CFG_HWRNG_PTA,n) 60$(call force,CFG_WITH_SOFTWARE_PRNG,y) 61endif 62 63ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 64CFG_STM32MP15_HUK ?= y 65CFG_STM32_HUK_FROM_DT ?= y 66endif 67 68ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 69$(call force,CFG_STM32MP13,y) 70endif 71 72ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 73$(call force,CFG_STM32MP15,y) 74endif 75 76# CFG_STM32MP1x switches are exclusive. 77# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 78# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 79ifeq ($(CFG_STM32MP13),y) 80$(call force,CFG_STM32MP15,n) 81else 82$(call force,CFG_STM32MP15,y) 83$(call force,CFG_STM32MP13,n) 84endif 85ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 86$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 87endif 88ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 89$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 90endif 91 92include core/arch/arm/cpu/cortex-a7.mk 93 94$(call force,CFG_DRIVERS_CLK,y) 95$(call force,CFG_DRIVERS_CLK_DT,y) 96$(call force,CFG_DRIVERS_GPIO,y) 97$(call force,CFG_DRIVERS_PINCTRL,y) 98$(call force,CFG_DRIVERS_REGULATOR,y) 99$(call force,CFG_GIC,y) 100$(call force,CFG_INIT_CNTVOFF,y) 101$(call force,CFG_PSCI_ARM32,y) 102$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 103$(call force,CFG_SM_PLATFORM_HANDLER,y) 104$(call force,CFG_STM32_SHARED_IO,y) 105$(call force,CFG_REGULATOR_FIXED,y) 106 107ifeq ($(CFG_STM32MP13),y) 108$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 109$(call force,CFG_CORE_RESERVED_SHM,n) 110$(call force,CFG_DRIVERS_CLK_FIXED,y) 111$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 112$(call force,CFG_STM32_GPIO,y) 113$(call force,CFG_STM32MP_CLK_CORE,y) 114$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 115$(call force,CFG_STM32MP13_CLK,y) 116$(call force,CFG_TEE_CORE_NB_CORE,1) 117$(call force,CFG_WITH_NSEC_GPIOS,n) 118CFG_EXTERNAL_DT ?= n 119CFG_STM32MP_OPP_COUNT ?= 2 120CFG_STM32MP1_SCMI_SHM_SYSRAM ?= y 121CFG_WITH_PAGER ?= n 122endif # CFG_STM32MP13 123 124ifeq ($(CFG_STM32MP15),y) 125$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 126$(call force,CFG_DRIVERS_CLK_FIXED,n) 127$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 128$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 129$(call force,CFG_STM32_SAES,n) 130$(call force,CFG_STM32MP15_CLK,y) 131CFG_CORE_RESERVED_SHM ?= y 132CFG_EXTERNAL_DT ?= y 133CFG_STM32_BSEC_SIP ?= y 134CFG_TEE_CORE_NB_CORE ?= 2 135CFG_WITH_PAGER ?= y 136CFG_WITH_SOFTWARE_PRNG ?= y 137endif # CFG_STM32MP15 138 139ifeq ($(CFG_WITH_PAGER),y) 140CFG_WITH_LPAE ?= n 141endif 142CFG_WITH_LPAE ?= y 143CFG_MMAP_REGIONS ?= 23 144CFG_DTB_MAX_SIZE ?= (256 * 1024) 145CFG_CORE_ASLR ?= n 146 147ifneq ($(CFG_WITH_LPAE),y) 148# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 149CFG_TEE_RAM_VA_SIZE ?= 0x00200000 150endif 151 152ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 153CFG_TZDRAM_START ?= 0xde000000 154CFG_DRAM_SIZE ?= 0x20000000 155endif 156 157CFG_DRAM_BASE ?= 0xc0000000 158CFG_DRAM_SIZE ?= 0x40000000 159 160# CFG_STM32MP1_SCMI_SHM_BASE and CFG_STM32MP1_SCMI_SHM_SIZE define the 161# device memory mapped SRAM used for SCMI message transfers. 162# When CFG_STM32MP1_SCMI_SHM_BASE is set to 0, the platform uses OP-TEE 163# native shared memory for SCMI communication instead of SRAM. 164# 165# When CFG_STM32MP1_SCMI_SHM_SYSRAM is enabled, OP-TEE uses the 166# last 4KB page of SYSRAM as SCMI shared memory. The switch is default 167# disabled. 168CFG_STM32MP1_SCMI_SHM_SYSRAM ?= n 169ifeq ($(CFG_STM32MP1_SCMI_SHM_SYSRAM),y) 170$(call force,CFG_STM32MP1_SCMI_SHM_BASE,0x2ffff000) 171else 172CFG_STM32MP1_SCMI_SHM_BASE ?= 0 173endif 174$(call force,CFG_STM32MP1_SCMI_SHM_SIZE,0x1000) 175 176ifeq ($(CFG_STM32MP15),y) 177CFG_TZDRAM_START ?= 0xfe000000 178ifeq ($(CFG_CORE_RESERVED_SHM),y) 179CFG_TZDRAM_SIZE ?= 0x01e00000 180else 181CFG_TZDRAM_SIZE ?= 0x02000000 182endif 183CFG_TZSRAM_START ?= 0x2ffc0000 184CFG_TZSRAM_SIZE ?= 0x0003f000 185ifeq ($(CFG_CORE_RESERVED_SHM),y) 186CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 187CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 188endif 189else 190CFG_TZDRAM_SIZE ?= 0x02000000 191CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 192endif #CFG_STM32MP15 193 194CFG_STM32_BSEC ?= y 195CFG_STM32_CRYP ?= y 196CFG_STM32_ETZPC ?= y 197CFG_STM32_GPIO ?= y 198CFG_STM32_I2C ?= y 199CFG_STM32_IWDG ?= y 200CFG_STM32_RNG ?= y 201CFG_STM32_RSTCTRL ?= y 202CFG_STM32_SAES ?= y 203CFG_STM32_TAMP ?= y 204CFG_STM32_UART ?= y 205CFG_STPMIC1 ?= y 206CFG_TZC400 ?= y 207 208CFG_DRIVERS_I2C ?= $(CFG_STM32_I2C) 209 210CFG_WITH_SOFTWARE_PRNG ?= n 211ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 212$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 213endif 214 215ifeq ($(CFG_STPMIC1),y) 216$(call force,CFG_STM32_I2C,y) 217$(call force,CFG_STM32_GPIO,y) 218endif 219 220# If any crypto driver is enabled, enable the crypto-framework layer 221ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP CFG_STM32_SAES),y) 222$(call force,CFG_STM32_CRYPTO_DRIVER,y) 223endif 224 225CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 226$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 227 228CFG_WDT ?= $(CFG_STM32_IWDG) 229 230# Platform specific configuration 231CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 232 233# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 234ifneq ($(CFG_SCMI_SCPFW),y) 235CFG_SCMI_MSG_DRIVERS ?= y 236endif 237 238# SiP/OEM service for non-secure world 239CFG_STM32_BSEC_SIP ?= n 240CFG_STM32MP1_SCMI_SIP ?= n 241ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 242$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 243$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 244$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 245endif 246 247# Enable BSEC PTA for fuses access management 248CFG_STM32_BSEC_PTA ?= y 249ifeq ($(CFG_STM32_BSEC_PTA),y) 250$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 251endif 252 253# Default enable SCMI PTA support 254CFG_SCMI_PTA ?= y 255ifeq ($(CFG_SCMI_PTA),y) 256ifneq ($(CFG_SCMI_SCPFW),y) 257$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 258CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 259CFG_SCMI_MSG_SHM_MSG ?= y 260CFG_SCMI_MSG_SMT ?= y 261endif # !CFG_SCMI_SCPFW 262endif # CFG_SCMI_PTA 263 264CFG_SCMI_SCPFW ?= n 265ifeq ($(CFG_SCMI_SCPFW),y) 266$(call force,CFG_SCMI_SCPFW_PRODUCT,optee-stm32mp1) 267endif 268 269CFG_SCMI_MSG_DRIVERS ?= n 270ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 271$(call force,CFG_SCMI_MSG_CLOCK,y) 272$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 273CFG_SCMI_MSG_SHM_MSG ?= y 274CFG_SCMI_MSG_SMT ?= y 275CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 276$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 277endif 278 279ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 280CFG_HWRNG_PTA ?= y 281endif 282ifeq ($(CFG_HWRNG_PTA),y) 283$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 284$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 285$(call force,CFG_HWRNG_QUALITY,1024) 286endif 287 288# Provision enough threads to pass xtest 289ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 290ifeq ($(CFG_WITH_PAGER),y) 291CFG_NUM_THREADS ?= 3 292else 293CFG_NUM_THREADS ?= 10 294endif 295endif 296 297# Default enable some test facitilites 298CFG_ENABLE_EMBEDDED_TESTS ?= y 299CFG_WITH_STATS ?= y 300 301# Enable OTP update with BSEC driver 302CFG_STM32_BSEC_WRITE ?= y 303 304# Default disable some support for pager memory size constraint 305ifeq ($(CFG_WITH_PAGER),y) 306CFG_TEE_CORE_DEBUG ?= n 307CFG_UNWIND ?= n 308CFG_LOCKDEP ?= n 309CFG_TA_BGET_TEST ?= n 310# Default disable early TA compression to support a smaller HEAP size 311CFG_EARLY_TA_COMPRESS ?= n 312CFG_CORE_HEAP_SIZE ?= 49152 313endif 314 315# Non-secure UART and GPIO/pinctrl for the output console 316CFG_WITH_NSEC_GPIOS ?= y 317CFG_WITH_NSEC_UARTS ?= y 318# UART instance used for early console (0 disables early console) 319CFG_STM32_EARLY_CONSOLE_UART ?= 4 320 321# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 322# Disable the HUK by default as it requires a product specific configuration. 323# 324# Configuration must provide OTP indices where HUK is loaded. 325# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 326# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 327# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 328# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 329# 330# Configuration must provide the HUK generation scheme. The following switches 331# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 332# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 333# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 334# content derived with the device UID fuses content. See derivation scheme 335# in stm32mp15_huk.c implementation. 336CFG_STM32MP15_HUK ?= n 337CFG_STM32_HUK_FROM_DT ?= n 338 339ifeq ($(CFG_STM32MP15_HUK),y) 340ifneq ($(CFG_STM32_HUK_FROM_DT),y) 341ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 342$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 343$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 344$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 345$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 346endif 347ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 348$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 349endif 350ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 351$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 352endif 353ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 354$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 355endif 356ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 357$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 358endif 359endif # CFG_STM32_HUK_FROM_DT 360 361CFG_STM32MP15_HUK_BSEC_KEY ?= y 362CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 363ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 364$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 365else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 366$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 367endif 368endif # CFG_STM32MP15_HUK 369 370CFG_TEE_CORE_DEBUG ?= y 371CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 372 373# Sanity on choice config switches 374ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 375$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 376endif 377