plat-stm32mp1: syscfg: HLSV mode for IO domains

Add platform API functions stm32mp_set_hslv_state() and
stm32mp_enable_fixed_vdd_hslv() to configure High Speed Low Voltage
mode of IO domains.

Platf

plat-stm32mp1: syscfg: HLSV mode for IO domains

Add platform API functions stm32mp_set_hslv_state() and
stm32mp_enable_fixed_vdd_hslv() to configure High Speed Low Voltage
mode of IO domains.

Platform function stm32mp_enable_fixed_vdd_hslv() is designed for
fixed voltage IO domains that need to be enable at boot time only
since the supply voltage level never changes.

On STM32MP13 variants, SDMMC IO domains may not be supplied by fixed
voltage VDD but rather by a supply which voltage level can change
at runtime for example to support SD/MMC normative 1.8V and 3.3V voltage
modes. Therefore these IO domains require a runtime configuration
function implemented by stm32mp_set_hslv_state().

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: syscfg: STM32MP13 dynamic IO compensation

Replace IO compensation API functions
stm32mp_syscfg_enable_io_compensation() and
stm32mp_syscfg_disable_io_compensation() with a new API fun

plat-stm32mp1: syscfg: STM32MP13 dynamic IO compensation

Replace IO compensation API functions
stm32mp_syscfg_enable_io_compensation() and
stm32mp_syscfg_disable_io_compensation() with a new API function
stm32mp_set_io_comp_by_index() dedicated to runtime configuration
of STM32MP13 SDMMC's domains IO compensation only.

On STM32MP15 variant, the configuration is enabled only during
initialization. On STM32MP13 variant, the same feature is also enabled
during initialization but the device embeds 2 more IO domains
(SDMMC1 and SDMMC2) for which the new API function allow runtime
reconfiguration support.

For sake of simplicity, keep related clocks always on.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: syscfg: compute base address once

Compute SYSCFG virtual address only once.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@f

plat-stm32mp1: syscfg: compute base address once

Compute SYSCFG virtual address only once.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: syscfg: use U() macro

Use U() macro where applicable in stm32mp1_syscfg.c driver.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.cheval

plat-stm32mp1: syscfg: use U() macro

Use U() macro where applicable in stm32mp1_syscfg.c driver.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mmu: fix nsec ddr discovery regarding MEM_AREA_RAM_NSEC

Memory registered as MEM_AREA_RAM_NSEC can be part of the non-secure
shared memory. This change fixes core_mmu_set_discovered_nsec_ddr()

core: mmu: fix nsec ddr discovery regarding MEM_AREA_RAM_NSEC

Memory registered as MEM_AREA_RAM_NSEC can be part of the non-secure
shared memory. This change fixes core_mmu_set_discovered_nsec_ddr()
to not check such memory area do not overlap with non-secure RAM.
This is no issue physical pages from MEM_AREA_RAM_NSEC memory are also
handled and mapped as dynamic non-secure memory by OP-TEE.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: use MEM_AREA_END to detect mapping area end

Change verify_special_mem_areas() prototype to remove the 'len'
argument that is useless since end of the static mapping areas array
is already

core: mm: use MEM_AREA_END to detect mapping area end

Change verify_special_mem_areas() prototype to remove the 'len'
argument that is useless since end of the static mapping areas array
is already defined by a MEM_AREA_END cell.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: MEM_AREA_ROM_SEC maps secure read only cached memory

Define memory area mapping identifier MEM_AREA_ROM_SEC to map read-only
secure cached memory.

Reviewed-by: Jens Wiklander <jens.wiklander@

core: MEM_AREA_ROM_SEC maps secure read only cached memory

Define memory area mapping identifier MEM_AREA_ROM_SEC to map read-only
secure cached memory.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: gic: use DT bindings

Use DT bindings GIC_PPI and GIC_SIP instead of 1 and 0 raw values.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@li

drivers: gic: use DT bindings

Use DT bindings GIC_PPI and GIC_SIP instead of 1 and 0 raw values.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: gic: register to dt_driver

Registers GIC driver as an interrupt controller in DT_DRIVER
providers when DT is supported. This change allows interrupt
consumer nodes to leverage interrupts an

drivers: gic: register to dt_driver

Registers GIC driver as an interrupt controller in DT_DRIVER
providers when DT is supported. This change allows interrupt
consumer nodes to leverage interrupts and interrupts-extended
properties DT bindings for their device drivers to retrieve
their interrupts.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: interrupt: add interrupt_create_handler()

Adds interrupt_create_handler() API function in interrupt framework.
The function is to be used with interrupt controls obtained
from the DT with int

core: interrupt: add interrupt_create_handler()

Adds interrupt_create_handler() API function in interrupt framework.
The function is to be used with interrupt controls obtained
from the DT with interrupt_dt_get() interrupt_dt_get_by_index() or
interrupt_dt_get_by_name().

The function differs from legacy interrupt_add_handler() in that
this latter always reconfigure the interrupt while new
interrupt_create_handler() function assumes the interrupt was configured
from interrupt_dt_get() or friends.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: interrupt: registering interrupt providers

Adds interrupt chip framework API functions for an interrupt controller
to register as an interrupt provider in the driver probing sequence
based on

core: interrupt: registering interrupt providers

Adds interrupt chip framework API functions for an interrupt controller
to register as an interrupt provider in the driver probing sequence
based on device tree. This allows interrupt consumer to be deferred
when a dependent interrupt controller is not yet initialized.

Interrupt controllers register a driver in DT_DRIVER providers list
with: interrupt_register_provider().

Interrupt consumer can get their interrupt through DT data with
interrupt_dt_get(), interrupt_dt_get_by_index() or
interrupt_dt_get_by_name().

This change removes inclusion of interrupt.h from kernel/dt.h as it is
not needed and conflicts with inclusion of kernel/dt.h from
kernel/interrupt.h.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: dt_driver: reference output device reference as void *

Changes dt_driver API function to reference device reference as
void * instead of void ** which could be confusing as the reference
can b

core: dt_driver: reference output device reference as void *

Changes dt_driver API function to reference device reference as
void * instead of void ** which could be confusing as the reference
can be a pointer to a device pointer (e.g. in clk_dt.c) or a pointer
to a structure (e.g. interrupt.c).

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: dt_driver: don't enforce phandle 1st arg is a phandle

Changes local function device_from_provider_prop() to assume its
argument @prop points to the first argument to pass with phandle.

This c

core: dt_driver: don't enforce phandle 1st arg is a phandle

Changes local function device_from_provider_prop() to assume its
argument @prop points to the first argument to pass with phandle.

This change allows a later change to support other DT bindings
("interrupts" property) where 1st cell of the property is not
a phandle but the 1st phandle argument to be passed.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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scmi-msg: fix voltage domains inline comment header file

Fix voltage domains inline comment header file.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carrie

scmi-msg: fix voltage domains inline comment header file

Fix voltage domains inline comment header file.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: print clock tree summary

Adds clk_print_summary() to print the clock tree current state on core
console using the info trace level. Clock framework spinlock is help
while clock tree is

drivers: clk: print clock tree summary

Adds clk_print_summary() to print the clock tree current state on core
console using the info trace level. Clock framework spinlock is help
while clock tree is printed.

The feature depends on CFG_DRIVERS_CLK_PRINT_TREE being enabled.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Co-developed-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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tree-wide: remove useless newline character in *MSG() messages

The *MSG() macros take care of printing a newline. Adding a newline
character ('\n') is useless. Remove it.

Signed-off-by: Vincent Mai

tree-wide: remove useless newline character in *MSG() messages

The *MSG() macros take care of printing a newline. Adding a newline
character ('\n') is useless. Remove it.

Signed-off-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: tee_svc.c: allow to pass non-NULL memref of size 0

Allow TAs to pass non-NULL memref of size zero to other TAs by
changing the non-NULL pointer into a NULL one in such a case. GP TEE
Internal

core: tee_svc.c: allow to pass non-NULL memref of size 0

Allow TAs to pass non-NULL memref of size zero to other TAs by
changing the non-NULL pointer into a NULL one in such a case. GP TEE
Internal Core API does not forbid such memref parameter [1] whereas
the previous implementation generated a TEE_ERROR_BAD_PARAMETERS error
code when converting such memref buffer pointer into a physical memory
address.

This change is specifically needed to allow a TA to forward a REE
client memref for which GP TEE Client API explicitly allows such
non-NULL address zero sized memref [2]. It also makes the TA
implementation more flexible when dealing with its own memref.

[1] TEE Internal Core API Specification – Public Release v1.3.1,
§4.9.4 "Operation Parameters in the Internal Client API"
Table 4-15: "Interpretation of params[i] on Entry to Internal Client
API"

[2] TEE Client API Specification v1.0, §4.5.4 TEEC_RegisterSharedMemory,
paragraph "Implementers' Notes"

Signed-off-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: fixup of transfer list entry overriding

Expand the data size of DTB transfer list entry to the max allocable
size to reserve sufficient space for new nodes.
This fixes a potential issue t

core: arm: fixup of transfer list entry overriding

Expand the data size of DTB transfer list entry to the max allocable
size to reserve sufficient space for new nodes.
This fixes a potential issue that the amended DTB transfer entry
overrides other entries followed by, when inserting new nodes.

When CFG_TRANSFER_LIST is enabled, instead of CFG_DTB_MAX_SIZE,
the DTB max size will be given by a calculation of the remaining space
in the transfer list mapped memory.

Fixes: 66763721fe35 ("core: add support for transfer list")
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add new argument to init_external_dt()

Add argument to function init_external_dt() to allow callers to specify
the maximum size of external DTB to be initialized.

Signed-off-by: Raymond Mao <

core: add new argument to init_external_dt()

Add argument to function init_external_dt() to allow callers to specify
the maximum size of external DTB to be initialized.

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: relax CFG_ASAN_SHADOW_OFFSET configuration value

Fixes CFG_ASAN_SHADOW_OFFSET configuration value for vexpress
platform qemu* flavors. Before this change CFG_ASAN_SHADOW_OFFSET
variab

plat-vexpress: relax CFG_ASAN_SHADOW_OFFSET configuration value

Fixes CFG_ASAN_SHADOW_OFFSET configuration value for vexpress
platform qemu* flavors. Before this change CFG_ASAN_SHADOW_OFFSET
variable needed a specific scope to override the default value set
by platform conf.mk file.

Fixes: 24475b562b81 ("plat-vexpress: move CFG_TEE_CORE_NB_CORE to platform conf.mk")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: relax CFG_TEE_CORE_NB_CORE configuration value

Fixes CFG_TEE_CORE_NB_CORE configuration value for all vexpress
platform flavors. Before this change CFG_TEE_CORE_NB_CORE variable
neede

plat-vexpress: relax CFG_TEE_CORE_NB_CORE configuration value

Fixes CFG_TEE_CORE_NB_CORE configuration value for all vexpress
platform flavors. Before this change CFG_TEE_CORE_NB_CORE variable
needed a specific scope to override the default value set by platform
conf.mk file.

Fixes: 24475b562b81 ("plat-vexpress: move CFG_TEE_CORE_NB_CORE to platform conf.mk")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: conf: fix order for CFG_REGULATOR_FIXED

Changes CFG_REGULATOR_FIXED config setting location to match alphabetical
order.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
S

plat-stm32mp1: conf: fix order for CFG_REGULATOR_FIXED

Changes CFG_REGULATOR_FIXED config setting location to match alphabetical
order.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: conf: enable support for GPIO regulators

Enables support for GPIO regulators on platform stm32mp1 when
CFG_STM32_GPIO is enabled.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.

plat-stm32mp1: conf: enable support for GPIO regulators

Enables support for GPIO regulators on platform stm32mp1 when
CFG_STM32_GPIO is enabled.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: GPIO controlled regulator

Implements a GPIO controlled regulators driver compliant with DT nodes
compatible with regulator-gpio. These regulators use GPIO pins to select
the volt

drivers: regulator: GPIO controlled regulator

Implements a GPIO controlled regulators driver compliant with DT nodes
compatible with regulator-gpio. These regulators use GPIO pins to select
the voltage level. The implementation supports only dual voltage level
selection using a single pin. The DT bindings allows more pins to
select between more voltages but no known platform currently requires
that so we preferred the simplified case.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: tee_ta_manager.c: add uuid in open session error trace

Adds the TA UUID in open session error trace to allow to identify
witch TA cause the issue when debug trace are not acitvated.

B

core: kernel: tee_ta_manager.c: add uuid in open session error trace

Adds the TA UUID in open session error trace to allow to identify
witch TA cause the issue when debug trace are not acitvated.

By the way, fix specifier for res argument that is a uint32_t.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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