dts: stm32mp15: disable non-secure IWDG2 on ST boards

Disable non-secure IWDG2 watchdog device in ST boards stm32mp157a-dk1,
stm32mp157c-dk2, stm32mp157c-ed1 and stm32mp157c-ev1. This watchdog is
fu

dts: stm32mp15: disable non-secure IWDG2 on ST boards

Disable non-secure IWDG2 watchdog device in ST boards stm32mp157a-dk1,
stm32mp157c-dk2, stm32mp157c-ed1 and stm32mp157c-ev1. This watchdog is
fully under control of the non-secure world and OP-TEE is not expected
to interfere with it.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dts: stm32mp15: enable secure IWDG1 on ST boards

Enable IWDG1 watchdog device in ST boards stm32mp157a-dk1,
stm32mp157c-dk2, stm32mp157c-ed1 and stm32mp157c-ev1.

Reviewed-by: Gatien Chevallier <gat

dts: stm32mp15: enable secure IWDG1 on ST boards

Enable IWDG1 watchdog device in ST boards stm32mp157a-dk1,
stm32mp157c-dk2, stm32mp157c-ed1 and stm32mp157c-ev1.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: arm: rpc_alloc: remove size limit for kernel payload

Removes the size limit of 1 page imposed in
thread_rpc_alloc_kernel_payload(). The purpose of this limit was to
error out early since the k

core: arm: rpc_alloc: remove size limit for kernel payload

Removes the size limit of 1 page imposed in
thread_rpc_alloc_kernel_payload(). The purpose of this limit was to
error out early since the kernel doesn't supply a list of physical pages
and the source of the error is not obvious at first glance. This is
now about to change so remove the limit since the kernel now may
supply the needed list of physical pages.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: rpmb: cleanup useless write_counter in struct rpmb_fat_entry

The write_counter field of the rpmb_fat_entry struct is set from the
RPMB device but never used. Rename it to 'unused' and cleanup

core: rpmb: cleanup useless write_counter in struct rpmb_fat_entry

The write_counter field of the rpmb_fat_entry struct is set from the
RPMB device but never used. Rename it to 'unused' and cleanup the
associated code.

Tested on QEMUv8 with:

$ make CFG_RPMB_FS=y CFG_RPMB_WRITE_KEY=y CFG_RPMB_TESKEY=y check

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com> (stm32mp157c-ev1 w/ RPMB)

show more ...

drivers: caam: update return type of caam_sm_free()

Update return type of caam_sm_free() from TEE_Result
to enum caam_status.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jer

drivers: caam: update return type of caam_sm_free()

Update return type of caam_sm_free() from TEE_Result
to enum caam_status.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

show more ...

riscv: virt: Enable CFG_DT

Enable CFG_DT to parse the external DTB passed by previous boot stage.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@lin

riscv: virt: Enable CFG_DT

Enable CFG_DT to parse the external DTB passed by previous boot stage.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

riscv: virt: Relax the configurations related to hart/thread number

Do not force the CFG_TEE_CORE_NB_CORE and CFG_NUM_THREADS to be 1, since
we may run SMP system which has multiple harts and thread

riscv: virt: Relax the configurations related to hart/thread number

Do not force the CFG_TEE_CORE_NB_CORE and CFG_NUM_THREADS to be 1, since
we may run SMP system which has multiple harts and threads.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

riscv: virt: Enable configurations for S-mode execution

In RISC-V QEMU virtual platform, we run OP-TEE as S-mode. This commit
forcely enables CFG_RISCV_S_MODE and disables CFG_RISCV_M_MODE. Also, we

riscv: virt: Enable configurations for S-mode execution

In RISC-V QEMU virtual platform, we run OP-TEE as S-mode. This commit
forcely enables CFG_RISCV_S_MODE and disables CFG_RISCV_M_MODE. Also, we
enable CFG_RISCV_SBI so that OP-TEE utilizes SBI to communicate with
other OS.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

plat-mediatek: disable console when CFG_TEE_CORE_LOG_LEVEL is 0

Following our usage, it can be interesting to disable the console,
typically for a final product.

Acked-by: Jens Wiklander <jens.wikl

plat-mediatek: disable console when CFG_TEE_CORE_LOG_LEVEL is 0

Following our usage, it can be interesting to disable the console,
typically for a final product.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Co-developed-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Julien Masson <jmasson@baylibre.com>

show more ...

plat-stm32mp1: scmi_server: remove useless bounding of voltage levels

Remove bounding of regulators supported voltage levels according
to mix/max levels now that drivers take care of that.

Acked-by

plat-stm32mp1: scmi_server: remove useless bounding of voltage levels

Remove bounding of regulators supported voltage levels according
to mix/max levels now that drivers take care of that.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: regulator: supported voltage consider levels bounds

Assert regulator_supported_voltages() provides a list that takes into
account the min/max voltage levels possibly set from the secure DT.

drivers: regulator: supported voltage consider levels bounds

Assert regulator_supported_voltages() provides a list that takes into
account the min/max voltage levels possibly set from the secure DT.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-stm32mp1: set voltage list at pmic driver init

Bound stm32mp1_pmic supported voltage levels list to min/max voltage
level values set from the DT. This change free quite a bit of byte in
the hea

plat-stm32mp1: set voltage list at pmic driver init

Bound stm32mp1_pmic supported voltage levels list to min/max voltage
level values set from the DT. This change free quite a bit of byte in
the heap for this platform.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: regulator: stm32_vrefbuf: set voltage list at init

Change stm32_vrefbuf driver to set the supported voltage levels list
at driver initialization rather than at first list query.

Acked-by:

drivers: regulator: stm32_vrefbuf: set voltage list at init

Change stm32_vrefbuf driver to set the supported voltage levels list
at driver initialization rather than at first list query.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: update transfer list header and signature

Add tl->flags and TL_FLAGS_HAS_CHECKSUM to align to the latest FW
Handoff spec update.
Bypass checksum verifying and updating if TL_FLAGS_HAS_CHECKSUM

core: update transfer list header and signature

Add tl->flags and TL_FLAGS_HAS_CHECKSUM to align to the latest FW
Handoff spec update.
Bypass checksum verifying and updating if TL_FLAGS_HAS_CHECKSUM bit
is not set in tl->flags.
Update TL signature to 4a0f_b10b to align to the latest FW Handoff
spec update.

Note: It causes Transfer List ABI breakage due to FW Handoff spec
stays with same rev number (v0.9) with above changes.

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: remove unused bytes from transfer list

Only marks the minimum bytes required by alignment as 'TL_TAG_EMPTY'
and release the rest of unused bytes from transfer list when downsizing
the data of

core: remove unused bytes from transfer list

Only marks the minimum bytes required by alignment as 'TL_TAG_EMPTY'
and release the rest of unused bytes from transfer list when downsizing
the data of a transfer entry.
Function transfer_list_set_data_size() will remove the unused bytes
from the transfer list so that the freed space is allocable when adding
new transfer entries.

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

pta: stats: add commands to print clock and regulator trees

Add statistics PTA commands STATS_CMD_PRINT_DRIVERS_INFO to print
device drivers information on console. The implementation currently
allo

pta: stats: add commands to print clock and regulator trees

Add statistics PTA commands STATS_CMD_PRINT_DRIVERS_INFO to print
device drivers information on console. The implementation currently
allows to print the clock tree and the regulator tree to core console.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: gic: allow GIC version 1

Before this patch with CFG_ARM_GICV3=n the GIC driver asserted that the
detected GIC version is 2. This is stricter than necessary and breaks
some older platforms so a

core: gic: allow GIC version 1

Before this patch with CFG_ARM_GICV3=n the GIC driver asserted that the
detected GIC version is 2. This is stricter than necessary and breaks
some older platforms so allow version 1 also.

Fixes: 69171bec89ce ("core: gic: check gic version")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Tested-by: Andrew Davis <afd@ti.com>

show more ...

core: gic: make GICR base optional

The physical address of the redistributor was, before this patch, always
used, regardless of whether affinity routing is enabled or otherwise not
needed.

Using th

core: gic: make GICR base optional

The physical address of the redistributor was, before this patch, always
used, regardless of whether affinity routing is enabled or otherwise not
needed.

Using the redistributor is optional if gic_init_donate_sgi_to_ns() isn't
called. So allow the GICR base address to be passed as zero if
gic_init_donate_sgi_to_ns() isn't called. However,
gic_init_donate_sgi_to_ns() will panic if called without a previously
configured GICR base address.

Fixes: 05089e5f9a56 ("core: gic: use redistributor CPU interface")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: ffa: fix FFA_NOTIFICATION_GET vm_id

handle_notification_get() has until now read the receiver endpoint ID
from the upper 16 bits of w1, but the receiver endpoint ID is passed in
the lower 16 b

core: ffa: fix FFA_NOTIFICATION_GET vm_id

handle_notification_get() has until now read the receiver endpoint ID
from the upper 16 bits of w1, but the receiver endpoint ID is passed in
the lower 16 bits of w1 passed to FFA_NOTIFICATION_GET. So fix the
function to read the lower 16 bits instead.

Fixes: 2e02a7374b86 ("core: ffa: add notifications with SPMC at S-EL1")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: regulator: fix variable sized voltages fallback

Fix build issue reported by Clang on variable size field desc
not being located at the end of struct voltages_fallback. The
error was reporte

drivers: regulator: fix variable sized voltages fallback

Fix build issue reported by Clang on variable size field desc
not being located at the end of struct voltages_fallback. The
error was reported with a trace message like below:

core/include/drivers/regulator.h:118:4: warning: field 'voltages_fallback' with variable sized type 'struct voltages_fallback' not at the end of a struct or class is a GNU extension [-Wgnu-variable-sized-type-not-at-end]
} voltages_fallback;
^
core/drivers/regulator/regulator_fixed.c:27:19: warning: field 'regulator' with variable sized type 'struct regulator' not at the end of a struct or class is a GNU extension [-Wgnu-variable-sized-type-not-at-end]
struct regulator regulator;
^
2 warnings generated.

To achieve this the variable size field entries is removed from
struct regulator_voltages that is renamed struct regulator_voltages_desc.
API function regulator_supported_voltages() and regulator drivers handler
function ::supported_voltages are updated the get 2 input arguments the
second being the levels arrays which size is defined by the description
argument.

Impacted sources files are updated accordingly.

Fixes: 43c155ba111d ("drivers: regulator: list supported levels")
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-sam: fix warnings found during checkpatch

Remove 'extern' from function prototypes in .h files.
Align the parameters in functions.

Signed-off-by: Tony Han <tony.han@microchip.com>
Reviewed-by:

plat-sam: fix warnings found during checkpatch

Remove 'extern' from function prototypes in .h files.
Align the parameters in functions.

Signed-off-by: Tony Han <tony.han@microchip.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: crypto: hisilicon: fix QM cache start and done define

Address offset of qm_cache_wb_start and qm_cache_wb_done
is wrong.

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management

drivers: crypto: hisilicon: fix QM cache start and done define

Address offset of qm_cache_wb_start and qm_cache_wb_done
is wrong.

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) module")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
[Edit commit subject]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

core: panic(): avoid panic in panic

When configured with CFG_HALT_CORES_ON_PANIC=y panic() sends a secure
SGI to all other CPUs to trap all of them, but if interrupts haven't
been configured yet it

core: panic(): avoid panic in panic

When configured with CFG_HALT_CORES_ON_PANIC=y panic() sends a secure
SGI to all other CPUs to trap all of them, but if interrupts haven't
been configured yet it triggers a cascade of panics. So add a check to
see if interrupts are configured before trying to trap the other CPUs.

Fixes: 2b719df0fc1c ("core: interrupt: halt other cores when one is panicking")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

core: add interrupt_get_main_chip_may_fail()

Add interrupt_get_main_chip_may_fail() to be able to check if it's
possible to use interrupts without causing a panic.

Signed-off-by: Jens Wiklander <je

core: add interrupt_get_main_chip_may_fail()

Add interrupt_get_main_chip_may_fail() to be able to check if it's
possible to use interrupts without causing a panic.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

core: dt_driver: do not defer probe on skip phandler arguments

Prevent dt_driver_device_from_node_idx_prop() to request driver probe
deferral when needing to skip phandle arguments cells related to

core: dt_driver: do not defer probe on skip phandler arguments

Prevent dt_driver_device_from_node_idx_prop() to request driver probe
deferral when needing to skip phandle arguments cells related to
providers not yet registered. When skipping these phandle argument cells
we don't really need the skipped provider is registered, we can read
the #xxx-cells property in the provider DT node straight.

For example, consider a driver which DT node defines:
clocks = <&foo_clock 1 2 3>, <&bar_clock 2>;
clock-names = "foo", "bar";
If driver calls clk_get_by_name(fdt, node, "bar"), it does not need to
wait &foo_clock related driver to be already probed, it does not even
need the driver to be ever probed.

Fixes: a22e85b25772 ("core: dt_driver: factorize clk_dt_get_from_provider()")
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...