drivers: stm32_rng: fix comment in stm32_rng_pm_resume()

Fix comment about the application of the RNG configuration in
stm32_rng_pm_resume(). Old comment mentioned reserved bits.

Signed-off-by: Gat

drivers: stm32_rng: fix comment in stm32_rng_pm_resume()

Fix comment about the application of the RNG configuration in
stm32_rng_pm_resume(). Old comment mentioned reserved bits.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: remove __unused attribute

Removes a useless __unused attribute for stm32_rng_probe() argument.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etie

drivers: stm32_rng: remove __unused attribute

Removes a useless __unused attribute for stm32_rng_probe() argument.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: check clock enable call

Fixes clock enable request that does not check the return value.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Ca

drivers: stm32_rng: check clock enable call

Fixes clock enable request that does not check the return value.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: allow cache_op_outer() to operate on non-secure buffers

According the ARM PL310 documentation, if the operation is specific
to the PA, the behavior is presented in the following manner:

core: arm: allow cache_op_outer() to operate on non-secure buffers

According the ARM PL310 documentation, if the operation is specific
to the PA, the behavior is presented in the following manner:
- Secure access: The data in the cache is only affected by the
the operation if it is secure.
- Non-secure access: The data in the cache is only affected by the
operation if it is non-secure.

Depending on the buffer location, use the secure or non-secure PL310
base address to do physical address based cache operation on the
buffer.

Link: https://developer.arm.com/documentation/ddi0246/a/programmer-s-model/register-descriptions/register-7--cache-maintenance-operations
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat: imx: implement pl310_nsbase()

Map PL310 registers as non-secure.
Implement pl310_nsbase() that returns non-secure PL310 base address.

Signed-off-by: Clement Faure <clement.faure@nxp.com

core: plat: imx: implement pl310_nsbase()

Map PL310 registers as non-secure.
Implement pl310_nsbase() that returns non-secure PL310 base address.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add pl310_nsbase() function

Add pl310_nsbase() function to return non-secure PL310 base address.

The default implementation is a weak function that returns the secure
PL310 base address to ma

core: add pl310_nsbase() function

Add pl310_nsbase() function to return non-secure PL310 base address.

The default implementation is a weak function that returns the secure
PL310 base address to match the previous behavior where only the secure
base address was returned.

It is up to the platform to implement that function.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: sa2ul_rng: check if rng is enabled before to do a read

Check if rng is enabled in sa2ul_rng_read128(), if not the
initialization sequence is run.
After a suspend to ram, the rng may be in r

plat-k3: sa2ul_rng: check if rng is enabled before to do a read

Check if rng is enabled in sa2ul_rng_read128(), if not the
initialization sequence is run.
After a suspend to ram, the rng may be in reset state, and it has to be
re-initialized if in reset state.

Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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pta: stm32mp: fix remoteproc config name

The CFG_RPROC_PTA config is not valid and has been replaced by the
CFG_REMOTEPROC_PTA config during the review process.

Fixes: f6c57ea446db ("pta: stm32mp:

pta: stm32mp: fix remoteproc config name

The CFG_RPROC_PTA config is not valid and has been replaced by the
CFG_REMOTEPROC_PTA config during the review process.

Fixes: f6c57ea446db ("pta: stm32mp: add new remoteproc PTA")
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Include kernel/interrupt.h for thread_arch.c

Otherwise, the compiler can not find the declaration of
interrupt_main_handler().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-

core: riscv: Include kernel/interrupt.h for thread_arch.c

Otherwise, the compiler can not find the declaration of
interrupt_main_handler().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Add missing initial value for read_tp()

The stack variable "tp" should have its initial value.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wikland

core: riscv: Add missing initial value for read_tp()

The stack variable "tp" should have its initial value.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: plic: Fix parameter type of plic_op_raise_sgi()

The commit ec740b9fe95e ("core: interrupt_raise_sgi() updates") changes
the cpu_mask parameter to a uint32_t. Apply this change onto
plic_op_

drivers: plic: Fix parameter type of plic_op_raise_sgi()

The commit ec740b9fe95e ("core: interrupt_raise_sgi() updates") changes
the cpu_mask parameter to a uint32_t. Apply this change onto
plic_op_raise_sgi().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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driver: crypto: hisilicon: Add the mailbox operation lock

refactor function of mailbox operation to ensure atomaticity

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) modul

driver: crypto: hisilicon: Add the mailbox operation lock

refactor function of mailbox operation to ensure atomaticity

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) module")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: read_64bit_pair()

Implement read_64bit_pair that read two 64 bits data together.

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-sam: force CFG_EXTERNAL_DT to n

Because this feature isn't used on SAM platforms and to disable DT
insecure warning.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jens Wik

plat-sam: force CFG_EXTERNAL_DT to n

Because this feature isn't used on SAM platforms and to disable DT
insecure warning.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: secure pins for peripherals used in the secure world

These pins are used by RCC MCO and the I2C4. As these peripherals are
used in OP-TEE, secure them.

Signed-off-by: Gatien Chevallier

dts: stm32: secure pins for peripherals used in the secure world

These pins are used by RCC MCO and the I2C4. As these peripherals are
used in OP-TEE, secure them.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: add secure configuration for GPIOs

This change adds security support for GPIOS. A bank of GPIO now has a
secure support and configuration.

Secure support is defined in the devi

drivers: stm32_gpio: add secure configuration for GPIOs

This change adds security support for GPIOS. A bank of GPIO now has a
secure support and configuration.

Secure support is defined in the device tree. If a GPIO bank is defined
as secure, the secure configuration is read through st,protreg device
tree property and is applied during probe.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: add TZPROT macro

Add TZPROT macro to define the security level for GPIOs

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carrier

dt-bindings: add TZPROT macro

Add TZPROT macro to define the security level for GPIOs

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: fix coding style issues

Prefer U(x) in definition of macros for unsigned ints.

Signed-off-by: Gatien Chevallier <gatien.chevallier@st.com>
Reviewed-by: Etienne Carriere <etienn

drivers: stm32_gpio: fix coding style issues

Prefer U(x) in definition of macros for unsigned ints.

Signed-off-by: Gatien Chevallier <gatien.chevallier@st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: fix iteration in set_bank_gpio_non_secure()

The for loop iterates over one too many elements.

Fixes: be53ee7b15f6 ("plat-stm32mp1: fix default setting GPIO as non-secure")
Sign

drivers: stm32_gpio: fix iteration in set_bank_gpio_non_secure()

The for loop iterates over one too many elements.

Fixes: be53ee7b15f6 ("plat-stm32mp1: fix default setting GPIO as non-secure")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: fix test on CFG_STM32_UART

Fix test directive on CFG_STM32_UART that boolean CFG_ configuration
switches do not have a meaningful value.

Fixes: bd1fffe512ce ("plat-stm32mp2: add new

plat-stm32mp2: fix test on CFG_STM32_UART

Fix test directive on CFG_STM32_UART that boolean CFG_ configuration
switches do not have a meaningful value.

Fixes: bd1fffe512ce ("plat-stm32mp2: add new platform support")
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: kernel_spmc: correct CFG_SECURE_PARTITION test

Replace occurrences of #if CFG_SECURE_PARTITION to a #ifdef test
as boolean CFG_ configuration switches do not have a meaningful value.

Fix

core: arm: kernel_spmc: correct CFG_SECURE_PARTITION test

Replace occurrences of #if CFG_SECURE_PARTITION to a #ifdef test
as boolean CFG_ configuration switches do not have a meaningful value.

Fixes: 4d0288475267 ("core: spmc: handle non-secure interrupts")
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_iwdg: enable state helper functions

Add iwdg_wdt_set_enabled() to register the watchdog is activated
and rename is_enable() to iwdg_wdt_is_enabled() for consistency.

Acked-by: Jerome

drivers: stm32_iwdg: enable state helper functions

Add iwdg_wdt_set_enabled() to register the watchdog is activated
and rename is_enable() to iwdg_wdt_is_enabled() for consistency.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_iwdg: enable bus clock once for all

Enable STM32 IWDG driver bus clock together with the IWDG kernel
clock when the driver is initialized. This clock is needed to propagate
IWDG early

drivers: stm32_iwdg: enable bus clock once for all

Enable STM32 IWDG driver bus clock together with the IWDG kernel
clock when the driver is initialized. This clock is needed to propagate
IWDG early interrupt to the system.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>

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drivers: stm32_iwdg: rename bus clock to clk_pclk

Rename STM32 IWDG watchdog bus clock clk_pclk, matching the reference
manual naming instead of clock.

Acked-by: Jerome Forissier <jerome.forissier@

drivers: stm32_iwdg: rename bus clock to clk_pclk

Rename STM32 IWDG watchdog bus clock clk_pclk, matching the reference
manual naming instead of clock.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_iwdg: remove stm32_iwdg_refresh()

Remove unused stm32_iwdg_refresh() intended to refresh all registered
watchdog devices.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Rev

drivers: stm32_iwdg: remove stm32_iwdg_refresh()

Remove unused stm32_iwdg_refresh() intended to refresh all registered
watchdog devices.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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