core: arm: kernel: add runtime check for CE

Add runtime check during boot for supported ARMv8 Crypto Extensions.
Core will panic if configuration enables an ARMv8 CE feature
that the hardware does n

core: arm: kernel: add runtime check for CE

Add runtime check during boot for supported ARMv8 Crypto Extensions.
Core will panic if configuration enables an ARMv8 CE feature
that the hardware does not support.

Link: https://github.com/OP-TEE/optee_os/issues/6631
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: add helper functions for checking CE support

Add helper functions for checking implementation of SHA1, SHA256,
SHA512, SHA3, SM3, SM4 instructions.

Acked-by: Etienne Carriere <etienne.ca

core: arm: add helper functions for checking CE support

Add helper functions for checking implementation of SHA1, SHA256,
SHA512, SHA3, SM3, SM4 instructions.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: add check in aarch32 for feat_crc32_implemented()

Add support for checking CRC32 HW instruction in aarch32.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wik

core: arm: add check in aarch32 for feat_crc32_implemented()

Add support for checking CRC32 HW instruction in aarch32.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm64: remove ID_AA64ISAR0_EL1 macros

Remove old definitions for ID_AA64ISAR0_EL1 CRC32 bitmask
and shift.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander

core: arm64: remove ID_AA64ISAR0_EL1 macros

Remove old definitions for ID_AA64ISAR0_EL1 CRC32 bitmask
and shift.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: rewrite feat_crc32_implemented()

Rewrite check in feat_crc32_implementedfor for ARM64.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklande

core: arm: rewrite feat_crc32_implemented()

Rewrite check in feat_crc32_implementedfor for ARM64.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm64: add masks for ID_AA64ISAR0_EL1 fields

Add masks for obtaining Crypto Extensions support status from
ID_AA64ISAR0_EL1 register:

Algo Bits
SM4 - [43:40]
SM3 - [39:36]
SHA

core: arm64: add masks for ID_AA64ISAR0_EL1 fields

Add masks for obtaining Crypto Extensions support status from
ID_AA64ISAR0_EL1 register:

Algo Bits
SM4 - [43:40]
SM3 - [39:36]
SHA3 - [35:32]
RDM - [31:28]
TME - [27:24]
Atomic - [23:20]
CRC32 - [19:16]
SHA2 - [15:12]
SHA1 - [11:8]
AES - [7:4]

For additional details check ARM Architecture Reference Manual
for ARMv8-A architecture profile.
ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: add masks for ID_ISAR5_EL1 fields

Add masks for obtaining Crypto Extensions support status from
ID_ISAR5_EL1 register:

Algo Bits
CRC32 - [19:16]
SHA2 - [15:12]
SHA1 - [1

core: arm: add masks for ID_ISAR5_EL1 fields

Add masks for obtaining Crypto Extensions support status from
ID_ISAR5_EL1 register:

Algo Bits
CRC32 - [19:16]
SHA2 - [15:12]
SHA1 - [11:8]
AES - [7:4]

For additional details check ARM Architecture Reference Manual
for ARMv8-A architecture profile.
D10.2.66 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: virt, ffa: keep guest partition until resources are reclaimed

Move a struct guest_partition to prtn_destroy_list if there are
resources remaining to be reclaimed by the hypervisor. Currently t

core: virt, ffa: keep guest partition until resources are reclaimed

Move a struct guest_partition to prtn_destroy_list if there are
resources remaining to be reclaimed by the hypervisor. Currently this is
needed with FF-A and SPMC at S-EL1.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: store shm_bits in partition for SPMC at S-EL1

Store the bitmask keeping track of allocated shared memory handles in
the current partition when configured with CFG_NS_VIRTUALIZATION and
CF

core: ffa: store shm_bits in partition for SPMC at S-EL1

Store the bitmask keeping track of allocated shared memory handles in
the current partition when configured with CFG_NS_VIRTUALIZATION and
CFG_CORE_SEL1_SPMC.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: add SPMC_CORE_SEL1_MAX_SHM_COUNT

Add SPMC_CORE_SEL1_MAX_SHM_COUNT, telling how many shared memory object
are supported in a configuration with SPMC at S-EL1.

Signed-off-by: Jens Wiklande

core: ffa: add SPMC_CORE_SEL1_MAX_SHM_COUNT

Add SPMC_CORE_SEL1_MAX_SHM_COUNT, telling how many shared memory object
are supported in a configuration with SPMC at S-EL1.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: thread_spmc.c: add set_simple_ret_val()

Simplify common FFA_ERRROR/FFA_SUCCESS_32 patterns where an error code
is returned on error or FFA_SUCCESS_32 without further values are used
on success

core: thread_spmc.c: add set_simple_ret_val()

Simplify common FFA_ERRROR/FFA_SUCCESS_32 patterns where an error code
is returned on error or FFA_SUCCESS_32 without further values are used
on success.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: wait for writes to propagate

Some updates to the GIC redistributor takes a while before they are
visible to all agents in the system. The GICR_CTLR_RWP bit in GICR_CTLR
indicates if updat

core: gic: wait for writes to propagate

Some updates to the GIC redistributor takes a while before they are
visible to all agents in the system. The GICR_CTLR_RWP bit in GICR_CTLR
indicates if updates are still being propagated. Add checks for this
after each write to GICR_ICENABLER0 to make sure that the system is
consistent before continuing.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: support to configure PPI interrupts

Add support to configure PPI interrupts (assigning to Secure Group 1
etc). Since PPIs are per CPU interrupts as SGIs their configuration
should be sync

core: gic: support to configure PPI interrupts

Add support to configure PPI interrupts (assigning to Secure Group 1
etc). Since PPIs are per CPU interrupts as SGIs their configuration
should be synchronized to all CPUs in the same way. Add support to
synchronize needed PPI configuration to other CPUs.

The configuration that needs to be synchronized to other CPUs should
ideally not be changed once the primary CPU has booted. So add a check
in gic_op_enable() to catch this.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: call init_multi_core_panic_handler() earlier

Call init_multi_core_panic_handler() slightly earlier in during boot
using nex_driver_init_late() instead of boot_final(). This avoids with a
comin

core: call init_multi_core_panic_handler() earlier

Call init_multi_core_panic_handler() slightly earlier in during boot
using nex_driver_init_late() instead of boot_final(). This avoids with a
coming assert() in the GIC driver to check that SGI and PPI can't be
configured after or at nex_release_init_resource().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Fix PTE creation when freeing PTE

The core_mmu_pte_create() is also called when MM core frees the pages,
which means the PTE should be zero. Current implementation always sets
valid bit

core: riscv: Fix PTE creation when freeing PTE

The core_mmu_pte_create() is also called when MM core frees the pages,
which means the PTE should be zero. Current implementation always sets
valid bit (V), which is not proper way when clearing PTE. Fix it by only
honoring pte_bits parameter, which may be constructed in
mattr_to_pte_bits().

The core_mmu_ptp_create() is used to create non-leaf PTE, which points
to the next level of the page table. According to RISC-V privilege Spec,
non-leaf PTE only needs V bit. Therefore, we just give the V bit to
core_mmu_pte_create() when we want to create non-leaf PTE.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Rename mattr_to_perms() to mattr_to_pte_bits()

This function not only constructs permission bits (R, W, X) of PTE, but
also other bits such as valid bit (V), user bit (U), global bit (G

core: riscv: Rename mattr_to_perms() to mattr_to_pte_bits()

This function not only constructs permission bits (R, W, X) of PTE, but
also other bits such as valid bit (V), user bit (U), global bit (G),
accessed bit (A), and dirty bit (D). Rename it to mattr_to_pte_bits()
for greater readability.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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drivers: clk: clk-stm32mp13: round up VCO to the nearest frequency

Round up the vco clock to avoid unexpected clock rate:
- 999,999,023 Hz instead 1,000,000,000 Hz
- 417,755,859 Hz instead 417,800,0

drivers: clk: clk-stm32mp13: round up VCO to the nearest frequency

Round up the vco clock to avoid unexpected clock rate:
- 999,999,023 Hz instead 1,000,000,000 Hz
- 417,755,859 Hz instead 417,800,000 Hz

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: clk-stm32mp13: don't gate/ungate oscillators not wired

If an oscillator is not wired we shouldn't gate it to avoid a panic.
For example the external LSE oscillator may not be supported

drivers: clk: clk-stm32mp13: don't gate/ungate oscillators not wired

If an oscillator is not wired we shouldn't gate it to avoid a panic.
For example the external LSE oscillator may not be supported on a board
in which case node named clk-lse is disabled in the board DTS file.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: clk-stm32mp13: add ADC and SPI clocks

Add definition of ADCs and SPI buses clocks for platform variant
STM32MP13.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed

drivers: clk: clk-stm32mp13: add ADC and SPI clocks

Add definition of ADCs and SPI buses clocks for platform variant
STM32MP13.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mmu: add MEM_AREA_ROM_SEC in check_mem_map()

Handle MEM_AREA_ROM_SEC in check_mem_map() switch case to prevent OP-TEE
core from panicking when such area is mapped.

Fixes: fc7e0cc38b99 ("core:

core: mmu: add MEM_AREA_ROM_SEC in check_mem_map()

Handle MEM_AREA_ROM_SEC in check_mem_map() switch case to prevent OP-TEE
core from panicking when such area is mapped.

Fixes: fc7e0cc38b99 ("core: MEM_AREA_ROM_SEC maps secure read only cached memory")
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: caam: add CAAM key support for DH

Add CAAM key support for DH.
Add DH black key support for shared secret generation.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sa

drivers: caam: add CAAM key support for DH

Add CAAM key support for DH.
Add DH black key support for shared secret generation.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM key support for ECC

Add CAAM key support for ECC.
Add RSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@n

drivers: caam: add CAAM key support for ECC

Add CAAM key support for ECC.
Add RSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM key support for DSA

Add CAAM key support for DSA.
Add DSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@n

drivers: caam: add CAAM key support for DSA

Add CAAM key support for DSA.
Add DSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM key support for RSA

Add CAAM key support for RSA.
Add RSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@n

drivers: caam: add CAAM key support for RSA

Add CAAM key support for RSA.
Add RSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM key driver

Add CAAM key driver and CAAM key object.
Add key blob encapsulation methods.
Add key serialize and deserialize functions for bignum encapsulation.

Signed-off-by:

drivers: caam: add CAAM key driver

Add CAAM key driver and CAAM key object.
Add key blob encapsulation methods.
Add key serialize and deserialize functions for bignum encapsulation.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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