drivers: regulator: do not cache voltage level value

Always read current voltage level from the device instead of
caching the level in struct regulator. This fixes issues for
when the regulator leve

drivers: regulator: do not cache voltage level value

Always read current voltage level from the device instead of
caching the level in struct regulator. This fixes issues for
when the regulator level value depends on the parent regulator
(supply). It is up the regulator drivers to cache or not this
value in their private data if applicable.

Fixes: 1a3d3273040b ("drivers: regulator framework")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add __must_check attribute to cpu_spin_lock_xsave()

cpu_spin_lock_xsave() masks exceptions, takes the spinlock and returns
previous exception state to be restored by cpu_spin_unlock_xrestore()

core: add __must_check attribute to cpu_spin_lock_xsave()

cpu_spin_lock_xsave() masks exceptions, takes the spinlock and returns
previous exception state to be restored by cpu_spin_unlock_xrestore().
The previously returned exception state must always be supplied so add
the __must_check attribute to cpu_spin_lock_xsave() and its debug
variants.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: kernel: add timeout_elapsed_us()

Add API function timeout_elapsed_us() to measure to time since or until
an initialized timeout reference elapses.

This function relies on other timeout_*() AP

core: kernel: add timeout_elapsed_us()

Add API function timeout_elapsed_us() to measure to time since or until
an initialized timeout reference elapses.

This function relies on other timeout_*() API functions are therefore
depends on CFG_CORE_HAS_GENERIC_TIMER being enabled.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: factorize delay and timeout implementation

Factorize RISC-V and Arm architectures implementation of delay and
timeout API functions into generic core kernel source directory.

Architec

core: kernel: factorize delay and timeout implementation

Factorize RISC-V and Arm architectures implementation of delay and
timeout API functions into generic core kernel source directory.

Architecture or platform only need to implement timer tick count
read function delay_cnt_read() and timer tick frequency (in Hertz)
delay_cnt_freq() which is related to CFG_CORE_HAS_GENERIC_TIMER support.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: force enable of CFG_CORE_HAS_GENERIC_TIMER

Ensure CFG_CORE_HAS_GENERIC_TIMER is enabled for RISC-V architecture
since the current implementation provides the necessary routines
in delay

core: riscv: force enable of CFG_CORE_HAS_GENERIC_TIMER

Ensure CFG_CORE_HAS_GENERIC_TIMER is enabled for RISC-V architecture
since the current implementation provides the necessary routines
in delay_arch.h outside any configuration switch directive. This change
clarifies riscv based platforms configuration that previously depended
on CFG_CORE_HAS_GENERIC_TIMER default enabling from mk/config.mk.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: describe udelay()/mdelay()

Add inline description comment for udelay() and mdelay() for
consistency of OP-TEE OS source tree, even if the function names
are quite explicit and do not s

core: kernel: describe udelay()/mdelay()

Add inline description comment for udelay() and mdelay() for
consistency of OP-TEE OS source tree, even if the function names
are quite explicit and do not strictly need such descriptions.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: disable PL011-specific code when CFG_SEMIHOSTING_CONSOLE=y

When the semihosting console is enabled (with CFG_SEMIHOSTING=y
CFG_SEMIHOSTING_CONSOLE=y) then some code in plat-vexpress/m

plat-vexpress: disable PL011-specific code when CFG_SEMIHOSTING_CONSOLE=y

When the semihosting console is enabled (with CFG_SEMIHOSTING=y
CFG_SEMIHOSTING_CONSOLE=y) then some code in plat-vexpress/main.c
doesn't make sense and needs to be disabled.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64: implement __do_semihosting() for Aarch64

Implement __do_semihosting() as documented in the "Semihosting for
Aarch32 and Aarch64" specification [1].

Link: https://github.com/ARM-softwar

core: arm64: implement __do_semihosting() for Aarch64

Implement __do_semihosting() as documented in the "Semihosting for
Aarch32 and Aarch64" specification [1].

Link: https://github.com/ARM-software/abi-aa/blob/2023Q3/semihosting/semihosting.rst [1]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: imx: enable TZC380 driver for all i.mx8m socs

This enables the TrustZone Address Space Controller (TZ380) driver for
all members of the i.MX8M soc family. Enabling the driver ensures
protectio

core: imx: enable TZC380 driver for all i.mx8m socs

This enables the TrustZone Address Space Controller (TZ380) driver for
all members of the i.MX8M soc family. Enabling the driver ensures
protection of the OP-TEE memory regions, so that only the secure world
can access it.

Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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riscv: sbi_console: prefer SBI v2.0 DBCN ecall over legacy sbi_console_putchar()

As the legacy sbi_console_putchar() may be deprecated in the future,
it is recommended to use sbi_dbcn_write_byte() p

riscv: sbi_console: prefer SBI v2.0 DBCN ecall over legacy sbi_console_putchar()

As the legacy sbi_console_putchar() may be deprecated in the future,
it is recommended to use sbi_dbcn_write_byte() provided by SBI v2.0
DBCN extension [1]. However, if the DBCN extension is not supported,
sbi_console_putchar() can still be used as the last resort.

Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/v2.0/src/ext-debug-console.adoc#function-console-write-byte-fid-2 [1]
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: sbi_console: remove unused sbi_console_flush()

sbi_console_flush() won't be implemented, remove the empty function.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Al

riscv: sbi_console: remove unused sbi_console_flush()

sbi_console_flush() won't be implemented, remove the empty function.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: sbi_console: remove global spinlock

sbi_console_putc() has been protected by puts_lock, so
remove the superfluous spinlock.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewe

riscv: sbi_console: remove global spinlock

sbi_console_putc() has been protected by puts_lock, so
remove the superfluous spinlock.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: sbi_console: remove unneeded #ifdef CFG_RISCV_SBI_CONSOLE

sbi_console.c has been assigned conditionally based on
CFG_RISCV_SBI_CONSOLE in sub.mk. Remove the #ifdef preprocessor
directive.

Si

riscv: sbi_console: remove unneeded #ifdef CFG_RISCV_SBI_CONSOLE

sbi_console.c has been assigned conditionally based on
CFG_RISCV_SBI_CONSOLE in sub.mk. Remove the #ifdef preprocessor
directive.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: sbi_console: split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR

Split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR definition for better
readability. Also, provide a function description.

Signed-off-by:

riscv: sbi_console: split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR

Split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR definition for better
readability. Also, provide a function description.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: sbi: minor cleanup for SBI HSM related definitions

Rename sbi_boot_hart() to sbi_hsm_hart_start() and use enumerated
type for function ID definition for better clarity and consistency
with th

riscv: sbi: minor cleanup for SBI HSM related definitions

Rename sbi_boot_hart() to sbi_hsm_hart_start() and use enumerated
type for function ID definition for better clarity and consistency
with the following commits.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: at91: add device trees for sama7g54_ek

Add the header file for pin definitions.
Add dtsi & dts files for sama7g54_ek.

Signed-off-by: Tony Han <tony.han@microchip.com>
[TP: Update device trees

dts: at91: add device trees for sama7g54_ek

Add the header file for pin definitions.
Add dtsi & dts files for sama7g54_ek.

Signed-off-by: Tony Han <tony.han@microchip.com>
[TP: Update device trees for sama7g54_ek according kernel dtsi and
dts files for the sama7g54_ek.]
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: sam: skip the NULL clocks when getting the clock by name

Skip the NULL items in the clock array when getting the clock by its name.

Signed-off-by: Tony Han <tony.han@microchip.com>
Ac

drivers: clk: sam: skip the NULL clocks when getting the clock by name

Skip the NULL items in the clock array when getting the clock by its name.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: sam: add sama7g5 clock description

Define PLL, master, system, peripheral, generic clocks for sama7g5 and
register the clocks to clock provider.

Signed-off-by: Tony Han <tony.han@micr

drivers: clk: sam: add sama7g5 clock description

Define PLL, master, system, peripheral, generic clocks for sama7g5 and
register the clocks to clock provider.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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dts: sama5d2: add huk node for the NVMEM hardware unique key

Add the definition of the NVMEM HUK controller in the sama5d2
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acke

dts: sama5d2: add huk node for the NVMEM hardware unique key

Add the definition of the NVMEM HUK controller in the sama5d2
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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dts: sama5d2: add NVMEM die_id node

Add the definition of the NVMEM die id controller in the sama5d2
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier

dts: sama5d2: add NVMEM die_id node

Add the definition of the NVMEM die id controller in the sama5d2
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-sam: enable NVMEM unique hardware key and die id support

Enable NVMEM support to allow reading hardware unique key from
the fuses.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Sign

plat-sam: enable NVMEM unique hardware key and die id support

Enable NVMEM support to allow reading hardware unique key from
the fuses.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: nvmem: add nvmem-huk driver

This driver is meant to read the OTP unique hardware key from a
NVMEM controller. It uses the nvmem framework to read the NVMEM
cells from the device tree.

Sign

drivers: nvmem: add nvmem-huk driver

This driver is meant to read the OTP unique hardware key from a
NVMEM controller. It uses the nvmem framework to read the NVMEM
cells from the device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: nvmem: add nvmem-die-id driver

This driver is meant to read the die id from a NVMEM controller.
It uses the nvmem framework to read the NVMEM cells from the
device tree.

Signed-off-by: Tho

drivers: nvmem: add nvmem-die-id driver

This driver is meant to read the die id from a NVMEM controller.
It uses the nvmem framework to read the NVMEM cells from the
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: Implement semihosting based console driver for log

Implement a simple console driver which uses semihosting operations to
read/write the trace messages. There are two paths to output the tr

drivers: Implement semihosting based console driver for log

Implement a simple console driver which uses semihosting operations to
read/write the trace messages. There are two paths to output the trace
messages:
- If the caller of semihosting_console_init() provides the path of the
file, the driver will try to open that file, and output the log to
that host side file.
- If the caller of semihosting_console_init() does not provide the path
of the file, the driver will connect the console to the host debug
console directly.

If CFG_SEMIHOSTING_CONSOLE is enabled, OP-TEE will try to initialize the
semihosting console driver by given CFG_SEMIHOSTING_CONSOLE_FILE.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console

core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console drivers (e.g., semihosting console).

If the cross-platform console drivers are not configured to be compiled,
plat_console_init() will be invoked to initialize platform-specific
console driver.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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