plat-stm32mp2: conf: support HSEM driver

Default enable HSEM driver for platform stm32mp2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carri

plat-stm32mp2: conf: support HSEM driver

Default enable HSEM driver for platform stm32mp2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: add RIF support driver for HSEM

This driver implements RIF configuration for HSEM, which is a RIF
aware IP. It means that the HSEM driver is in charge of configuring its
own RIF restriction

drivers: add RIF support driver for HSEM

This driver implements RIF configuration for HSEM, which is a RIF
aware IP. It means that the HSEM driver is in charge of configuring its
own RIF restrictions and that the HSEM has dedicated RIF configuration
registers.

HSEM has two types of CID filtering registers.
-For processor filtering : HSEM_CnCIDCFGR
When CFEN is enabled: processor[n] CID filtering enabled for HSEM_(S)CnIER,
HSEM_(S)CnICR, HSEM_(S)CnISR, and HSEM_(S)CnMISR registers and for allowed
list filter usage in HSEM_GpCIDCFGR.SEM_WLIST_Cn. The CID is put in the
CID bitfield.

-For semaphore group filtering : HSEM_GpCIDCFGR
Used to apply CID filtering over a group of semaphore. The same policy
applies to all semaphores present in the group. This register handles
what are the processor's CID who are white-listed for the group in the
SEM_WLIST_C bitfield.

Therefore, both these registers are interconnected.

Security and privilege configuration granularity expands to each individual
semaphore.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add HPDMA1/2/3 nodes in stm32mp251.dtsi

Add HPDMA1/2/3 nodes and default disable them.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etien

dts: stm32: add HPDMA1/2/3 nodes in stm32mp251.dtsi

Add HPDMA1/2/3 nodes and default disable them.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: conf: support HPDMA driver

Default enable HPDMA driver for platform stm32mp2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.car

plat-stm32mp2: conf: support HPDMA driver

Default enable HPDMA driver for platform stm32mp2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: add HPDMA driver with RIF support

This driver implements RIF configuration for HPDMA, which is a RIF aware
IP. It means that the HPDMA driver is in charge of configuring its own RIF
restric

drivers: add HPDMA driver with RIF support

This driver implements RIF configuration for HPDMA, which is a RIF aware
IP. It means that the HPDMA driver is in charge of configuring its own RIF
restrictions and that the HPDMA has dedicated RIF configuration registers.

RIF configuration is possible when the executing context is TDCID.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add FMC node in stm32mp251.dtsi

Add the Flexible Memory Controller(FMC) node and default disable it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne C

dts: stm32: add FMC node in stm32mp251.dtsi

Add the Flexible Memory Controller(FMC) node and default disable it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: conf: support FMC driver

Default enable FMC driver for platform stm32mp2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carrier

plat-stm32mp2: conf: support FMC driver

Default enable FMC driver for platform stm32mp2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: add FMC driver with RIF support

This driver implements RIF configuration for FMC, which is a RIF aware IP.
It means that the FMC driver is in charge of configuring its own RIF
restrictions

drivers: add FMC driver with RIF support

This driver implements RIF configuration for FMC, which is a RIF aware IP.
It means that the FMC driver is in charge of configuring its own RIF
restrictions and that the FMC has dedicated RIF configuration registers.

Additional check on RIF configuration is added for this IP when debug is
on.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mutex: add support timeout condvar

Add support timeout condvar based on timeout notify

Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org

core: mutex: add support timeout condvar

Add support timeout condvar based on timeout notify

Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: notif: add support timeout notify

Add support timeout notification, allowing to
avoid waiting indefinitely for the completion of an event

Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Rev

core: notif: add support timeout notify

Add support timeout notification, allowing to
avoid waiting indefinitely for the completion of an event

Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: make sure tee_entry_get_os_revision() uses a proper TEE_IMPL_GIT_SHA1

tee_entry_get_os_revision() stores TEE_IMPL_GIT_SHA1 into a 32 or
64-bit register, depending on the platform. Unfortunatel

core: make sure tee_entry_get_os_revision() uses a proper TEE_IMPL_GIT_SHA1

tee_entry_get_os_revision() stores TEE_IMPL_GIT_SHA1 into a 32 or
64-bit register, depending on the platform. Unfortunately the command
that creates TEE_IMPL_GIT_SHA1 does not provide any guarantee that the
value will fit. For instance it can happen that 8 characters are not
enough to disambiguate two commits in the repository, in which case
git rev-parse --short=8 will happily return 9 or more characters. In
this case a 32-bit build would display a warning and TEE_IMPL_GIT_SHA1
would be truncated in a way we don't want (discarding the most
significant bits).

Therefore, make sure TEE_IMPL_GIT_SHA1 is exactly 8 or 16 hexadecimal
characters (plus the leading 0x).

The OPTEE_FFA_GET_OS_VERSION operation in handle_blocking_call() has to
be modified since the output is a 32-bit register, and SPMC being a 64-bit
TEE core, TEE_IMPL_GIT_SHA1 is a 64-bit value too.

CI needs updating to avoid the following error:

fatal: detected dubious ownership in repository at
'/__w/optee_os/optee_os'

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Closes: https://github.com/OP-TEE/optee_os/issues/6783
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: firewall: move RIFPROT binding

Move RIFPROT macro definition in stm32mp25-rif.h as it is common
to all RIF-based peripherals.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.s

dt-bindings: firewall: move RIFPROT binding

Move RIFPROT macro definition in stm32mp25-rif.h as it is common
to all RIF-based peripherals.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: fix stm32_rif_semaphore_enabled_and_ok() prototype

The stm32_rif_semaphore_enabled_and_ok() function checks a single CID
at a time, not a bit field.

Fixes: 1506f47af917 ("drivers

drivers: firewall: fix stm32_rif_semaphore_enabled_and_ok() prototype

The stm32_rif_semaphore_enabled_and_ok() function checks a single CID
at a time, not a bit field.

Fixes: 1506f47af917 ("drivers: firewall: add stm32_rif driver for common RIF features")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: add support for Microchip sama7g54-ek board

Add the main functions for sama7g54 initialize, including:
- console_init()
- Matrix, TZC, TZPM, interrupt related
Update conf.mk and Makefile

plat-sam: add support for Microchip sama7g54-ek board

Add the main functions for sama7g54 initialize, including:
- console_init()
- Matrix, TZC, TZPM, interrupt related
Update conf.mk and Makefile for sama7g5 OP-TEE support.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: rename filename for sama5d2 functions to 'platform_sama5d2.c'

Rename 'main.c' to 'platform_sama5d2.c' in 'core/arch/arm/plat-sam'.
Update the makefile accordingly.

Signed-off-by: Tony Han

plat-sam: rename filename for sama5d2 functions to 'platform_sama5d2.c'

Rename 'main.c' to 'platform_sama5d2.c' in 'core/arch/arm/plat-sam'.
Update the makefile accordingly.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: optimize the macro and makefile for building sama5d2 clocks

Rename 'CFG_DRIVERS_SAMA5D2_CLK' to 'CFG_SAMA5D2'.
Adjust the sequence of source files in 'core/drivers/clk/sam/sub.mk'.

Signed

plat-sam: optimize the macro and makefile for building sama5d2 clocks

Rename 'CFG_DRIVERS_SAMA5D2_CLK' to 'CFG_SAMA5D2'.
Adjust the sequence of source files in 'core/drivers/clk/sam/sub.mk'.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_wdt: update "#include" list of the header files

Remove the unused header files from "#include".
"#include" the header files needed explicitly even if they are included
indirectly.

Si

drivers: atmel_wdt: update "#include" list of the header files

Remove the unused header files from "#include".
"#include" the header files needed explicitly even if they are included
indirectly.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_wdt: remove the unused variable from "struct atmel_wdt"

The variable "unsigned long rate" is not used, remove it.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Fo

drivers: atmel_wdt: remove the unused variable from "struct atmel_wdt"

The variable "unsigned long rate" is not used, remove it.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_wdt: upgrade to support sama7g5 watchdog

In sama7g5 there's a DWDT (Dual Watchdog Timer) and the registers
are not the same as the wdt for sama5d2. Here the DWD is handled
as 2 watchd

drivers: atmel_wdt: upgrade to support sama7g5 watchdog

In sama7g5 there's a DWDT (Dual Watchdog Timer) and the registers
are not the same as the wdt for sama5d2. Here the DWD is handled
as 2 watchdogs.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: reset cancellation mask on TA exit

Before this patch, the TA cancellation mask was only reset when the
session was created, but the GP spec requires the cancellation mask to
be reset each time

core: reset cancellation mask on TA exit

Before this patch, the TA cancellation mask was only reset when the
session was created, but the GP spec requires the cancellation mask to
be reset each time a TA is entered via one of its entry points. So fix
this by resetting the cancellation mask each time a TA returns.

Link: https://github.com/OP-TEE/optee_test/issues/731
Fixes: b01047730e77 ("Open-source the TEE Core")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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vexpress-qemu_armv8a: increase CFG_CORE_HEAP_SIZE to 131072

Set the default core heap size for QEMUv8 to 128K because 64K is not
enough to complete the "make check" test with CFG_RPMB_FS=y
CFG_RPMB_

vexpress-qemu_armv8a: increase CFG_CORE_HEAP_SIZE to 131072

Set the default core heap size for QEMUv8 to 128K because 64K is not
enough to complete the "make check" test with CFG_RPMB_FS=y
CFG_RPMB_WRITE_KEY=y.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_i2c: protect bus access with a mutex

Protect concurrent accesses to an STM32 I2C bus with a PM aware mutex.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by:

drivers: stm32_i2c: protect bus access with a mutex

Protect concurrent accesses to an STM32 I2C bus with a PM aware mutex.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: stm32_rifsc: remove use of CFG_PM

Remove use of CFG_PM from STM32 RIFSC driver since this configuration
switch is not defined in OP-TEE OS.

Reviewed-by: Gatien Chevallier <gatien

drivers: firewall: stm32_rifsc: remove use of CFG_PM

Remove use of CFG_PM from STM32 RIFSC driver since this configuration
switch is not defined in OP-TEE OS.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: remove use of CFG_PM

Remove use of CFG_PM from STM32 RNG driver since this configuration
switch is not defined in OP-TEE OS.

Reviewed-by: Gatien Chevallier <gatien.chevallier@fo

drivers: stm32_rng: remove use of CFG_PM

Remove use of CFG_PM from STM32 RNG driver since this configuration
switch is not defined in OP-TEE OS.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32_cryp: add pm to CRYP driver

Add power management support to the CRYP driver through suspend/resume
callbacks.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Sig

drivers: crypto: stm32_cryp: add pm to CRYP driver

Add power management support to the CRYP driver through suspend/resume
callbacks.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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