1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 compatible = "arm,cortex-a35"; 19 device_type = "cpu"; 20 reg = <0>; 21 enable-method = "psci"; 22 }; 23 }; 24 25 psci { 26 compatible = "arm,psci-1.0"; 27 method = "smc"; 28 }; 29 30 intc: interrupt-controller@4ac00000 { 31 compatible = "arm,cortex-a7-gic"; 32 #interrupt-cells = <3>; 33 interrupt-controller; 34 reg = <0x0 0x4ac10000 0x0 0x1000>, 35 <0x0 0x4ac20000 0x0 0x2000>, 36 <0x0 0x4ac40000 0x0 0x2000>, 37 <0x0 0x4ac60000 0x0 0x2000>; 38 #address-cells = <1>; 39 }; 40 41 clocks { 42 clk_hse: clk-hse { 43 #clock-cells = <0>; 44 compatible = "fixed-clock"; 45 clock-frequency = <24000000>; 46 }; 47 48 clk_hsi: clk-hsi { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <64000000>; 52 }; 53 54 clk_lse: clk-lse { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <32768>; 58 }; 59 60 clk_lsi: clk-lsi { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32000>; 64 }; 65 66 clk_msi: clk-msi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <4000000>; 70 }; 71 72 clk_i2sin: clk-i2sin { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <0>; 76 }; 77 78 clocks { 79 clk_rcbsec: clk-rcbsec { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <64000000>; 83 }; 84 }; 85 }; 86 87 soc@0 { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 interrupt-parent = <&intc>; 92 ranges = <0x0 0x0 0x0 0x80000000>; 93 94 hpdma1: dma-controller@40400000 { 95 compatible = "st,stm32-dma3"; 96 reg = <0x40400000 0x1000>; 97 #dma-cells = <4>; 98 status = "disabled"; 99 }; 100 101 hpdma2: dma-controller@40410000 { 102 compatible = "st,stm32-dma3"; 103 reg = <0x40410000 0x1000>; 104 #dma-cells = <4>; 105 status = "disabled"; 106 }; 107 108 hpdma3: dma-controller@40420000 { 109 compatible = "st,stm32-dma3"; 110 reg = <0x40420000 0x1000>; 111 #dma-cells = <4>; 112 status = "disabled"; 113 }; 114 115 rifsc: rifsc@42080000 { 116 compatible = "st,stm32mp25-rifsc"; 117 reg = <0x42080000 0x1000>; 118 #address-cells = <1>; 119 #size-cells = <1>; 120 121 usart2: serial@400e0000 { 122 reg = <0x400e0000 0x400>; 123 status = "disabled"; 124 }; 125 }; 126 127 pinctrl: pinctrl@44240000 { 128 #address-cells = <1>; 129 #size-cells = <1>; 130 compatible = "st,stm32mp257-pinctrl"; 131 ranges = <0 0x44240000 0xa0400>; 132 pins-are-numbered; 133 134 gpioa: gpio@44240000 { 135 gpio-controller; 136 #gpio-cells = <2>; 137 interrupt-controller; 138 #interrupt-cells = <2>; 139 reg = <0x0 0x400>; 140 st,bank-name = "GPIOA"; 141 status = "disabled"; 142 }; 143 144 gpiob: gpio@44250000 { 145 gpio-controller; 146 #gpio-cells = <2>; 147 interrupt-controller; 148 #interrupt-cells = <2>; 149 reg = <0x10000 0x400>; 150 st,bank-name = "GPIOB"; 151 status = "disabled"; 152 }; 153 154 gpioc: gpio@44260000 { 155 gpio-controller; 156 #gpio-cells = <2>; 157 interrupt-controller; 158 #interrupt-cells = <2>; 159 reg = <0x20000 0x400>; 160 st,bank-name = "GPIOC"; 161 status = "disabled"; 162 }; 163 164 gpiod: gpio@44270000 { 165 gpio-controller; 166 #gpio-cells = <2>; 167 interrupt-controller; 168 #interrupt-cells = <2>; 169 reg = <0x30000 0x400>; 170 st,bank-name = "GPIOD"; 171 status = "disabled"; 172 }; 173 174 gpioe: gpio@44280000 { 175 gpio-controller; 176 #gpio-cells = <2>; 177 interrupt-controller; 178 #interrupt-cells = <2>; 179 reg = <0x40000 0x400>; 180 st,bank-name = "GPIOE"; 181 status = "disabled"; 182 }; 183 184 gpiof: gpio@44290000 { 185 gpio-controller; 186 #gpio-cells = <2>; 187 interrupt-controller; 188 #interrupt-cells = <2>; 189 reg = <0x50000 0x400>; 190 st,bank-name = "GPIOF"; 191 status = "disabled"; 192 }; 193 194 gpiog: gpio@442a0000 { 195 gpio-controller; 196 #gpio-cells = <2>; 197 interrupt-controller; 198 #interrupt-cells = <2>; 199 reg = <0x60000 0x400>; 200 st,bank-name = "GPIOG"; 201 status = "disabled"; 202 }; 203 204 gpioh: gpio@442b0000 { 205 gpio-controller; 206 #gpio-cells = <2>; 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 reg = <0x70000 0x400>; 210 st,bank-name = "GPIOH"; 211 status = "disabled"; 212 }; 213 214 gpioi: gpio@442c0000 { 215 gpio-controller; 216 #gpio-cells = <2>; 217 interrupt-controller; 218 #interrupt-cells = <2>; 219 reg = <0x80000 0x400>; 220 st,bank-name = "GPIOI"; 221 status = "disabled"; 222 }; 223 224 gpioj: gpio@442d0000 { 225 gpio-controller; 226 #gpio-cells = <2>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 reg = <0x90000 0x400>; 230 st,bank-name = "GPIOJ"; 231 status = "disabled"; 232 }; 233 234 gpiok: gpio@442e0000 { 235 gpio-controller; 236 #gpio-cells = <2>; 237 interrupt-controller; 238 #interrupt-cells = <2>; 239 reg = <0xa0000 0x400>; 240 st,bank-name = "GPIOK"; 241 status = "disabled"; 242 }; 243 }; 244 245 pinctrl_z: pinctrl-z@46200000 { 246 #address-cells = <1>; 247 #size-cells = <1>; 248 compatible = "st,stm32mp257-z-pinctrl"; 249 ranges = <0 0x46200000 0x400>; 250 pins-are-numbered; 251 252 gpioz: gpio@46200000 { 253 gpio-controller; 254 #gpio-cells = <2>; 255 interrupt-controller; 256 #interrupt-cells = <2>; 257 reg = <0 0x400>; 258 st,bank-name = "GPIOZ"; 259 st,bank-ioport = <11>; 260 status = "disabled"; 261 }; 262 }; 263 264 fmc: memory-controller@48200000 { 265 #address-cells = <2>; 266 #size-cells = <1>; 267 compatible = "st,stm32mp25-fmc2-ebi"; 268 reg = <0x48200000 0x400>; 269 status = "disabled"; 270 271 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 272 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 273 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 274 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 275 <4 0 0x80000000 0x10000000>; /* NAND */ 276 }; 277 }; 278}; 279