| 9ff4f2cc | 05-Aug-2016 |
Jerome Forissier <jerome.forissier@linaro.org> |
arm32: AES using ARMv8-A cryptographic extensions
Add AES acceleration to LibTomCrypt in 32-bit mode using ARMv8 Cryptographic Extensions. Enabled when CFG_CRYPTO_AES_ARM32_CE=y.
The ARMv8 CE assem
arm32: AES using ARMv8-A cryptographic extensions
Add AES acceleration to LibTomCrypt in 32-bit mode using ARMv8 Cryptographic Extensions. Enabled when CFG_CRYPTO_AES_ARM32_CE=y.
The ARMv8 CE assembler code comes from the Linux kernel's arch/arm64/crypto/aes-ce-core.S (contributed by Ard Biesheuvel, Linaro) with minor updates:
- Removed the alignment hints in vld1/vst1 operations, for instance 'vld1.8 {q1}, [r1, :64]!' becomes 'vld1.8 {q1}, [r1]!'. This is required because the input and output buffers may not be 8-byte aligned. - ce_aes_ctr_encrypt(): do not increment the counter on the first block because the C wrapper already did. Do not increment the counter after the last block has been processed either, because the C wrapper will do it before calling ce_aes_ctr_encrypt() again. - aes_xts_decrypt(): drop the 'first' parameter which is not used (it would always be set to 1 by the caller).
Tested on HiKey with xtest [1] for functional tests and aes-perf [2] for speed. In the table below, a mode name followed by a '+' means accelerated with crypto extensions, while no '+' is with acceleration disabled (i.e., CFG_CRYPTO_AES_ARM32_CE=n).
Average encryption speed (MiB/s):
Size | Mode (KiB) | ECB CBC CTR XTS ECB+ CBC+ CTR+ XTS+ ------+-------------------------------------------------- 1 | 14.9 12.7 12.3 10.9 33.8 32.7 33.3 29.1 2 | 18.2 15.4 14.9 13.3 65.0 60.9 62.6 55.4 4 | 20.8 17.3 16.6 15.0 119.3 106.0 112.6 101.0 8 | 22.4 18.2 17.6 16.0 201.6 166.5 182.3 166.7 16 | 23.3 19.0 18.1 16.6 308.1 232.9 264.3 248.3 32 | 23.8 19.3 18.4 16.9 427.7 295.1 346.4 335.1 64 | 24.0 19.5 18.6 17.1 532.8 341.3 411.0 407.6 128 | 24.2 19.6 18.7 17.2 608.1 371.3 454.9 457.5 256 | 24.2 19.6 18.7 17.1 624.4 382.0 463.5 481.6 512 | 24.0 19.4 18.6 17.1 658.8 389.6 477.3 498.3
[1] https://github.com/OP-TEE/optee_test [2] https://github.com/linaro-swg/aes-perf.git
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: David Brown <david.brown@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 34777d46 | 04-Aug-2016 |
Jerome Forissier <jerome.forissier@linaro.org> |
arm64: libtomcrypt: rename AES CE files
aes_arm64_ce.c contains wrapper code for the assembly routines that implement AES using the ARMv8-A cryptographic extensions. It is currently used only in 64-
arm64: libtomcrypt: rename AES CE files
aes_arm64_ce.c contains wrapper code for the assembly routines that implement AES using the ARMv8-A cryptographic extensions. It is currently used only in 64-bit builds, but could be used for 32-bits as well. So, rename it to aes_armv8a_ce.c to better reflect its content and prepare for 32-bit support. Also rename the 64-bit assembly file (aes_modes_arm64_ce_a64.S -> aes_modes_armv8a_ce_a64.S) for consistency. Note: this naming scheme (xyz_armv8a_ce.c / xyz_armv8a_ce_a{32,64}.S) is already used for SHA1 and SHA2.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: David Brown <david.brown@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 3b0115a7 | 02-Feb-2016 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: ltc: allocate memory pool unlocked
Allocate the LTC memory pool without the TEE_PAGER_AREA_LOCK to allow paging out data and make more physical pages available for paging.
Reviewed-by: Jerome
core: ltc: allocate memory pool unlocked
Allocate the LTC memory pool without the TEE_PAGER_AREA_LOCK to allow paging out data and make more physical pages available for paging.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: David Brown <david.brown@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 092a2b76 | 24-Jan-2016 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: pager: add support to page out r/w pages
Adds support in pager to page out read-write pages by encrypting them with AES-GCM to avoid leaking sensitive information. With this patch there are th
core: pager: add support to page out r/w pages
Adds support in pager to page out read-write pages by encrypting them with AES-GCM to avoid leaking sensitive information. With this patch there are three different ways of providing virtual memory: - read only, where each page is protected with a SHA-256 hash - read write locked, corresponding with previous zero initialized where mapped pages are removed from the usual pool of physical pages and only returned on explicit release - read write, *new* dirty read write pages triggers update to the storage using encryption (AES-GCM) before the page is reused.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: David Brown <david.brown@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 80d254e7 | 03-Feb-2016 |
Jens Wiklander <jens.wiklander@linaro.org> |
ltc: provide rng_generate()
Adds rng_generate() to the tee_crypt_provider interface to be used by pager and early initialization code where the complete crypto library might not be available.
Revie
ltc: provide rng_generate()
Adds rng_generate() to the tee_crypt_provider interface to be used by pager and early initialization code where the complete crypto library might not be available.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: David Brown <david.brown@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| d3295019 | 16-Mar-2016 |
Pascal Brand <pascal.brand@st.com> |
LTC: no definition of LTC_NO_FAST
LTC_NO_FAST resets LTC_FAST if the latter has been set. Indeed, LTC_FAST is never set on ARM architecture, so LTC_NO_FAST has no effect
Reviewed-by: Jerome Forissi
LTC: no definition of LTC_NO_FAST
LTC_NO_FAST resets LTC_FAST if the latter has been set. Indeed, LTC_FAST is never set on ARM architecture, so LTC_NO_FAST has no effect
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Pascal Brand <pascal.brand@st.com>
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