1 /* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <platform_config.h> 28 #include <kernel/panic.h> 29 #include <kernel/thread.h> 30 #include <kernel/thread_defs.h> 31 #include "thread_private.h" 32 #include <sm/sm_defs.h> 33 #include <sm/sm.h> 34 #include <sm/teesmc.h> 35 #include <sm/teesmc_optee.h> 36 #include <arm.h> 37 #include <kernel/tz_proc_def.h> 38 #include <kernel/tz_proc.h> 39 #include <kernel/misc.h> 40 #include <mm/tee_mmu.h> 41 #include <mm/tee_mmu_defs.h> 42 #include <mm/tee_mm.h> 43 #include <mm/tee_pager.h> 44 #include <kernel/tee_ta_manager.h> 45 #include <util.h> 46 #include <trace.h> 47 #include <assert.h> 48 49 #ifdef ARM32 50 #define STACK_TMP_SIZE 1024 51 #define STACK_THREAD_SIZE 8192 52 53 #if TRACE_LEVEL > 0 54 #define STACK_ABT_SIZE 2048 55 #else 56 #define STACK_ABT_SIZE 1024 57 #endif 58 59 #endif /*ARM32*/ 60 61 #ifdef ARM64 62 #define STACK_TMP_SIZE 2048 63 #define STACK_THREAD_SIZE 8192 64 65 #if TRACE_LEVEL > 0 66 #define STACK_ABT_SIZE 3072 67 #else 68 #define STACK_ABT_SIZE 1024 69 #endif 70 #endif /*ARM64*/ 71 72 #define RPC_MAX_PARAMS 2 73 74 struct thread_ctx threads[CFG_NUM_THREADS]; 75 76 static struct thread_core_local thread_core_local[CFG_TEE_CORE_NB_CORE]; 77 78 #ifdef CFG_WITH_STACK_CANARIES 79 #ifdef ARM32 80 #define STACK_CANARY_SIZE (4 * sizeof(uint32_t)) 81 #endif 82 #ifdef ARM64 83 #define STACK_CANARY_SIZE (8 * sizeof(uint32_t)) 84 #endif 85 #define START_CANARY_VALUE 0xdededede 86 #define END_CANARY_VALUE 0xabababab 87 #define GET_START_CANARY(name, stack_num) name[stack_num][0] 88 #define GET_END_CANARY(name, stack_num) \ 89 name[stack_num][sizeof(name[stack_num]) / sizeof(uint32_t) - 1] 90 #else 91 #define STACK_CANARY_SIZE 0 92 #endif 93 94 #define DECLARE_STACK(name, num_stacks, stack_size) \ 95 static uint32_t name[num_stacks][ \ 96 ROUNDUP(stack_size + STACK_CANARY_SIZE, STACK_ALIGNMENT) / \ 97 sizeof(uint32_t)] \ 98 __attribute__((section(".nozi.stack"), \ 99 aligned(STACK_ALIGNMENT))) 100 101 #define GET_STACK(stack) \ 102 ((vaddr_t)(stack) + sizeof(stack) - STACK_CANARY_SIZE / 2) 103 104 DECLARE_STACK(stack_tmp, CFG_TEE_CORE_NB_CORE, STACK_TMP_SIZE); 105 DECLARE_STACK(stack_abt, CFG_TEE_CORE_NB_CORE, STACK_ABT_SIZE); 106 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 107 DECLARE_STACK(stack_sm, CFG_TEE_CORE_NB_CORE, SM_STACK_SIZE); 108 #endif 109 #ifndef CFG_WITH_PAGER 110 DECLARE_STACK(stack_thread, CFG_NUM_THREADS, STACK_THREAD_SIZE); 111 #endif 112 113 const vaddr_t stack_tmp_top[CFG_TEE_CORE_NB_CORE] = { 114 GET_STACK(stack_tmp[0]), 115 #if CFG_TEE_CORE_NB_CORE > 1 116 GET_STACK(stack_tmp[1]), 117 #endif 118 #if CFG_TEE_CORE_NB_CORE > 2 119 GET_STACK(stack_tmp[2]), 120 #endif 121 #if CFG_TEE_CORE_NB_CORE > 3 122 GET_STACK(stack_tmp[3]), 123 #endif 124 #if CFG_TEE_CORE_NB_CORE > 4 125 GET_STACK(stack_tmp[4]), 126 #endif 127 #if CFG_TEE_CORE_NB_CORE > 5 128 GET_STACK(stack_tmp[5]), 129 #endif 130 #if CFG_TEE_CORE_NB_CORE > 6 131 GET_STACK(stack_tmp[6]), 132 #endif 133 #if CFG_TEE_CORE_NB_CORE > 7 134 GET_STACK(stack_tmp[7]), 135 #endif 136 #if CFG_TEE_CORE_NB_CORE > 8 137 #error "Top of tmp stacks aren't defined for more than 8 CPUS" 138 #endif 139 }; 140 141 thread_smc_handler_t thread_std_smc_handler_ptr; 142 static thread_smc_handler_t thread_fast_smc_handler_ptr; 143 thread_fiq_handler_t thread_fiq_handler_ptr; 144 thread_pm_handler_t thread_cpu_on_handler_ptr; 145 thread_pm_handler_t thread_cpu_off_handler_ptr; 146 thread_pm_handler_t thread_cpu_suspend_handler_ptr; 147 thread_pm_handler_t thread_cpu_resume_handler_ptr; 148 thread_pm_handler_t thread_system_off_handler_ptr; 149 thread_pm_handler_t thread_system_reset_handler_ptr; 150 151 152 static unsigned int thread_global_lock = SPINLOCK_UNLOCK; 153 154 static void init_canaries(void) 155 { 156 #ifdef CFG_WITH_STACK_CANARIES 157 size_t n; 158 #define INIT_CANARY(name) \ 159 for (n = 0; n < ARRAY_SIZE(name); n++) { \ 160 uint32_t *start_canary = &GET_START_CANARY(name, n); \ 161 uint32_t *end_canary = &GET_END_CANARY(name, n); \ 162 \ 163 *start_canary = START_CANARY_VALUE; \ 164 *end_canary = END_CANARY_VALUE; \ 165 DMSG("#Stack canaries for %s[%zu] with top at %p\n", \ 166 #name, n, (void *)(end_canary - 1)); \ 167 DMSG("watch *%p\n", (void *)end_canary); \ 168 } 169 170 INIT_CANARY(stack_tmp); 171 INIT_CANARY(stack_abt); 172 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 173 INIT_CANARY(stack_sm); 174 #endif 175 #ifndef CFG_WITH_PAGER 176 INIT_CANARY(stack_thread); 177 #endif 178 #endif/*CFG_WITH_STACK_CANARIES*/ 179 } 180 181 void thread_check_canaries(void) 182 { 183 #ifdef CFG_WITH_STACK_CANARIES 184 size_t n; 185 186 for (n = 0; n < ARRAY_SIZE(stack_tmp); n++) { 187 assert(GET_START_CANARY(stack_tmp, n) == START_CANARY_VALUE); 188 assert(GET_END_CANARY(stack_tmp, n) == END_CANARY_VALUE); 189 } 190 191 for (n = 0; n < ARRAY_SIZE(stack_abt); n++) { 192 assert(GET_START_CANARY(stack_abt, n) == START_CANARY_VALUE); 193 assert(GET_END_CANARY(stack_abt, n) == END_CANARY_VALUE); 194 } 195 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 196 for (n = 0; n < ARRAY_SIZE(stack_sm); n++) { 197 assert(GET_START_CANARY(stack_sm, n) == START_CANARY_VALUE); 198 assert(GET_END_CANARY(stack_sm, n) == END_CANARY_VALUE); 199 } 200 #endif 201 #ifndef CFG_WITH_PAGER 202 for (n = 0; n < ARRAY_SIZE(stack_thread); n++) { 203 assert(GET_START_CANARY(stack_thread, n) == START_CANARY_VALUE); 204 assert(GET_END_CANARY(stack_thread, n) == END_CANARY_VALUE); 205 } 206 #endif 207 #endif/*CFG_WITH_STACK_CANARIES*/ 208 } 209 210 static void lock_global(void) 211 { 212 cpu_spin_lock(&thread_global_lock); 213 } 214 215 static void unlock_global(void) 216 { 217 cpu_spin_unlock(&thread_global_lock); 218 } 219 220 #ifdef ARM32 221 uint32_t thread_get_exceptions(void) 222 { 223 uint32_t cpsr = read_cpsr(); 224 225 return (cpsr >> CPSR_F_SHIFT) & THREAD_EXCP_ALL; 226 } 227 228 void thread_set_exceptions(uint32_t exceptions) 229 { 230 uint32_t cpsr = read_cpsr(); 231 232 cpsr &= ~(THREAD_EXCP_ALL << CPSR_F_SHIFT); 233 cpsr |= ((exceptions & THREAD_EXCP_ALL) << CPSR_F_SHIFT); 234 write_cpsr(cpsr); 235 } 236 #endif /*ARM32*/ 237 238 #ifdef ARM64 239 uint32_t thread_get_exceptions(void) 240 { 241 uint32_t daif = read_daif(); 242 243 return (daif >> DAIF_F_SHIFT) & THREAD_EXCP_ALL; 244 } 245 246 void thread_set_exceptions(uint32_t exceptions) 247 { 248 uint32_t daif = read_daif(); 249 250 daif &= ~(THREAD_EXCP_ALL << DAIF_F_SHIFT); 251 daif |= ((exceptions & THREAD_EXCP_ALL) << DAIF_F_SHIFT); 252 write_daif(daif); 253 } 254 #endif /*ARM64*/ 255 256 uint32_t thread_mask_exceptions(uint32_t exceptions) 257 { 258 uint32_t state = thread_get_exceptions(); 259 260 thread_set_exceptions(state | (exceptions & THREAD_EXCP_ALL)); 261 return state; 262 } 263 264 void thread_unmask_exceptions(uint32_t state) 265 { 266 thread_set_exceptions(state & THREAD_EXCP_ALL); 267 } 268 269 270 struct thread_core_local *thread_get_core_local(void) 271 { 272 uint32_t cpu_id = get_core_pos(); 273 274 /* 275 * IRQs must be disabled before playing with core_local since 276 * we otherwise may be rescheduled to a different core in the 277 * middle of this function. 278 */ 279 assert(thread_get_exceptions() & THREAD_EXCP_IRQ); 280 281 assert(cpu_id < CFG_TEE_CORE_NB_CORE); 282 return &thread_core_local[cpu_id]; 283 } 284 285 static void thread_lazy_save_ns_vfp(void) 286 { 287 #ifdef CFG_WITH_VFP 288 struct thread_ctx *thr = threads + thread_get_id(); 289 290 thr->vfp_state.ns_saved = false; 291 #if defined(ARM64) && defined(CFG_WITH_ARM_TRUSTED_FW) 292 /* 293 * ARM TF saves and restores CPACR_EL1, so we must assume NS world 294 * uses VFP and always preserve the register file when secure world 295 * is about to use it 296 */ 297 thr->vfp_state.ns.force_save = true; 298 #endif 299 vfp_lazy_save_state_init(&thr->vfp_state.ns); 300 #endif /*CFG_WITH_VFP*/ 301 } 302 303 static void thread_lazy_restore_ns_vfp(void) 304 { 305 #ifdef CFG_WITH_VFP 306 struct thread_ctx *thr = threads + thread_get_id(); 307 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 308 309 assert(!thr->vfp_state.sec_lazy_saved && !thr->vfp_state.sec_saved); 310 311 if (tuv && tuv->lazy_saved && !tuv->saved) { 312 vfp_lazy_save_state_final(&tuv->vfp); 313 tuv->saved = true; 314 } 315 316 vfp_lazy_restore_state(&thr->vfp_state.ns, thr->vfp_state.ns_saved); 317 thr->vfp_state.ns_saved = false; 318 #endif /*CFG_WITH_VFP*/ 319 } 320 321 #ifdef ARM32 322 static void init_regs(struct thread_ctx *thread, 323 struct thread_smc_args *args) 324 { 325 thread->regs.pc = (uint32_t)thread_std_smc_entry; 326 327 /* 328 * Stdcalls starts in SVC mode with masked IRQ, masked Asynchronous 329 * abort and unmasked FIQ. 330 */ 331 thread->regs.cpsr = read_cpsr() & ARM32_CPSR_E; 332 thread->regs.cpsr |= CPSR_MODE_SVC | CPSR_I | CPSR_A; 333 /* Enable thumb mode if it's a thumb instruction */ 334 if (thread->regs.pc & 1) 335 thread->regs.cpsr |= CPSR_T; 336 /* Reinitialize stack pointer */ 337 thread->regs.svc_sp = thread->stack_va_end; 338 339 /* 340 * Copy arguments into context. This will make the 341 * arguments appear in r0-r7 when thread is started. 342 */ 343 thread->regs.r0 = args->a0; 344 thread->regs.r1 = args->a1; 345 thread->regs.r2 = args->a2; 346 thread->regs.r3 = args->a3; 347 thread->regs.r4 = args->a4; 348 thread->regs.r5 = args->a5; 349 thread->regs.r6 = args->a6; 350 thread->regs.r7 = args->a7; 351 } 352 #endif /*ARM32*/ 353 354 #ifdef ARM64 355 static void init_regs(struct thread_ctx *thread, 356 struct thread_smc_args *args) 357 { 358 thread->regs.pc = (uint64_t)thread_std_smc_entry; 359 360 /* 361 * Stdcalls starts in SVC mode with masked IRQ, masked Asynchronous 362 * abort and unmasked FIQ. 363 */ 364 thread->regs.cpsr = SPSR_64(SPSR_64_MODE_EL1, SPSR_64_MODE_SP_EL0, 365 DAIFBIT_IRQ | DAIFBIT_ABT); 366 /* Reinitialize stack pointer */ 367 thread->regs.sp = thread->stack_va_end; 368 369 /* 370 * Copy arguments into context. This will make the 371 * arguments appear in x0-x7 when thread is started. 372 */ 373 thread->regs.x[0] = args->a0; 374 thread->regs.x[1] = args->a1; 375 thread->regs.x[2] = args->a2; 376 thread->regs.x[3] = args->a3; 377 thread->regs.x[4] = args->a4; 378 thread->regs.x[5] = args->a5; 379 thread->regs.x[6] = args->a6; 380 thread->regs.x[7] = args->a7; 381 } 382 #endif /*ARM64*/ 383 384 void thread_init_boot_thread(void) 385 { 386 struct thread_core_local *l = thread_get_core_local(); 387 size_t n; 388 389 for (n = 0; n < CFG_NUM_THREADS; n++) 390 TAILQ_INIT(&threads[n].mutexes); 391 392 for (n = 0; n < CFG_TEE_CORE_NB_CORE; n++) 393 thread_core_local[n].curr_thread = -1; 394 395 l->curr_thread = 0; 396 threads[0].state = THREAD_STATE_ACTIVE; 397 } 398 399 void thread_clr_boot_thread(void) 400 { 401 struct thread_core_local *l = thread_get_core_local(); 402 403 assert(l->curr_thread >= 0 && l->curr_thread < CFG_NUM_THREADS); 404 assert(threads[l->curr_thread].state == THREAD_STATE_ACTIVE); 405 assert(TAILQ_EMPTY(&threads[l->curr_thread].mutexes)); 406 threads[l->curr_thread].state = THREAD_STATE_FREE; 407 l->curr_thread = -1; 408 } 409 410 static void thread_alloc_and_run(struct thread_smc_args *args) 411 { 412 size_t n; 413 struct thread_core_local *l = thread_get_core_local(); 414 bool found_thread = false; 415 416 assert(l->curr_thread == -1); 417 418 lock_global(); 419 420 for (n = 0; n < CFG_NUM_THREADS; n++) { 421 if (threads[n].state == THREAD_STATE_FREE) { 422 threads[n].state = THREAD_STATE_ACTIVE; 423 found_thread = true; 424 break; 425 } 426 } 427 428 unlock_global(); 429 430 if (!found_thread) { 431 args->a0 = TEESMC_RETURN_ETHREAD_LIMIT; 432 return; 433 } 434 435 l->curr_thread = n; 436 437 threads[n].flags = 0; 438 init_regs(threads + n, args); 439 440 /* Save Hypervisor Client ID */ 441 threads[n].hyp_clnt_id = args->a7; 442 443 thread_lazy_save_ns_vfp(); 444 thread_resume(&threads[n].regs); 445 } 446 447 #ifdef ARM32 448 static void copy_a0_to_a3(struct thread_ctx_regs *regs, 449 struct thread_smc_args *args) 450 { 451 /* 452 * Update returned values from RPC, values will appear in 453 * r0-r3 when thread is resumed. 454 */ 455 regs->r0 = args->a0; 456 regs->r1 = args->a1; 457 regs->r2 = args->a2; 458 regs->r3 = args->a3; 459 } 460 #endif /*ARM32*/ 461 462 #ifdef ARM64 463 static void copy_a0_to_a3(struct thread_ctx_regs *regs, 464 struct thread_smc_args *args) 465 { 466 /* 467 * Update returned values from RPC, values will appear in 468 * x0-x3 when thread is resumed. 469 */ 470 regs->x[0] = args->a0; 471 regs->x[1] = args->a1; 472 regs->x[2] = args->a2; 473 regs->x[3] = args->a3; 474 } 475 #endif /*ARM64*/ 476 477 static void thread_resume_from_rpc(struct thread_smc_args *args) 478 { 479 size_t n = args->a3; /* thread id */ 480 struct thread_core_local *l = thread_get_core_local(); 481 uint32_t rv = 0; 482 483 assert(l->curr_thread == -1); 484 485 lock_global(); 486 487 if (n < CFG_NUM_THREADS && 488 threads[n].state == THREAD_STATE_SUSPENDED && 489 args->a7 == threads[n].hyp_clnt_id) 490 threads[n].state = THREAD_STATE_ACTIVE; 491 else 492 rv = TEESMC_RETURN_ERESUME; 493 494 unlock_global(); 495 496 if (rv) { 497 args->a0 = rv; 498 return; 499 } 500 501 l->curr_thread = n; 502 503 if (threads[n].have_user_map) 504 core_mmu_set_user_map(&threads[n].user_map); 505 506 /* 507 * Return from RPC to request service of an IRQ must not 508 * get parameters from non-secure world. 509 */ 510 if (threads[n].flags & THREAD_FLAGS_COPY_ARGS_ON_RETURN) { 511 copy_a0_to_a3(&threads[n].regs, args); 512 threads[n].flags &= ~THREAD_FLAGS_COPY_ARGS_ON_RETURN; 513 } 514 515 thread_lazy_save_ns_vfp(); 516 thread_resume(&threads[n].regs); 517 } 518 519 void thread_handle_fast_smc(struct thread_smc_args *args) 520 { 521 thread_check_canaries(); 522 thread_fast_smc_handler_ptr(args); 523 /* Fast handlers must not unmask any exceptions */ 524 assert(thread_get_exceptions() == THREAD_EXCP_ALL); 525 } 526 527 void thread_handle_std_smc(struct thread_smc_args *args) 528 { 529 thread_check_canaries(); 530 531 if (args->a0 == TEESMC32_CALL_RETURN_FROM_RPC) 532 thread_resume_from_rpc(args); 533 else 534 thread_alloc_and_run(args); 535 } 536 537 /* Helper routine for the assembly function thread_std_smc_entry() */ 538 void __thread_std_smc_entry(struct thread_smc_args *args) 539 { 540 struct thread_ctx *thr = threads + thread_get_id(); 541 542 if (!thr->rpc_arg) { 543 paddr_t parg; 544 void *arg; 545 546 parg = thread_rpc_alloc_arg( 547 TEESMC32_GET_ARG_SIZE(RPC_MAX_PARAMS)); 548 if (!parg || !ALIGNMENT_IS_OK(parg, struct teesmc32_arg) || 549 core_pa2va(parg, &arg)) { 550 thread_rpc_free_arg(parg); 551 args->a0 = TEESMC_RETURN_ENOMEM; 552 return; 553 } 554 555 thr->rpc_arg = arg; 556 thr->rpc_parg = parg; 557 } 558 559 thread_std_smc_handler_ptr(args); 560 } 561 562 void *thread_get_tmp_sp(void) 563 { 564 struct thread_core_local *l = thread_get_core_local(); 565 566 return (void *)l->tmp_stack_va_end; 567 } 568 569 #ifdef ARM64 570 vaddr_t thread_get_saved_thread_sp(void) 571 { 572 struct thread_core_local *l = thread_get_core_local(); 573 int ct = l->curr_thread; 574 575 assert(ct != -1); 576 return threads[ct].kern_sp; 577 } 578 #endif /*ARM64*/ 579 580 bool thread_addr_is_in_stack(vaddr_t va) 581 { 582 struct thread_ctx *thr = threads + thread_get_id(); 583 584 return va < thr->stack_va_end && 585 va >= (thr->stack_va_end - STACK_THREAD_SIZE); 586 } 587 588 void thread_state_free(void) 589 { 590 struct thread_core_local *l = thread_get_core_local(); 591 int ct = l->curr_thread; 592 593 assert(ct != -1); 594 assert(TAILQ_EMPTY(&threads[ct].mutexes)); 595 596 thread_lazy_restore_ns_vfp(); 597 598 lock_global(); 599 600 assert(threads[ct].state == THREAD_STATE_ACTIVE); 601 threads[ct].state = THREAD_STATE_FREE; 602 threads[ct].flags = 0; 603 l->curr_thread = -1; 604 605 unlock_global(); 606 } 607 608 #ifdef ARM32 609 static bool is_from_user(uint32_t cpsr) 610 { 611 return (cpsr & ARM32_CPSR_MODE_MASK) == ARM32_CPSR_MODE_USR; 612 } 613 #endif 614 615 #ifdef ARM64 616 static bool is_from_user(uint32_t cpsr) 617 { 618 if (cpsr & (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT)) 619 return true; 620 if (((cpsr >> SPSR_64_MODE_EL_SHIFT) & SPSR_64_MODE_EL_MASK) == 621 SPSR_64_MODE_EL0) 622 return true; 623 return false; 624 } 625 #endif 626 627 int thread_state_suspend(uint32_t flags, uint32_t cpsr, vaddr_t pc) 628 { 629 struct thread_core_local *l = thread_get_core_local(); 630 int ct = l->curr_thread; 631 632 assert(ct != -1); 633 634 thread_check_canaries(); 635 636 if (is_from_user(cpsr)) 637 thread_user_save_vfp(); 638 thread_lazy_restore_ns_vfp(); 639 640 lock_global(); 641 642 assert(threads[ct].state == THREAD_STATE_ACTIVE); 643 threads[ct].flags |= flags; 644 threads[ct].regs.cpsr = cpsr; 645 threads[ct].regs.pc = pc; 646 threads[ct].state = THREAD_STATE_SUSPENDED; 647 648 threads[ct].have_user_map = core_mmu_user_mapping_is_active(); 649 if (threads[ct].have_user_map) { 650 core_mmu_get_user_map(&threads[ct].user_map); 651 core_mmu_set_user_map(NULL); 652 } 653 654 655 l->curr_thread = -1; 656 657 unlock_global(); 658 659 return ct; 660 } 661 662 #ifdef ARM32 663 static void set_tmp_stack(struct thread_core_local *l, vaddr_t sp) 664 { 665 l->tmp_stack_va_end = sp; 666 thread_set_irq_sp(sp); 667 thread_set_fiq_sp(sp); 668 } 669 670 static void set_abt_stack(struct thread_core_local *l __unused, vaddr_t sp) 671 { 672 thread_set_abt_sp(sp); 673 } 674 #endif /*ARM32*/ 675 676 #ifdef ARM64 677 static void set_tmp_stack(struct thread_core_local *l, vaddr_t sp) 678 { 679 /* 680 * We're already using the tmp stack when this function is called 681 * so there's no need to assign it to any stack pointer. However, 682 * we'll need to restore it at different times so store it here. 683 */ 684 l->tmp_stack_va_end = sp; 685 } 686 687 static void set_abt_stack(struct thread_core_local *l, vaddr_t sp) 688 { 689 l->abt_stack_va_end = sp; 690 } 691 #endif /*ARM64*/ 692 693 bool thread_init_stack(uint32_t thread_id, vaddr_t sp) 694 { 695 if (thread_id >= CFG_NUM_THREADS) 696 return false; 697 threads[thread_id].stack_va_end = sp; 698 return true; 699 } 700 701 int thread_get_id(void) 702 { 703 /* thread_get_core_local() requires IRQs to be disabled */ 704 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 705 struct thread_core_local *l; 706 int ct; 707 708 l = thread_get_core_local(); 709 ct = l->curr_thread; 710 assert((ct >= 0) && (ct < CFG_NUM_THREADS)); 711 712 thread_unmask_exceptions(exceptions); 713 return ct; 714 } 715 716 static void init_handlers(const struct thread_handlers *handlers) 717 { 718 thread_std_smc_handler_ptr = handlers->std_smc; 719 thread_fast_smc_handler_ptr = handlers->fast_smc; 720 thread_fiq_handler_ptr = handlers->fiq; 721 thread_cpu_on_handler_ptr = handlers->cpu_on; 722 thread_cpu_off_handler_ptr = handlers->cpu_off; 723 thread_cpu_suspend_handler_ptr = handlers->cpu_suspend; 724 thread_cpu_resume_handler_ptr = handlers->cpu_resume; 725 thread_system_off_handler_ptr = handlers->system_off; 726 thread_system_reset_handler_ptr = handlers->system_reset; 727 } 728 729 730 #ifdef CFG_WITH_PAGER 731 static void init_thread_stacks(void) 732 { 733 size_t n; 734 735 /* 736 * Allocate virtual memory for thread stacks. 737 */ 738 for (n = 0; n < CFG_NUM_THREADS; n++) { 739 tee_mm_entry_t *mm; 740 vaddr_t sp; 741 742 /* Find vmem for thread stack and its protection gap */ 743 mm = tee_mm_alloc(&tee_mm_vcore, 744 SMALL_PAGE_SIZE + STACK_THREAD_SIZE); 745 TEE_ASSERT(mm); 746 747 /* Claim eventual physical page */ 748 tee_pager_add_pages(tee_mm_get_smem(mm), tee_mm_get_size(mm), 749 true); 750 751 /* Realloc both protection vmem and stack vmem separately */ 752 sp = tee_mm_get_smem(mm); 753 tee_mm_free(mm); 754 mm = tee_mm_alloc2(&tee_mm_vcore, sp, SMALL_PAGE_SIZE); 755 TEE_ASSERT(mm); 756 mm = tee_mm_alloc2(&tee_mm_vcore, sp + SMALL_PAGE_SIZE, 757 STACK_THREAD_SIZE); 758 TEE_ASSERT(mm); 759 760 /* init effective stack */ 761 sp = tee_mm_get_smem(mm) + tee_mm_get_bytes(mm); 762 if (!thread_init_stack(n, sp)) 763 panic(); 764 765 /* Add the area to the pager */ 766 tee_pager_add_area(mm, TEE_PAGER_AREA_RW, NULL, NULL); 767 } 768 } 769 #else 770 static void init_thread_stacks(void) 771 { 772 size_t n; 773 774 /* Assign the thread stacks */ 775 for (n = 0; n < CFG_NUM_THREADS; n++) { 776 if (!thread_init_stack(n, GET_STACK(stack_thread[n]))) 777 panic(); 778 } 779 } 780 #endif /*CFG_WITH_PAGER*/ 781 782 void thread_init_primary(const struct thread_handlers *handlers) 783 { 784 /* 785 * The COMPILE_TIME_ASSERT only works in function context. These 786 * checks verifies that the offsets used in assembly code matches 787 * what's used in C code. 788 */ 789 #ifdef ARM32 790 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r0) == 791 THREAD_SVC_REG_R0_OFFS); 792 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r1) == 793 THREAD_SVC_REG_R1_OFFS); 794 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r2) == 795 THREAD_SVC_REG_R2_OFFS); 796 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r3) == 797 THREAD_SVC_REG_R3_OFFS); 798 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r4) == 799 THREAD_SVC_REG_R4_OFFS); 800 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r5) == 801 THREAD_SVC_REG_R5_OFFS); 802 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r6) == 803 THREAD_SVC_REG_R6_OFFS); 804 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r7) == 805 THREAD_SVC_REG_R7_OFFS); 806 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, lr) == 807 THREAD_SVC_REG_LR_OFFS); 808 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, spsr) == 809 THREAD_SVC_REG_SPSR_OFFS); 810 #endif /*ARM32*/ 811 #ifdef ARM64 812 /* struct thread_abort_regs */ 813 COMPILE_TIME_ASSERT(offsetof(struct thread_abort_regs, x22) == 814 THREAD_ABT_REG_X_OFFS(22)); 815 COMPILE_TIME_ASSERT(offsetof(struct thread_abort_regs, elr) == 816 THREAD_ABT_REG_ELR_OFFS); 817 COMPILE_TIME_ASSERT(offsetof(struct thread_abort_regs, spsr) == 818 THREAD_ABT_REG_SPSR_OFFS); 819 COMPILE_TIME_ASSERT(offsetof(struct thread_abort_regs, sp_el0) == 820 THREAD_ABT_REG_SP_EL0_OFFS); 821 COMPILE_TIME_ASSERT(sizeof(struct thread_abort_regs) == 822 THREAD_ABT_REGS_SIZE); 823 824 /* struct thread_ctx */ 825 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx, kern_sp) == 826 THREAD_CTX_KERN_SP_OFFSET); 827 COMPILE_TIME_ASSERT(sizeof(struct thread_ctx) == THREAD_CTX_SIZE); 828 829 /* struct thread_ctx_regs */ 830 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx_regs, sp) == 831 THREAD_CTX_REGS_SP_OFFSET); 832 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx_regs, pc) == 833 THREAD_CTX_REGS_PC_OFFSET); 834 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx_regs, cpsr) == 835 THREAD_CTX_REGS_SPSR_OFFSET); 836 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx_regs, x[23]) == 837 THREAD_CTX_REGS_X_OFFSET(23)); 838 COMPILE_TIME_ASSERT(sizeof(struct thread_ctx_regs) == 839 THREAD_CTX_REGS_SIZE); 840 841 /* struct thread_user_mode_rec */ 842 COMPILE_TIME_ASSERT( 843 offsetof(struct thread_user_mode_rec, exit_status0_ptr) == 844 THREAD_USER_MODE_REC_EXIT_STATUS0_PTR_OFFSET); 845 COMPILE_TIME_ASSERT( 846 offsetof(struct thread_user_mode_rec, exit_status1_ptr) == 847 THREAD_USER_MODE_REC_EXIT_STATUS1_PTR_OFFSET); 848 COMPILE_TIME_ASSERT( 849 offsetof(struct thread_user_mode_rec, x[1]) == 850 THREAD_USER_MODE_REC_X_OFFSET(20)); 851 COMPILE_TIME_ASSERT(sizeof(struct thread_user_mode_rec) == 852 THREAD_USER_MODE_REC_SIZE); 853 854 /* struct thread_core_local */ 855 COMPILE_TIME_ASSERT( 856 offsetof(struct thread_core_local, tmp_stack_va_end) == 857 THREAD_CORE_LOCAL_TMP_STACK_VA_END_OFFSET); 858 COMPILE_TIME_ASSERT( 859 offsetof(struct thread_core_local, curr_thread) == 860 THREAD_CORE_LOCAL_CURR_THREAD_OFFSET); 861 COMPILE_TIME_ASSERT( 862 offsetof(struct thread_core_local, flags) == 863 THREAD_CORE_LOCAL_FLAGS_OFFSET); 864 COMPILE_TIME_ASSERT( 865 offsetof(struct thread_core_local, abt_stack_va_end) == 866 THREAD_CORE_LOCAL_ABT_STACK_VA_END_OFFSET); 867 COMPILE_TIME_ASSERT( 868 offsetof(struct thread_core_local, x[3]) == 869 THREAD_CORE_LOCAL_X_OFFSET(3)); 870 COMPILE_TIME_ASSERT(sizeof(struct thread_core_local) == 871 THREAD_CORE_LOCAL_SIZE); 872 873 #endif /*ARM64*/ 874 875 init_handlers(handlers); 876 877 /* Initialize canaries around the stacks */ 878 init_canaries(); 879 880 init_thread_stacks(); 881 } 882 883 static void init_sec_mon(size_t pos __maybe_unused) 884 { 885 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 886 /* Initialize secure monitor */ 887 sm_init(GET_STACK(stack_sm[pos])); 888 sm_set_entry_vector(thread_vector_table); 889 #endif 890 } 891 892 void thread_init_per_cpu(void) 893 { 894 size_t pos = get_core_pos(); 895 struct thread_core_local *l = thread_get_core_local(); 896 897 init_sec_mon(pos); 898 899 set_tmp_stack(l, GET_STACK(stack_tmp[pos])); 900 set_abt_stack(l, GET_STACK(stack_abt[pos])); 901 902 thread_init_vbar(); 903 } 904 905 void thread_set_tsd(void *tsd) 906 { 907 /* thread_get_core_local() requires IRQs to be disabled */ 908 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 909 struct thread_core_local *l; 910 int ct; 911 912 l = thread_get_core_local(); 913 ct = l->curr_thread; 914 915 assert(ct != -1); 916 assert(threads[ct].state == THREAD_STATE_ACTIVE); 917 threads[ct].tsd = tsd; 918 919 thread_unmask_exceptions(exceptions); 920 } 921 922 void *thread_get_tsd(void) 923 { 924 /* thread_get_core_local() requires IRQs to be disabled */ 925 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 926 struct thread_core_local *l; 927 int ct; 928 void *tsd; 929 930 l = thread_get_core_local(); 931 ct = l->curr_thread; 932 933 if (ct == -1 || threads[ct].state != THREAD_STATE_ACTIVE) 934 tsd = NULL; 935 else 936 tsd = threads[ct].tsd; 937 938 thread_unmask_exceptions(exceptions); 939 return tsd; 940 } 941 942 struct thread_ctx_regs *thread_get_ctx_regs(void) 943 { 944 struct thread_core_local *l = thread_get_core_local(); 945 946 assert(l->curr_thread != -1); 947 return &threads[l->curr_thread].regs; 948 } 949 950 void thread_set_irq(bool enable) 951 { 952 /* thread_get_core_local() requires IRQs to be disabled */ 953 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 954 struct thread_core_local *l; 955 956 l = thread_get_core_local(); 957 958 assert(l->curr_thread != -1); 959 960 if (enable) { 961 threads[l->curr_thread].flags |= THREAD_FLAGS_IRQ_ENABLE; 962 thread_set_exceptions(exceptions & ~THREAD_EXCP_IRQ); 963 } else { 964 /* 965 * No need to disable IRQ here since it's already disabled 966 * above. 967 */ 968 threads[l->curr_thread].flags &= ~THREAD_FLAGS_IRQ_ENABLE; 969 } 970 } 971 972 void thread_restore_irq(void) 973 { 974 /* thread_get_core_local() requires IRQs to be disabled */ 975 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 976 struct thread_core_local *l; 977 978 l = thread_get_core_local(); 979 980 assert(l->curr_thread != -1); 981 982 if (threads[l->curr_thread].flags & THREAD_FLAGS_IRQ_ENABLE) 983 thread_set_exceptions(exceptions & ~THREAD_EXCP_IRQ); 984 } 985 986 #ifdef CFG_WITH_VFP 987 uint32_t thread_kernel_enable_vfp(void) 988 { 989 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 990 struct thread_ctx *thr = threads + thread_get_id(); 991 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 992 993 assert(!vfp_is_enabled()); 994 995 if (!thr->vfp_state.ns_saved) { 996 vfp_lazy_save_state_final(&thr->vfp_state.ns); 997 thr->vfp_state.ns_saved = true; 998 } else if (thr->vfp_state.sec_lazy_saved && 999 !thr->vfp_state.sec_saved) { 1000 /* 1001 * This happens when we're handling an abort while the 1002 * thread was using the VFP state. 1003 */ 1004 vfp_lazy_save_state_final(&thr->vfp_state.sec); 1005 thr->vfp_state.sec_saved = true; 1006 } else if (tuv && tuv->lazy_saved && !tuv->saved) { 1007 /* 1008 * This can happen either during syscall or abort 1009 * processing (while processing a syscall). 1010 */ 1011 vfp_lazy_save_state_final(&tuv->vfp); 1012 tuv->saved = true; 1013 } 1014 1015 vfp_enable(); 1016 return exceptions; 1017 } 1018 1019 void thread_kernel_disable_vfp(uint32_t state) 1020 { 1021 uint32_t exceptions; 1022 1023 assert(vfp_is_enabled()); 1024 1025 vfp_disable(); 1026 exceptions = thread_get_exceptions(); 1027 assert(exceptions & THREAD_EXCP_IRQ); 1028 exceptions &= ~THREAD_EXCP_IRQ; 1029 exceptions |= state & THREAD_EXCP_IRQ; 1030 thread_set_exceptions(exceptions); 1031 } 1032 1033 void thread_kernel_save_vfp(void) 1034 { 1035 struct thread_ctx *thr = threads + thread_get_id(); 1036 1037 assert(thread_get_exceptions() & THREAD_EXCP_IRQ); 1038 if (vfp_is_enabled()) { 1039 vfp_lazy_save_state_init(&thr->vfp_state.sec); 1040 thr->vfp_state.sec_lazy_saved = true; 1041 } 1042 } 1043 1044 void thread_kernel_restore_vfp(void) 1045 { 1046 struct thread_ctx *thr = threads + thread_get_id(); 1047 1048 assert(thread_get_exceptions() & THREAD_EXCP_IRQ); 1049 assert(!vfp_is_enabled()); 1050 if (thr->vfp_state.sec_lazy_saved) { 1051 vfp_lazy_restore_state(&thr->vfp_state.sec, 1052 thr->vfp_state.sec_saved); 1053 thr->vfp_state.sec_saved = false; 1054 thr->vfp_state.sec_lazy_saved = false; 1055 } 1056 } 1057 1058 void thread_user_enable_vfp(struct thread_user_vfp_state *uvfp) 1059 { 1060 struct thread_ctx *thr = threads + thread_get_id(); 1061 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 1062 1063 assert(thread_get_exceptions() & THREAD_EXCP_IRQ); 1064 assert(!vfp_is_enabled()); 1065 1066 if (!thr->vfp_state.ns_saved) { 1067 vfp_lazy_save_state_final(&thr->vfp_state.ns); 1068 thr->vfp_state.ns_saved = true; 1069 } else if (tuv && uvfp != tuv) { 1070 if (tuv->lazy_saved && !tuv->saved) { 1071 vfp_lazy_save_state_final(&tuv->vfp); 1072 tuv->saved = true; 1073 } 1074 } 1075 1076 if (uvfp->lazy_saved) 1077 vfp_lazy_restore_state(&uvfp->vfp, uvfp->saved); 1078 uvfp->lazy_saved = false; 1079 uvfp->saved = false; 1080 1081 thr->vfp_state.uvfp = uvfp; 1082 vfp_enable(); 1083 } 1084 1085 void thread_user_save_vfp(void) 1086 { 1087 struct thread_ctx *thr = threads + thread_get_id(); 1088 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 1089 1090 assert(thread_get_exceptions() & THREAD_EXCP_IRQ); 1091 if (!vfp_is_enabled()) 1092 return; 1093 1094 assert(tuv && !tuv->lazy_saved && !tuv->saved); 1095 vfp_lazy_save_state_init(&tuv->vfp); 1096 tuv->lazy_saved = true; 1097 } 1098 1099 void thread_user_clear_vfp(struct thread_user_vfp_state *uvfp) 1100 { 1101 struct thread_ctx *thr = threads + thread_get_id(); 1102 1103 if (uvfp == thr->vfp_state.uvfp) 1104 thr->vfp_state.uvfp = NULL; 1105 uvfp->lazy_saved = false; 1106 uvfp->saved = false; 1107 } 1108 #endif /*CFG_WITH_VFP*/ 1109 1110 #ifdef ARM32 1111 static bool get_spsr(bool is_32bit, unsigned long entry_func, uint32_t *spsr) 1112 { 1113 uint32_t s; 1114 1115 if (!is_32bit) 1116 return false; 1117 1118 s = read_spsr(); 1119 s &= ~(CPSR_MODE_MASK | CPSR_T | CPSR_IT_MASK1 | CPSR_IT_MASK2); 1120 s |= CPSR_MODE_USR; 1121 if (entry_func & 1) 1122 s |= CPSR_T; 1123 *spsr = s; 1124 return true; 1125 } 1126 #endif 1127 1128 #ifdef ARM64 1129 static bool get_spsr(bool is_32bit, unsigned long entry_func, uint32_t *spsr) 1130 { 1131 uint32_t s; 1132 1133 if (is_32bit) { 1134 s = read_daif() & (SPSR_32_AIF_MASK << SPSR_32_AIF_SHIFT); 1135 s |= SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT; 1136 s |= (entry_func & SPSR_32_T_MASK) << SPSR_32_T_SHIFT; 1137 } else { 1138 s = read_daif() & (SPSR_64_DAIF_MASK << SPSR_64_DAIF_SHIFT); 1139 } 1140 1141 *spsr = s; 1142 return true; 1143 } 1144 #endif 1145 1146 uint32_t thread_enter_user_mode(unsigned long a0, unsigned long a1, 1147 unsigned long a2, unsigned long a3, unsigned long user_sp, 1148 unsigned long entry_func, bool is_32bit, 1149 uint32_t *exit_status0, uint32_t *exit_status1) 1150 { 1151 uint32_t spsr; 1152 1153 if (!get_spsr(is_32bit, entry_func, &spsr)) { 1154 *exit_status0 = 1; /* panic */ 1155 *exit_status1 = 0xbadbadba; 1156 return 0; 1157 } 1158 return __thread_enter_user_mode(a0, a1, a2, a3, user_sp, entry_func, 1159 spsr, exit_status0, exit_status1); 1160 } 1161 1162 void thread_add_mutex(struct mutex *m) 1163 { 1164 struct thread_core_local *l = thread_get_core_local(); 1165 int ct = l->curr_thread; 1166 1167 assert(ct != -1 && threads[ct].state == THREAD_STATE_ACTIVE); 1168 assert(m->owner_id == -1); 1169 m->owner_id = ct; 1170 TAILQ_INSERT_TAIL(&threads[ct].mutexes, m, link); 1171 } 1172 1173 void thread_rem_mutex(struct mutex *m) 1174 { 1175 struct thread_core_local *l = thread_get_core_local(); 1176 int ct = l->curr_thread; 1177 1178 assert(ct != -1 && threads[ct].state == THREAD_STATE_ACTIVE); 1179 assert(m->owner_id == ct); 1180 m->owner_id = -1; 1181 TAILQ_REMOVE(&threads[ct].mutexes, m, link); 1182 } 1183 1184 paddr_t thread_rpc_alloc_arg(size_t size) 1185 { 1186 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1187 TEESMC_RETURN_RPC_ALLOC_ARG, size}; 1188 1189 thread_rpc(rpc_args); 1190 return rpc_args[1]; 1191 } 1192 1193 paddr_t thread_rpc_alloc_payload(size_t size) 1194 { 1195 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1196 TEESMC_RETURN_RPC_ALLOC_PAYLOAD, size}; 1197 1198 thread_rpc(rpc_args); 1199 return rpc_args[1]; 1200 } 1201 1202 void thread_rpc_free_arg(paddr_t arg) 1203 { 1204 if (arg) { 1205 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1206 TEESMC_RETURN_RPC_FREE_ARG, arg}; 1207 1208 thread_rpc(rpc_args); 1209 } 1210 } 1211 void thread_rpc_free_payload(paddr_t payload) 1212 { 1213 if (payload) { 1214 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1215 TEESMC_RETURN_RPC_FREE_PAYLOAD, payload}; 1216 1217 thread_rpc(rpc_args); 1218 } 1219 } 1220 1221 static uint32_t rpc_cmd_nolock(uint32_t cmd, size_t num_params, 1222 struct teesmc32_param *params) 1223 { 1224 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 0 }; 1225 struct thread_ctx *thr = threads + thread_get_id(); 1226 struct teesmc32_arg *arg = thr->rpc_arg; 1227 paddr_t parg = thr->rpc_parg; 1228 const size_t params_size = sizeof(struct teesmc32_param) * num_params; 1229 size_t n; 1230 1231 TEE_ASSERT(arg && parg && num_params <= RPC_MAX_PARAMS); 1232 1233 memset(arg, 0, TEESMC32_GET_ARG_SIZE(RPC_MAX_PARAMS)); 1234 arg->cmd = cmd; 1235 arg->ret = TEE_ERROR_GENERIC; /* in case value isn't updated */ 1236 arg->num_params = num_params; 1237 memcpy(TEESMC32_GET_PARAMS(arg), params, params_size); 1238 1239 rpc_args[0] = TEESMC_RETURN_RPC_CMD; 1240 rpc_args[1] = parg; 1241 thread_rpc(rpc_args); 1242 1243 for (n = 0; n < num_params; n++) { 1244 switch (params[n].attr & TEESMC_ATTR_TYPE_MASK) { 1245 case TEESMC_ATTR_TYPE_VALUE_OUTPUT: 1246 case TEESMC_ATTR_TYPE_VALUE_INOUT: 1247 case TEESMC_ATTR_TYPE_MEMREF_OUTPUT: 1248 case TEESMC_ATTR_TYPE_MEMREF_INOUT: 1249 memcpy(params + n, TEESMC32_GET_PARAMS(arg) + n, 1250 sizeof(struct teesmc32_param)); 1251 break; 1252 default: 1253 break; 1254 } 1255 } 1256 1257 return arg->ret; 1258 } 1259 1260 uint32_t thread_rpc_cmd(uint32_t cmd, size_t num_params, 1261 struct teesmc32_param *params) 1262 { 1263 uint32_t ret; 1264 1265 ret = rpc_cmd_nolock(cmd, num_params, params); 1266 1267 return ret; 1268 } 1269 1270 void thread_optee_rpc_alloc_payload(size_t size, paddr_t *payload, 1271 paddr_t *cookie) 1272 { 1273 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1274 TEESMC_RETURN_OPTEE_RPC_ALLOC_PAYLOAD, size}; 1275 1276 thread_rpc(rpc_args); 1277 if (payload) 1278 *payload = rpc_args[1]; 1279 if (cookie) 1280 *cookie = rpc_args[2]; 1281 } 1282 1283 void thread_optee_rpc_free_payload(paddr_t cookie) 1284 { 1285 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] ={ 1286 TEESMC_RETURN_OPTEE_RPC_FREE_PAYLOAD, cookie}; 1287 1288 thread_rpc(rpc_args); 1289 } 1290