1/* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <asm.S> 29#include <arm.h> 30#include <arm32_macros.S> 31#include <kernel/unwind.h> 32 33/* Let platforms override this if needed */ 34.weak get_core_pos 35 36FUNC get_core_pos , : 37UNWIND( .fnstart) 38 read_mpidr r0 39 /* Calculate CorePos = (ClusterId * 4) + CoreId */ 40 and r1, r0, #MPIDR_CPU_MASK 41 and r0, r0, #MPIDR_CLUSTER_MASK 42 add r0, r1, r0, LSR #6 43 bx lr 44UNWIND( .fnend) 45END_FUNC get_core_pos 46 47/* 48 * uint32_t temp_set_mode(int cpu_mode) 49 * returns cpsr to be set 50 */ 51LOCAL_FUNC temp_set_mode , : 52UNWIND( .fnstart) 53 mov r1, r0 54 cmp r1, #CPSR_MODE_USR /* update mode: usr -> sys */ 55 moveq r1, #CPSR_MODE_SYS 56 cpsid aif /* disable interrupts */ 57 mrs r0, cpsr /* get cpsr with disabled its*/ 58 bic r0, #CPSR_MODE_MASK /* clear mode */ 59 orr r0, r1 /* set expected mode */ 60 bx lr 61UNWIND( .fnend) 62END_FUNC temp_set_mode 63 64/* uint32_t read_mode_sp(int cpu_mode) */ 65FUNC read_mode_sp , : 66UNWIND( .fnstart) 67 push {r4, lr} 68UNWIND( .save {r4, lr}) 69 mrs r4, cpsr /* save cpsr */ 70 bl temp_set_mode 71 msr cpsr, r0 /* set the new mode */ 72 mov r0, sp /* get the function result */ 73 msr cpsr, r4 /* back to the old mode */ 74 pop {r4, pc} 75UNWIND( .fnend) 76END_FUNC read_mode_sp 77 78/* uint32_t read_mode_lr(int cpu_mode) */ 79FUNC read_mode_lr , : 80UNWIND( .fnstart) 81 push {r4, lr} 82UNWIND( .save {r4, lr}) 83 mrs r4, cpsr /* save cpsr */ 84 bl temp_set_mode 85 msr cpsr, r0 /* set the new mode */ 86 mov r0, lr /* get the function result */ 87 msr cpsr, r4 /* back to the old mode */ 88 pop {r4, pc} 89UNWIND( .fnend) 90END_FUNC read_mode_lr 91