drivers/tpm2: Add TPM2 MMIO driver

Add support for platforms that interface with TPM2 via
MMIO using FIFO protocol.

Co-developed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Victor Cho

drivers/tpm2: Add TPM2 MMIO driver

Add support for platforms that interface with TPM2 via
MMIO using FIFO protocol.

Co-developed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers/tpm2: Add basic TPM2 support in OP-TEE

TPM2 driver introduced in this commit is based on TPM TCG
specification [1] & [2].

The APIs exposed allows to send commands and receive response
from

drivers/tpm2: Add basic TPM2 support in OP-TEE

TPM2 driver introduced in this commit is based on TPM TCG
specification [1] & [2].

The APIs exposed allows to send commands and receive response
from a TPM2 chip.

[1] TCG PC Client Platform TPM Profile Specification for TPM 2.0
Vesrion 1.0.5 Revision 14
[2] TCG PC Client Device Driver Design Principles for TPM 2.0
Version 1.1 Revision 0.04

Co-developed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: io: add {get/put}_unaligned_be{16/32/64}()

Add 16, 32 and 64 bits put/get functions for big endian
unaligned access

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jens W

core: io: add {get/put}_unaligned_be{16/32/64}()

Add 16, 32 and 64 bits put/get functions for big endian
unaligned access

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: mm: fix core virtual address range constraint in lpae

Changes strategy to set core virtual memory addresses in case pager
is enabled (CFG_WITH_PAGER=y) with LPAE (CFG_WITH_LPAE=y). In this
con

core: mm: fix core virtual address range constraint in lpae

Changes strategy to set core virtual memory addresses in case pager
is enabled (CFG_WITH_PAGER=y) with LPAE (CFG_WITH_LPAE=y). In this
configuration the virtual memory addresses are expected to fit in a
single base translation table in order to save 4kB translation pages.
This change makes core to fallback to the generic layout, possibly
spreading virtual addresses over several base translation tables if
the virtual memory addresses do not fit in the optimized address
range preferred for that configuration.

Fixes: https://github.com/OP-TEE/optee_os/issues/5201
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: dt_driver: drivers to test probe deferral

Implements driver providers for some emulated resource (clocks and reset
controllers), consumer drivers and a embedded test DTSI file to
test the DT_D

core: dt_driver: drivers to test probe deferral

Implements driver providers for some emulated resource (clocks and reset
controllers), consumer drivers and a embedded test DTSI file to
test the DT_DRIVER probe sequence.

The driver consumer run few tests and logs results locally. The
result participates in core self test result reported by the
PTA test interface.

One can test with vexpress platform flavor qemu_virt and qemu_v8 using,
for example, the build instruction below:
make PLATFORM=vexpress-qemu_virt \
CFG_DT_DRIVER_EMBEDDED_TEST=y \
CFG_EMBED_DTB_SOURCE_FILE=embedded_dtb_test.dts

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_iwdg: implementation of independent watchdog

Implements independent watchdog (IWDG) driver to help detecting
malfunctions due to software or hardware failures. IWDG instances
are cloc

drivers: stm32_iwdg: implementation of independent watchdog

Implements independent watchdog (IWDG) driver to help detecting
malfunctions due to software or hardware failures. IWDG instances
are clocked by an independent clock and stays active if the main
clock fails.

The driver mandates IWDG instances configuration from an embedded DTB.

For the list of features, refer to the reference manuals at:
https://wiki.st.com/stm32mpu/wiki/STM32MP15_resources

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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core: sp_mem: add security attribute

Currently sp_mem only supports non-secure memory. This patch enables
using it for secure memory too.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed

core: sp_mem: add security attribute

Currently sp_mem only supports non-secure memory. This patch enables
using it for secure memory too.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jelle Sels <jelle.sels@arm.com>

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core: sp_mem: add memory type attribute

Currently sp_mem only supports TEE_MATTR_MEM_TYPE_CACHE memory type.
This patch adds support for using it with any type so it can be used
for device memory to

core: sp_mem: add memory type attribute

Currently sp_mem only supports TEE_MATTR_MEM_TYPE_CACHE memory type.
This patch adds support for using it with any type so it can be used
for device memory too.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jelle Sels <jelle.sels@arm.com>

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drivers: add stm32 tamper domain driver

Adds stm32_tamp driver for stm32mp1 TAMP sub-system. The implementation
only covers probing of the driver upon embedded DTB content and enabling
some secure c

drivers: add stm32 tamper domain driver

Adds stm32_tamp driver for stm32mp1 TAMP sub-system. The implementation
only covers probing of the driver upon embedded DTB content and enabling
some secure configuration.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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clk: stm32mp13: Introduce STM32MP13 clocks platform

This driver uses a clk-stm32-core API to manage STM32 gates, dividers
and muxes.
The goal of this first patch is to parse the device tree and init

clk: stm32mp13: Introduce STM32MP13 clocks platform

This driver uses a clk-stm32-core API to manage STM32 gates, dividers
and muxes.
The goal of this first patch is to parse the device tree and initialize
a platform data to configure the clock tree.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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dt-bindings: stm32: add stm32mp13 clock and reset bindings

Add new clocks and reset binding files to manage STM32MP13 RCC.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Ga

dt-bindings: stm32: add stm32mp13 clock and reset bindings

Add new clocks and reset binding files to manage STM32MP13 RCC.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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core: dt: add kernel DT API to retrieved device information from DT

Add _fdt_read_uint32_array(), _fdt_read_uint32(),
_fdt_read_uint32_default(), _fdt_check_node() functions.

Acked-by: Etienne Carr

core: dt: add kernel DT API to retrieved device information from DT

Add _fdt_read_uint32_array(), _fdt_read_uint32(),
_fdt_read_uint32_default(), _fdt_check_node() functions.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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core: pager: export __{text,rodata}_{init,pageable}_{start,end}

Add symbols __text_pageable_start, __text_pageable_end,
__rodata_pageable_start and __rodata_pageable_end. They will later be
used by

core: pager: export __{text,rodata}_{init,pageable}_{start,end}

Add symbols __text_pageable_start, __text_pageable_end,
__rodata_pageable_start and __rodata_pageable_end. They will later be
used by the attestation PTA.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kern.ld.S: move .scattered_array* into .data.rel.ro

Moves the symbols tagged with .scattered_array* from the .rodata output
section into a new output section: .data.rel.ro, which is also writ

core: kern.ld.S: move .scattered_array* into .data.rel.ro

Moves the symbols tagged with .scattered_array* from the .rodata output
section into a new output section: .data.rel.ro, which is also writeable
(hence the suppression of __SECTION_FLAGS_RODATA in scattered_array.h)
but placed in tee.elf to be mapped read-only after relocations are
applied. The new section is created only when core ASLR is enabled,
otherwise no relocation can occur and we can keep the previous code.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add delimited area in .text to store data

A few variables such as boot_mmu_config are stored within the .text
section of tee.elf, because they need to be reachable from the identity
mapping wh

core: add delimited area in .text to store data

A few variables such as boot_mmu_config are stored within the .text
section of tee.elf, because they need to be reachable from the identity
mapping which covers a subset of .text. Having them here however is a
problem when one wants to measure (hash) the .text section because the
runtime content may be different from the content in the tee.elf. In
order to workaround this issue, allocate an area in the .text section
to gather the data that are modified at boot time. Symbols tagged with
.identity_map.data will be stored there. Two delimiters are introduced:
__text_data_start and __text_data_end.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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kernel/linker.h: export __text_end

Add __text_end to <kernel/linker.h>. Can be used for example to compute
a hash of the TEE executable code in a remote attestation scenario.

Signed-off-by: Jerome

kernel/linker.h: export __text_end

Add __text_end to <kernel/linker.h>. Can be used for example to compute
a hash of the TEE executable code in a remote attestation scenario.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: suppress text relocation on stack_tmp_export

stack_tmp_export is a pointer so it is associated with a dynamic
relocation when position-independent code is generated (ASLR). Moreover,
this symb

core: suppress text relocation on stack_tmp_export

stack_tmp_export is a pointer so it is associated with a dynamic
relocation when position-independent code is generated (ASLR). Moreover,
this symbol is in the .identity_map section, which is part of .text after
the final link. To get rid of this TEXTREL, remove stack_tmp_export and
compute the corresponding value in assembly instead from stack_tmp and
constants defined in core/arch/arm/kernel/asm-defines.c.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: provide dummy mobj_reg_shm_get_by_cookie()

Provides a dummy static inlined mobj_reg_shm_get_by_cookie() returning NULL
in case CFG_CORE_DYN_SHM=n.

Reviewed-by: Jerome Forissier <jerome@foriss

core: provide dummy mobj_reg_shm_get_by_cookie()

Provides a dummy static inlined mobj_reg_shm_get_by_cookie() returning NULL
in case CFG_CORE_DYN_SHM=n.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Add support for DEVICE_nGnRnE

Currently OP-TEE only allows non-cached memory to be mapped as
ATTR_DEVICE_nGnRE/Device. This patch adds support for
ATTR_DEVICE_nGnRnE/Strongly-ordered.

Signed-

core: Add support for DEVICE_nGnRnE

Currently OP-TEE only allows non-cached memory to be mapped as
ATTR_DEVICE_nGnRE/Device. This patch adds support for
ATTR_DEVICE_nGnRnE/Strongly-ordered.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: Add mattr_is_cached()

mattr_is_cached() can be used to determine if the mattr is cached or
not.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@lina

core: Add mattr_is_cached()

mattr_is_cached() can be used to determine if the mattr is cached or
not.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: change TEE_MATTR_CACHE_ to TEE_MATTR_MEM_TYPE_

Some extra memory types will be added. This patch renames all
TEE_MATTR_CACHE_ defines to TEE_MATTR_MEM_TYPE_. This will make the next
patches ea

core: change TEE_MATTR_CACHE_ to TEE_MATTR_MEM_TYPE_

Some extra memory types will be added. This patch renames all
TEE_MATTR_CACHE_ defines to TEE_MATTR_MEM_TYPE_. This will make the next
patches easier to understand.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: add description for get_aslr_seed()

Adds a comment describing get_aslr_seed().

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

drivers: rtc: add RTC API

This API allows to interact with a RTC registered as the system RTC.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@l

drivers: rtc: add RTC API

This API allows to interact with a RTC registered as the system RTC.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: stm32_rstctrl reset controller for stm32mp1 platforms

Implement stm32 platforms reset controller device, embedded upon
CFG_STM32_RSTCTRL=y.

The drivers exposes its reset controls to the dt

drivers: stm32_rstctrl reset controller for stm32mp1 platforms

Implement stm32 platforms reset controller device, embedded upon
CFG_STM32_RSTCTRL=y.

The drivers exposes its reset controls to the dt_driver provider and
with stm32mp1 platform legacy reset control API function:
stm32_reset_assert(), stm32_reset_deassert() and
stm32_reset_assert_deassert_mcu().

This change also removes source file stm32mp1_rcc.c that has moved
to drivers/rstctrl/stm32_rstctrl.c but stm32_rcc_base() definition
which is moved into to platform main.c.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat: arm: refactor GIC initialization

All platforms (except STM32MP1) follow the same pattern during GIC
initialization: get virtual addresses for distributor (and optionally,
for CPU interface), c

plat: arm: refactor GIC initialization

All platforms (except STM32MP1) follow the same pattern during GIC
initialization: get virtual addresses for distributor (and optionally,
for CPU interface), check that they are not NULL, call either
gic_init() or gic_init_base_addr().

We can move most of this logic into gic_init_base_addr(), while
platform-specific code will supply only base physical addresses for
distributor and CPU interface. This will simplify and align platform
code.

ST32MP1 had more complex logic, as it used io_pa_or_va_secure() to get
MMIO range addresses. However, as main_init_gic() called
assert(cpu_mmu_enabled()), there is no sense in using
io_pa_or_va_secure(), because we already ensured that VA will be
always used. Thus assert() call was moved to gic_init_base_addr(), and
STM32MP1 were aligned with other platforms.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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