1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* 3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved 4 */ 5 6 #ifndef CLK_STM32_CORE_H 7 #define CLK_STM32_CORE_H 8 9 #include <drivers/clk.h> 10 11 struct mux_cfg { 12 uint16_t offset; 13 uint8_t shift; 14 uint8_t width; 15 uint8_t ready; 16 }; 17 18 struct gate_cfg { 19 uint16_t offset; 20 uint8_t bit_idx; 21 uint8_t set_clr; 22 }; 23 24 struct div_table_cfg { 25 unsigned int val; 26 unsigned int div; 27 }; 28 29 struct div_cfg { 30 uint16_t offset; 31 uint8_t shift; 32 uint8_t width; 33 uint8_t flags; 34 uint8_t ready; 35 const struct div_table_cfg *table; 36 }; 37 38 struct clk_stm32_priv { 39 uintptr_t base; 40 const struct mux_cfg *muxes; 41 const uint32_t nb_muxes; 42 const struct gate_cfg *gates; 43 const uint32_t nb_gates; 44 const struct div_cfg *div; 45 const uint32_t nb_div; 46 void *pdata; 47 }; 48 49 struct clk_fixed_rate_cfg { 50 unsigned long rate; 51 }; 52 53 struct fixed_factor_cfg { 54 unsigned int mult; 55 unsigned int div; 56 }; 57 58 struct clk_gate_cfg { 59 uint32_t offset; 60 uint8_t bit_idx; 61 }; 62 63 struct clk_stm32_mux_cfg { 64 int mux_id; 65 }; 66 67 struct clk_stm32_gate_cfg { 68 int gate_id; 69 }; 70 71 struct clk_stm32_div_cfg { 72 int div_id; 73 }; 74 75 struct clk_stm32_composite_cfg { 76 int gate_id; 77 int div_id; 78 int mux_id; 79 }; 80 81 struct clk_stm32_timer_cfg { 82 uint32_t apbdiv; 83 uint32_t timpre; 84 }; 85 86 struct clk_stm32_gate_ready_cfg { 87 int gate_id; 88 int gate_rdy_id; 89 }; 90 91 /* Define for divider clocks */ 92 #define CLK_DIVIDER_ONE_BASED BIT(0) 93 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 94 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 95 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 96 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 97 #define CLK_DIVIDER_READ_ONLY BIT(5) 98 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) 99 #define CLK_DIVIDER_BIG_ENDIAN BIT(7) 100 101 #define DIV_NO_RDY UINT8_MAX 102 #define MUX_NO_RDY UINT8_MAX 103 104 #define MASK_WIDTH_SHIFT(_width, _shift) \ 105 GENMASK_32(((_width) + (_shift) - 1U), (_shift)) 106 107 /* Define for composite clocks */ 108 #define NO_MUX INT32_MAX 109 #define NO_DIV INT32_MAX 110 #define NO_GATE INT32_MAX 111 112 void stm32_gate_enable(uint16_t gate_id); 113 void stm32_gate_disable(uint16_t gate_id); 114 bool stm32_gate_is_enabled(uint16_t gate_id); 115 TEE_Result stm32_gate_wait_ready(uint16_t gate_id, bool ready_on); 116 TEE_Result stm32_gate_rdy_enable(uint16_t gate_id); 117 TEE_Result stm32_gate_rdy_disable(uint16_t gate_id); 118 119 size_t stm32_mux_get_parent(uint32_t mux_id); 120 TEE_Result stm32_mux_set_parent(uint16_t pid, uint8_t sel); 121 122 TEE_Result stm32_div_set_rate(int div_id, unsigned long rate, 123 unsigned long prate); 124 125 uint32_t stm32_div_get_value(int div_id); 126 TEE_Result stm32_div_set_value(uint32_t div_id, uint32_t value); 127 128 int clk_stm32_parse_fdt_by_name(const void *fdt, int node, const char *name, 129 uint32_t *tab, uint32_t *nb); 130 131 struct clk_stm32_priv *clk_stm32_get_priv(void); 132 uintptr_t clk_stm32_get_rcc_base(void); 133 134 TEE_Result clk_stm32_init(struct clk_stm32_priv *priv, uintptr_t base); 135 136 #endif /* CLK_STM32_CORE_H */ 137