| b462b681 | 26-Feb-2025 |
Jens Wiklander <jens.wiklander@linaro.org> |
Use malloc flags MAF_* in tee_mm.h
Switch to use the malloc flags MAF_* in tee_mm.h replacing the previous TEE_MM_POOL_* flags. TEE_MM_POOL_* flags are kept defined using MAF_* flags to for easier t
Use malloc flags MAF_* in tee_mm.h
Switch to use the malloc flags MAF_* in tee_mm.h replacing the previous TEE_MM_POOL_* flags. TEE_MM_POOL_* flags are kept defined using MAF_* flags to for easier transition. The TEE_MM_POOL_* flags can be moved gradually after this commit.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 96f43358 | 26-Feb-2025 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add nex_dyn_vaspace and tee_dyn_vaspace areas
Add MEM_AREA_NEX_DYN_VASPACE and MEM_AREA_TEE_DYN_VASPACE areas for dynamic Nexus and TEE memory mapping. This will be used to map additional heap
core: add nex_dyn_vaspace and tee_dyn_vaspace areas
Add MEM_AREA_NEX_DYN_VASPACE and MEM_AREA_TEE_DYN_VASPACE areas for dynamic Nexus and TEE memory mapping. This will be used to map additional heap and the stacks in later patches.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 3006d24d | 08-Jan-2025 |
Tony Han <tony.han@microchip.com> |
plat-sam: add sama7g5's PDMC gclk clocks to the SCMI clock list
Add PDMC gclk clocks to the SCMI clock list so that they could be used outside OP-TEE OS.
Signed-off-by: Tony Han <tony.han@microchip
plat-sam: add sama7g5's PDMC gclk clocks to the SCMI clock list
Add PDMC gclk clocks to the SCMI clock list so that they could be used outside OP-TEE OS.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| b0da0d59 | 06-Mar-2025 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: boot: add boot_init_primary_runtime()
Split the early parts of boot_init_primary_final() into boot_init_primary_runtime(). boot_init_primary_runtime() initializes the runtime, part of that is
core: boot: add boot_init_primary_runtime()
Split the early parts of boot_init_primary_final() into boot_init_primary_runtime(). boot_init_primary_runtime() initializes the runtime, part of that is to generate the PAUTH keys. The PAUTH keys are loaded in assembly before boot_init_primary_final() is called.
This fixes an error when SPs are initialized by entering and exiting S-EL0 from boot_init_primary_final() but the PAUTH registers hasn't been initialized with the right values. E/TC:0 0 Core undef-abort at address 0xe106be4 E/TC:0 0 esr 0x72000000 ttbr0 0x200000e27d000 ttbr1 0x00000000 cidr 0x0 E/TC:0 0 cpu #0 cpsr 0x60000144 E/TC:0 0 x0 0000000000000000 x1 0000000000000000 E/TC:0 0 x2 0000000000000000 x3 0000000000000000 E/TC:0 0 x4 000000000e27a060 x5 000000000e27a05c E/TC:0 0 x6 000000000000009f x7 0000000000000083 E/TC:0 0 x8 0000000000000000 x9 0000000000004367 E/TC:0 0 x10 000000000000009f x11 0000000000000000 E/TC:0 0 x12 0000000000000000 x13 0000000040006f80 E/TC:0 0 x14 0000000000000000 x15 0000000000000000 E/TC:0 0 x16 000000000e107460 x17 0000000000000000 E/TC:0 0 x18 0000000000000000 x19 000000000e002000 E/TC:0 0 x20 000000000e300000 x21 0000000040000000 E/TC:0 0 x22 0000000000000000 x23 000000000e272830 E/TC:0 0 x24 000000000e22c250 x25 0000000000000000 E/TC:0 0 x26 0000000000000000 x27 0000000000000000 E/TC:0 0 x28 0000000000000000 x29 000000000e27a020 E/TC:0 0 x30 0a2ed3b10e1314e8 elr 000000000e106be4 E/TC:0 0 sp_el0 000000000e27a010 E/TC:0 0 TEE load address @ 0xe100000 E/TC:0 0 Core undef-abort at address 0xe106be4 .debug_info+27620 E/TC:0 0 Call stack: E/TC:0 0 0x0e106be4 thread_enter_user_mode at core/arch/arm/kernel/thread.c:1049 E/TC:0 0 0x0e110628 sp_open_session at core/arch/arm/kernel/secure_partition.c:635 E/TC:0 0 0x0e112508 sp_init_uuid at core/arch/arm/kernel/secure_partition.c:1583 E/TC:0 0 0x0e1135f8 sp_init_all at core/arch/arm/kernel/secure_partition.c:2018 E/TC:0 0 0x0e137950 do_init_calls at core/kernel/initcall.c:20 E/TC:0 0 0x0e137b0c call_finalcalls at core/kernel/initcall.c:73
Fixes: b5ec8152f3e5 ("core: arm: refactor boot") Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| bea90f04 | 03-Mar-2025 |
Alvin Chang <alvinga@andestech.com> |
core: Implicitly enable CFG_BOOT_MEM
Now both ARM and RISC-V architectures support and enable CFG_BOOT_MEM by default. It's unnecessary to define CFG_BOOT_MEM. This commit removes CFG_BOOT_MEM and r
core: Implicitly enable CFG_BOOT_MEM
Now both ARM and RISC-V architectures support and enable CFG_BOOT_MEM by default. It's unnecessary to define CFG_BOOT_MEM. This commit removes CFG_BOOT_MEM and relevant dead code.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
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| 69e9ad1b | 27-Feb-2025 |
Huang Borong <huangborong@bosc.ac.cn> |
drivers: add RISC-V APLIC interrupt driver
The RISC-V Advanced Interrupt Architecture (AIA) specification introduces the APLIC, which can serve as a new external interrupt controller to replace the
drivers: add RISC-V APLIC interrupt driver
The RISC-V Advanced Interrupt Architecture (AIA) specification introduces the APLIC, which can serve as a new external interrupt controller to replace the original Platform-Level Interrupt Controller (PLIC) or as a device to convert wired interrupts into message-signaled interrupts (MSIs) and forward them to the Incoming MSI Controller (IMSIC).
The APLIC driver supports both "direct delivery mode" and "MSI delivery mode." Use the `CFG_RISCV_APLIC` flag to enable the APLIC driver in "direct delivery mode," and use the `CFG_RISCV_APLIC_MSI` flag to enable the APLIC driver in "MSI delivery mode" when selecting `CFG_RISCV_IMSIC`.
APLIC initialization can be done through the device tree.
For more details, see: https://github.com/riscv/riscv-aia
Signed-off-by: Huang Borong <huangborong@bosc.ac.cn> Reviewed-by: Alvin Chang <alvinga@andestech.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| f4b54213 | 27-Feb-2025 |
Huang Borong <huangborong@bosc.ac.cn> |
drivers: add RISC-V IMSIC interrupt driver
The RISC-V Advanced Interrupt Architecture (AIA) specification introduces the IMSIC as a new external interrupt controller. An IMSIC receives and records i
drivers: add RISC-V IMSIC interrupt driver
The RISC-V Advanced Interrupt Architecture (AIA) specification introduces the IMSIC as a new external interrupt controller. An IMSIC receives and records incoming message-signaled interrupts (MSIs).
This commit enables the initialization of the IMSIC based on the device tree and adds control and status registers (CSRs) for indirect access to the IMSIC as well as for reading interrupt identities.
Use the `CFG_RISCV_IMSIC` flag to control whether to build this driver.
For more details, see: https://github.com/riscv/riscv-aia
Signed-off-by: Huang Borong <huangborong@bosc.ac.cn> Reviewed-by: Alvin Chang <alvinga@andestech.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 5e01ede9 | 26-Feb-2025 |
Alvin Chang <alvinga@andestech.com> |
core: kernel: Remove unused call_initcalls()
Remove call_initcalls() since there is no architecture calls it.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Jens Wiklander <jens.wi
core: kernel: Remove unused call_initcalls()
Remove call_initcalls() since there is no architecture calls it.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
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| 321b5b24 | 11-Oct-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp2: add platform-specific abort handler
When a data abort occurs and its fault type is FAULT_TYPE_IGNORE, it may be an abort generated by the SERC hardware block. Check if a SERC Illegal
plat-stm32mp2: add platform-specific abort handler
When a data abort occurs and its fault type is FAULT_TYPE_IGNORE, it may be an abort generated by the SERC hardware block. Check if a SERC Illegal Access was caught and print the SERC register and panic() if that is the case.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 325d4963 | 11-Oct-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
core: add platform-specific abort handler
Platforms may have specific code to handle an abort when fault type is FAULT_TYPE_IGNORE. Add plat_abort_handler() that can be overridden at platform level
core: add platform-specific abort handler
Platforms may have specific code to handle an abort when fault type is FAULT_TYPE_IGNORE. Add plat_abort_handler() that can be overridden at platform level.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| ae7f9049 | 07-Feb-2025 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: interrupt: fix interrupt_set_{affinity|wake}() description
Fix inline description of itr_num argument for interrupt_set_affinity() and interrupt_set_wake().
Fixes: b2d6db21ec5e ("core: interr
core: interrupt: fix interrupt_set_{affinity|wake}() description
Fix inline description of itr_num argument for interrupt_set_affinity() and interrupt_set_wake().
Fixes: b2d6db21ec5e ("core: interrupt: helper function for raise_pi, raise_sgi, set_affinity") Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| d2c318b6 | 07-Feb-2025 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: interrupt: clarify when dt_get_irq handler is needed
Add an inline comment telling struct itr_chip:dt_get_irq handler is needed only when interrupt consumer manually get configuration informat
core: interrupt: clarify when dt_get_irq handler is needed
Add an inline comment telling struct itr_chip:dt_get_irq handler is needed only when interrupt consumer manually get configuration information from the DT to later configure the interrupt. The aim of this change is to clarify this handler is not needed for interrupt provider registered with interrupt_register_provider() and which consumer rely on interrupt_dt_get_by_*() to configure their interrupts.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| df7874b5 | 14-Feb-2025 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: interrupt: itr_chip may not require configure handler
The configure handler in struct itr_ops is not required for interrupt providers which consumers only use the DT to get and configure their
core: interrupt: itr_chip may not require configure handler
The configure handler in struct itr_ops is not required for interrupt providers which consumers only use the DT to get and configure their interrupts (with interrupt_dt_get_by_*() and interrupt_create_handler()). Therefore change itr_chip_is_valid() to not enforce its support but add back that constraint for the interrupt main controller.
Add an itr_chip_dt_only_init() helper function for interrupt controllers which consumers only use the DT to configure their interrupt, that is such controllers do not need a configure handler.
itr_chip_is_valid() is not called outside interrupt.c where it is used in itr_chip_init() and itr_chip_dt_only_init() so make it a local function.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 2a50ce7d | 07-Feb-2025 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: interrupt: rename .add handler to .configure
Rename field add of struct itr_ops to configure for consistency since that handler is used the configure the interrupt. Update existing interrupt d
core: interrupt: rename .add handler to .configure
Rename field add of struct itr_ops to configure for consistency since that handler is used the configure the interrupt. Update existing interrupt drivers accordingly.
By the way fix inline comment spelling typo (s/contrainsts/constraints/).
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| b5ec8152 | 22-Jan-2025 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: refactor boot
Introduce CFG_BOOT_INIT_THREAD_CORE_LOCAL0 to indicate that thread_core_local[0] is initialized before the boot_init_* functions are called.
thread_init_core_local_stacks()
core: arm: refactor boot
Introduce CFG_BOOT_INIT_THREAD_CORE_LOCAL0 to indicate that thread_core_local[0] is initialized before the boot_init_* functions are called.
thread_init_core_local_stacks() and thread_init_thread_core_local() are replaced by a new version of thread_init_thread_core_local() for CFG_BOOT_INIT_THREAD_CORE_LOCAL0=y.
Move initialization of thread_core_local[] from very early to boot_init_primary_late() where various DTBs containing run-time configuration are available. This will be needed in later patches when the number of configured cores can be read from DT or some other run-time configuration.
Move the "OP-TEE version" print and following code from boot_init_primary_late() to boot_init_primary_final()
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 7d9d593d | 05-Feb-2025 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: firewall: stm32_etzpc: remove header file
Remove stm32_etzpc.h header file that is not required since the declared and defined resources are used internally in stm32_etzpc.c
By the way, al
drivers: firewall: stm32_etzpc: remove header file
Remove stm32_etzpc.h header file that is not required since the declared and defined resources are used internally in stm32_etzpc.c
By the way, also remove inclusion of stm32mp15-etzpc.h DT bindings header file from stm32_rng.c where it is not needed.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 62673d08 | 22-Jan-2025 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: initcall.h: make boot_final() last final call
Make the boot_final() call last among the final call, that is, after the xen_*_init*() calls. spmc_init() accesses the manifest_fd so it must be c
core: initcall.h: make boot_final() last final call
Make the boot_final() call last among the final call, that is, after the xen_*_init*() calls. spmc_init() accesses the manifest_fd so it must be called before release_manifest_dt() removes it.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 50cbe7eb | 23-Jan-2025 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: interrupt: explicit dt_get_irq handler expects big endian data
Explicit that struct itr_chip::dt_get_irq handler expects a reference to an array of big-endian properties. This was implicitly t
core: interrupt: explicit dt_get_irq handler expects big endian data
Explicit that struct itr_chip::dt_get_irq handler expects a reference to an array of big-endian properties. This was implicitly told before since DTB format is big-endian.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 77c4fee6 | 24-Jan-2025 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: interrupt: fix interrupt_create_handler() description
Correct inline description comment of interrupt_create_handler() that referred deprecated API function labels dt_get_interrupt_by_*() and
core: interrupt: fix interrupt_create_handler() description
Correct inline description comment of interrupt_create_handler() that referred deprecated API function labels dt_get_interrupt_by_*() and mention argument itr_desc that was reaplce with the 2 arguments itr_chip and itr_num.
By the way, indent functions argument description for consistency with the other function inline description comments in this header file.
Fixes: e9376d025eb5 ("core: interrupt: add interrupt_create_handler()") Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| bb032271 | 22-Jan-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
dt-bindings: add RISAL bindings in the RIFSC file
Add the RISAL bindings in the RIFSC file as the RISAL is a sub-feature of the RIFSC.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.co
dt-bindings: add RISAL bindings in the RIFSC file
Add the RISAL bindings in the RIFSC file as the RISAL is a sub-feature of the RIFSC.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| ded20780 | 23-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: stm32_i2c: use compatible st,stm32mp15-i2c-non-secure
Change STM32 I2C driver to rely on the compatible DT property of the node to store whether the bus is expected assigned to secure or no
drivers: stm32_i2c: use compatible st,stm32mp15-i2c-non-secure
Change STM32 I2C driver to rely on the compatible DT property of the node to store whether the bus is expected assigned to secure or non-secure world. Using a non-secure I2C bus in OP-TEE on stm32mp1 platforms is something expected only on STM32MP15 variant for compatibility with platform already supported in upstream Linux/U-Boot components, as defined by st,stm32mp15-i2c-non-secure specific compatible string ID.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| dc2cf47a | 16-Jan-2025 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: rpmb: get RPMB storage space allocation stats
Add rpmb_mem_stats() to get the RPMB secure storage space allocation statistics.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> A
core: rpmb: get RPMB storage space allocation stats
Add rpmb_mem_stats() to get the RPMB secure storage space allocation statistics.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| b0b019b8 | 12-Dec-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: counter: stm32_stgen: add STGEN driver
STGEN is the platform timer. It generates a time-count value that provides a consistent view of time for multiple processors and other blocks in a dev
drivers: counter: stm32_stgen: add STGEN driver
STGEN is the platform timer. It generates a time-count value that provides a consistent view of time for multiple processors and other blocks in a device. It is physically linked to the ARM generic timer.
Add the STGEN driver that is in charge of configuring the ARM generic timer source and send an SMC to the BL31 monitor to update the CP15 register. This driver is only compatible for 64bits platforms.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 73aafcc9 | 08-Jan-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: rtc: check data consistency in rtc_set_time()
Ensure that arguments passed to rtc_set_time() are coherent to defined RTC range and Gregorian calendar values.
Signed-off-by: Gatien Chevalli
drivers: rtc: check data consistency in rtc_set_time()
Ensure that arguments passed to rtc_set_time() are coherent to defined RTC range and Gregorian calendar values.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| a83e616e | 08-Jan-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: rtc: add RTC_TIME() helper macro
Add RTC_TIME() helper macro that allows to initialize all fields of a struct optee_rtc_time.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.co
drivers: rtc: add RTC_TIME() helper macro
Add RTC_TIME() helper macro that allows to initialize all fields of a struct optee_rtc_time.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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