drivers: stm32_remote_proc: add stm32_rproc_is_secure()

Add stm32_remoteproc driver API function stm32_rproc_is_secure()
that return whether of not remote processor management shall be
handled throu

drivers: stm32_remote_proc: add stm32_rproc_is_secure()

Add stm32_remoteproc driver API function stm32_rproc_is_secure()
that return whether of not remote processor management shall be
handled through OP-TEE remoteproc secure services.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>

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dt-bindings: add stm32 bindings for TZC400 platform configuration

Add stm32 specific peripheral IDs for the TZC400 configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Re

dt-bindings: add stm32 bindings for TZC400 platform configuration

Add stm32 specific peripheral IDs for the TZC400 configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_etzpc: update driver to set ETZPC configuration from DT

Remove old implementation where the ETZPC configuration was a hard
coded table in the shared resources file and use the device

drivers: stm32_etzpc: update driver to set ETZPC configuration from DT

Remove old implementation where the ETZPC configuration was a hard
coded table in the shared resources file and use the device tree to
get it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: add platform specific ETZPC bindings

Define ETZPC bindings for STM32MP15 and STM32MP13 and add these
header files into the stm32mp_dt_bindings helper. While there, also
update some incl

dt-bindings: add platform specific ETZPC bindings

Define ETZPC bindings for STM32MP15 and STM32MP13 and add these
header files into the stm32mp_dt_bindings helper. While there, also
update some includes to fix the path errors.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risab: add RISAB internal memory firewall driver

This driver implements the RISAB driver. Through RISAB registers, a
trusted compartment, or the compartment to which the page configur

drivers: stm32_risab: add RISAB internal memory firewall driver

This driver implements the RISAB driver. Through RISAB registers, a
trusted compartment, or the compartment to which the page configuration
has been delegated, configures the firewall attributes necessary to
access a page.

Each RISAB is dedicated to a internal memory and can cover 128KBytes of
data, separated in 32 pages of 4 KBytes, containing 8 blocks each.

It is possible to align a RISAB secure and privilege regions
allocations with an ARM Cortex M, which defines in its address space
configurable regions with a 256Bytes granularity. The configuration
would be 512Bytes block-based in order to align the two.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: remove firewall_dt_probe_bus()

Remove firewall_dt_probe_bus() from the firewall framework as it seems
unlikely that we can have a consensual implementation of this feature.

Signe

drivers: firewall: remove firewall_dt_probe_bus()

Remove firewall_dt_probe_bus() from the firewall framework as it seems
unlikely that we can have a consensual implementation of this feature.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: add stm32_risaf driver

Add the stm32_risaf driver to handle all RISAFs instances on a SoC.
Through RISAF registers, a trusted domain application, or the application
to whom the co

drivers: firewall: add stm32_risaf driver

Add the stm32_risaf driver to handle all RISAFs instances on a SoC.
Through RISAF registers, a trusted domain application, or the application
to whom the configuration has been delegated, assigns memory regions to
one or more security domains (secure, privilege, compartment).
RISAF4 includes the DDR memory cipher engine (DDRMCE) feature.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: add stm32mp25 RISAF bindings

Add stm32mp25 specific RISAF device tree bindings. This file contains
device tree contains helpers and RISAFPROT macro that is used to
define the RIF config

dt-bindings: add stm32mp25 RISAF bindings

Add stm32mp25 specific RISAF device tree bindings. This file contains
device tree contains helpers and RISAFPROT macro that is used to
define the RIF configuration for a RISAF region.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rif: tag unused parameters as __unused

When CFG_STM32_RIF is not set, inclusion of this header file causes
warnings because of function parameters not being tagged as unused.
Tag them

drivers: stm32_rif: tag unused parameters as __unused

When CFG_STM32_RIF is not set, inclusion of this header file causes
warnings because of function parameters not being tagged as unused.
Tag them properly.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Fixes: 1506f47af917 ("drivers: firewall: add stm32_rif driver for common RIF features")
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: rstctrl: Fix function description

Fix the description of functions rstctrl_dt_get_func() and
rstctrl_register_provider() and rstctrl_get_exclusive().

By the way, append parentheses ("()")

drivers: rstctrl: Fix function description

Fix the description of functions rstctrl_dt_get_func() and
rstctrl_register_provider() and rstctrl_get_exclusive().

By the way, append parentheses ("()") to function names in
inline description comment for consistency in core header files.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: stm32_remoteproc: Add remote processor memories cleanup function

This patch introduces a new function stm32_rproc_clean_up_memories() to
clean up the memory regions used by the remote proce

drivers: stm32_remoteproc: Add remote processor memories cleanup function

This patch introduces a new function stm32_rproc_clean_up_memories() to
clean up the memory regions used by the remote processor.
The function iterates over each memory region, maps it, clears the memory
by setting it to zero, and then unmaps it.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rif: add stm32_rif_access_violation_action()

This function should be used by peripherals capable on raising
access violation interrupts (SERC, IAC). The behavior of the platform
on su

drivers: stm32_rif: add stm32_rif_access_violation_action()

This function should be used by peripherals capable on raising
access violation interrupts (SERC, IAC). The behavior of the platform
on such event is platform-specific. Therefore, its definition must be
done at platform level.

Also add CFG_STM32_PANIC_ON_IAC_EVENT and CFG_STM32_PANIC_ON_SERC_EVENT
to choose if the platform should panic upon receiving an IAC or a
SERC event.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: clk_get_rates_array() returns ordered rates

Explicitly state in clk_get_rates_array() inline description comment
that the output rates arrays is ordered by increasing frequency
values.

drivers: clk: clk_get_rates_array() returns ordered rates

Explicitly state in clk_get_rates_array() inline description comment
that the output rates arrays is ordered by increasing frequency
values. This change allows to better fit the sole consumer of this
API function that is the SCMI server implementation. SCMI specification
states that discrete clock rates list shall follow this order.

Update at91_cpu_opp clock driver to ensure it satisfy this constraint.
The SAM platforms that embed this driver (sama7g5) already satisfy this
constraints but only at its DTS level. This change ensures the driver
will always.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: imx_mu: enable support for i.MX91

Enable MU driver support for i.MX91

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

drivers: rstctrl: add reset controller for STM32MP25 platforms

Implement the STM32MP25 reset controller device by embedding it
with CFG_STM32_RSTCTRL=y and CFG_STM32MP25_RSTCTRL=y.

Signed-off-by: G

drivers: rstctrl: add reset controller for STM32MP25 platforms

Implement the STM32MP25 reset controller device by embedding it
with CFG_STM32_RSTCTRL=y and CFG_STM32MP25_RSTCTRL=y.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32mp25: Introduce STM32MP25 clocks platform

This driver is based on clk-stm32-core API to manage STM32 gates, dividers
and muxes.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st

clk: stm32mp25: Introduce STM32MP25 clocks platform

This driver is based on clk-stm32-core API to manage STM32 gates, dividers
and muxes.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: add the STM32MP2 clock and reset bindings

Add the associated bindings for device tree and drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Etienne Ca

dt-bindings: add the STM32MP2 clock and reset bindings

Add the associated bindings for device tree and drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: add rcc helper function

Add dedicate include file for RCC to add helper function.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etie

plat-stm32mp2: add rcc helper function

Add dedicate include file for RCC to add helper function.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: pm: sam: add code for enable/disable sama7g5 DRAM self-refresh mode

Add the header file "sama7-ddr.h" for sama7g5 DRAM controller.
Add 2 macros for enable and disable sama7g5 DRAM self-refr

drivers: pm: sam: add code for enable/disable sama7g5 DRAM self-refresh mode

Add the header file "sama7-ddr.h" for sama7g5 DRAM controller.
Add 2 macros for enable and disable sama7g5 DRAM self-refresh mode.
Enable self-refresh mode before entering the low-power modes and
disable it after exiting the low-power modes.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: firewall: add firewall framework

Add a generic firewall controller framework. The goal of this framework
is to offer access control and configuration APIs, that are implemented
in the firewall

core: firewall: add firewall framework

Add a generic firewall controller framework. The goal of this framework
is to offer access control and configuration APIs, that are implemented
in the firewall controllers drivers, to the firewall consumers. This
framework requires an embedded device tree.

A firewall controller is an access controller [1]. It should register
itself as a provider to the framework. Firewall controllers have the
possibility to populate their bus according to defined firewall accesses
defined in the "access-controllers" property in each of the device's
node.

Any device that consumes one or more firewall should refer it/them in
their "access-controllers" property. Arguments can be passed along with
the phandle of the firewall controller(s).

Link: https://patchwork.kernel.org/project/linux-media/patch/20240105130404.301172-2-gatien.chevallier@foss.st.com/ [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: Add FFA_CONSOLE based console driver for log

This console driver uses FFA_CONSOLE ABI to write the trace logs.

If CFG_FFA_CONSOLE is enabled, OP-TEE will try to initialize the console
driv

drivers: Add FFA_CONSOLE based console driver for log

This console driver uses FFA_CONSOLE ABI to write the trace logs.

If CFG_FFA_CONSOLE is enabled, OP-TEE will try to initialize the console
driver that uses FFA interface to print trace logs.

Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: pm: sam: rename pm_init functions for later sama7g5 support

PM support for sama7g5 will reuse some existing functions.
Rename sama5d2_pm_init() to sam_pm_init().
Rename sama5d2_pm_init_all(

drivers: pm: sam: rename pm_init functions for later sama7g5 support

PM support for sama7g5 will reuse some existing functions.
Rename sama5d2_pm_init() to sam_pm_init().
Rename sama5d2_pm_init_all() to sam_pm_init_all().

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: atmel_shdwc: enable RTT (Real-time Timer) Wake-up

For sama7g5 the Wake-up can be caused by RTT.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@li

drivers: atmel_shdwc: enable RTT (Real-time Timer) Wake-up

For sama7g5 the Wake-up can be caused by RTT.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: include standard header files from stpmic1_regulator.h

Add missing inclusion of stdbool.h and stddef.h in stpmic1_regulator.h.
The issue was revealed when upgrading to latest SCP-firmware s

drivers: include standard header files from stpmic1_regulator.h

Add missing inclusion of stdbool.h and stddef.h in stpmic1_regulator.h.
The issue was revealed when upgrading to latest SCP-firmware source tree.

Fixes: 9cb0d51670f2 ("drivers: stpmic1: export regulators API in a specific header file")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: firewall: fix stm32_rif_semaphore_enabled_and_ok() prototype

The stm32_rif_semaphore_enabled_and_ok() function checks a single CID
at a time, not a bit field.

Fixes: 1506f47af917 ("drivers

drivers: firewall: fix stm32_rif_semaphore_enabled_and_ok() prototype

The stm32_rif_semaphore_enabled_and_ok() function checks a single CID
at a time, not a bit field.

Fixes: 1506f47af917 ("drivers: firewall: add stm32_rif driver for common RIF features")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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