xref: /optee_os/core/arch/arm/dts/stm32mp251.dtsi (revision 85df05e1fba86dbdd7f5e8af31c5ad1e496ab20f) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/clock/st,stm32mp25-rcc.h>
8#include <dt-bindings/firewall/stm32mp25-rifsc.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/reset/st,stm32mp25-rcc.h>
11
12/ {
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			compatible = "arm,cortex-a35";
22			device_type = "cpu";
23			reg = <0>;
24			enable-method = "psci";
25		};
26	};
27
28	psci {
29		compatible = "arm,psci-1.0";
30		method = "smc";
31	};
32
33	intc: interrupt-controller@4ac00000 {
34		compatible = "arm,cortex-a7-gic";
35		#interrupt-cells = <3>;
36		interrupt-controller;
37		reg = <0x0 0x4ac10000 0x0 0x1000>,
38		      <0x0 0x4ac20000 0x0 0x2000>,
39		      <0x0 0x4ac40000 0x0 0x2000>,
40		      <0x0 0x4ac60000 0x0 0x2000>;
41		#address-cells = <1>;
42	};
43
44	clocks {
45		clk_hse: clk-hse {
46			#clock-cells = <0>;
47			compatible = "fixed-clock";
48			clock-frequency = <24000000>;
49		};
50
51		clk_hsi: clk-hsi {
52			#clock-cells = <0>;
53			compatible = "fixed-clock";
54			clock-frequency = <64000000>;
55		};
56
57		clk_lse: clk-lse {
58			#clock-cells = <0>;
59			compatible = "fixed-clock";
60			clock-frequency = <32768>;
61		};
62
63		clk_lsi: clk-lsi {
64			#clock-cells = <0>;
65			compatible = "fixed-clock";
66			clock-frequency = <32000>;
67		};
68
69		clk_msi: clk-msi {
70			#clock-cells = <0>;
71			compatible = "fixed-clock";
72			clock-frequency = <4000000>;
73		};
74
75		clk_i2sin: clk-i2sin {
76			#clock-cells = <0>;
77			compatible = "fixed-clock";
78			clock-frequency = <0>;
79		};
80
81		clk_rcbsec: clk-rcbsec {
82			#clock-cells = <0>;
83			compatible = "fixed-clock";
84			clock-frequency = <64000000>;
85		};
86	};
87
88	soc@0 {
89		compatible = "simple-bus";
90		#address-cells = <1>;
91		#size-cells = <1>;
92		interrupt-parent = <&intc>;
93		ranges = <0x0 0x0 0x0 0x80000000>;
94
95		hpdma1: dma-controller@40400000 {
96			compatible = "st,stm32-dma3";
97			reg = <0x40400000 0x1000>;
98			#dma-cells = <4>;
99			status = "disabled";
100		};
101
102		hpdma2: dma-controller@40410000 {
103			compatible = "st,stm32-dma3";
104			reg = <0x40410000 0x1000>;
105			#dma-cells = <4>;
106			status = "disabled";
107		};
108
109		hpdma3: dma-controller@40420000 {
110			compatible = "st,stm32-dma3";
111			reg = <0x40420000 0x1000>;
112			#dma-cells = <4>;
113			status = "disabled";
114		};
115
116		ipcc1: mailbox@40490000 {
117			compatible = "st,stm32mp25-ipcc";
118			reg = <0x40490000 0x400>;
119			status = "disabled";
120		};
121
122		rifsc: rifsc@42080000 {
123			compatible = "st,stm32mp25-rifsc";
124			reg = <0x42080000 0x1000>;
125			#address-cells = <1>;
126			#size-cells = <1>;
127
128			usart2: serial@400e0000 {
129				compatible = "st,stm32h7-uart";
130				reg = <0x400e0000 0x400>;
131				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
132				clocks = <&rcc CK_KER_USART2>;
133				access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>;
134				status = "disabled";
135			};
136		};
137
138		iac: iac@42090000 {
139			compatible = "st,stm32mp25-iac";
140			reg = <0x42090000 0x400>;
141			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
142		};
143
144		serc: serc@44080000 {
145			compatible = "st,stm32mp25-serc";
146			reg = <0x44080000 0x1000>;
147			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
148			clocks = <&rcc CK_BUS_SERC>;
149		};
150
151		rcc: rcc@44200000 {
152			compatible = "st,stm32mp25-rcc", "syscon";
153			reg = <0x44200000 0x10000>;
154			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
155
156			#clock-cells = <1>;
157			#reset-cells = <1>;
158			clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>,
159				 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>;
160			clock-names = "clk-hse", "clk-hsi", "clk-lse",
161				      "clk-lsi", "clk-msi", "clk-i2sin";
162
163			hsi_calibration: hsi-calibration {
164				compatible = "st,hsi-cal";
165				st,cal_hsi_dev = <31>;
166				st,cal_hsi_ref = <1953>;
167				status = "disabled";
168			};
169
170			msi_calibration: msi-calibration {
171				compatible = "st,msi-cal";
172				status = "disabled";
173			};
174		};
175
176		pinctrl: pinctrl@44240000 {
177			#address-cells = <1>;
178			#size-cells = <1>;
179			compatible = "st,stm32mp257-pinctrl";
180			ranges = <0 0x44240000 0xa0400>;
181			pins-are-numbered;
182
183			gpioa: gpio@44240000 {
184				gpio-controller;
185				#gpio-cells = <2>;
186				interrupt-controller;
187				#interrupt-cells = <2>;
188				reg = <0x0 0x400>;
189				clocks = <&rcc CK_BUS_GPIOA>;
190				st,bank-name = "GPIOA";
191				status = "disabled";
192			};
193
194			gpiob: gpio@44250000 {
195				gpio-controller;
196				#gpio-cells = <2>;
197				interrupt-controller;
198				#interrupt-cells = <2>;
199				reg = <0x10000 0x400>;
200				clocks = <&rcc CK_BUS_GPIOB>;
201				st,bank-name = "GPIOB";
202				status = "disabled";
203			};
204
205			gpioc: gpio@44260000 {
206				gpio-controller;
207				#gpio-cells = <2>;
208				interrupt-controller;
209				#interrupt-cells = <2>;
210				reg = <0x20000 0x400>;
211				clocks = <&rcc CK_BUS_GPIOC>;
212				st,bank-name = "GPIOC";
213				status = "disabled";
214			};
215
216			gpiod: gpio@44270000 {
217				gpio-controller;
218				#gpio-cells = <2>;
219				interrupt-controller;
220				#interrupt-cells = <2>;
221				reg = <0x30000 0x400>;
222				clocks = <&rcc CK_BUS_GPIOD>;
223				st,bank-name = "GPIOD";
224				status = "disabled";
225			};
226
227			gpioe: gpio@44280000 {
228				gpio-controller;
229				#gpio-cells = <2>;
230				interrupt-controller;
231				#interrupt-cells = <2>;
232				reg = <0x40000 0x400>;
233				clocks = <&rcc CK_BUS_GPIOE>;
234				st,bank-name = "GPIOE";
235				status = "disabled";
236			};
237
238			gpiof: gpio@44290000 {
239				gpio-controller;
240				#gpio-cells = <2>;
241				interrupt-controller;
242				#interrupt-cells = <2>;
243				reg = <0x50000 0x400>;
244				clocks = <&rcc CK_BUS_GPIOF>;
245				st,bank-name = "GPIOF";
246				status = "disabled";
247			};
248
249			gpiog: gpio@442a0000 {
250				gpio-controller;
251				#gpio-cells = <2>;
252				interrupt-controller;
253				#interrupt-cells = <2>;
254				reg = <0x60000 0x400>;
255				clocks = <&rcc CK_BUS_GPIOG>;
256				st,bank-name = "GPIOG";
257				status = "disabled";
258			};
259
260			gpioh: gpio@442b0000 {
261				gpio-controller;
262				#gpio-cells = <2>;
263				interrupt-controller;
264				#interrupt-cells = <2>;
265				reg = <0x70000 0x400>;
266				clocks = <&rcc CK_BUS_GPIOH>;
267				st,bank-name = "GPIOH";
268				status = "disabled";
269			};
270
271			gpioi: gpio@442c0000 {
272				gpio-controller;
273				#gpio-cells = <2>;
274				interrupt-controller;
275				#interrupt-cells = <2>;
276				reg = <0x80000 0x400>;
277				clocks = <&rcc CK_BUS_GPIOI>;
278				st,bank-name = "GPIOI";
279				status = "disabled";
280			};
281
282			gpioj: gpio@442d0000 {
283				gpio-controller;
284				#gpio-cells = <2>;
285				interrupt-controller;
286				#interrupt-cells = <2>;
287				reg = <0x90000 0x400>;
288				clocks = <&rcc CK_BUS_GPIOJ>;
289				st,bank-name = "GPIOJ";
290				status = "disabled";
291			};
292
293			gpiok: gpio@442e0000 {
294				gpio-controller;
295				#gpio-cells = <2>;
296				interrupt-controller;
297				#interrupt-cells = <2>;
298				reg = <0xa0000 0x400>;
299				clocks = <&rcc CK_BUS_GPIOK>;
300				st,bank-name = "GPIOK";
301				status = "disabled";
302			};
303		};
304
305		pinctrl_z: pinctrl-z@46200000 {
306			#address-cells = <1>;
307			#size-cells = <1>;
308			compatible = "st,stm32mp257-z-pinctrl";
309			ranges = <0 0x46200000 0x400>;
310			pins-are-numbered;
311
312			gpioz: gpio@46200000 {
313				gpio-controller;
314				#gpio-cells = <2>;
315				interrupt-controller;
316				#interrupt-cells = <2>;
317				reg = <0 0x400>;
318				clocks = <&rcc CK_BUS_GPIOZ>;
319				st,bank-name = "GPIOZ";
320				st,bank-ioport = <11>;
321				status = "disabled";
322			};
323		};
324
325		hsem: hwspinlock@46240000 {
326			compatible = "st,stm32mp25-hsem";
327			reg = <0x46240000 0x400>;
328			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
329			status = "disabled";
330		};
331
332		ipcc2: mailbox@46250000 {
333			compatible = "st,stm32mp25-ipcc";
334			reg = <0x46250000 0x400>;
335			status = "disabled";
336		};
337
338		fmc: memory-controller@48200000 {
339			#address-cells = <2>;
340			#size-cells = <1>;
341			compatible = "st,stm32mp25-fmc2-ebi";
342			reg = <0x48200000 0x400>;
343			status = "disabled";
344
345			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
346				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
347				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
348				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
349				 <4 0 0x80000000 0x10000000>; /* NAND */
350		};
351	};
352};
353