drivers: stm32_rtc: add the capability to wakeup the platform

During probe, we look for the property "wakeup-source" that
will trigger the feature "RTC_WAKEUP_ALARM" which will
be send to the caller

drivers: stm32_rtc: add the capability to wakeup the platform

During probe, we look for the property "wakeup-source" that
will trigger the feature "RTC_WAKEUP_ALARM" which will
be send to the callers of the framework `rtc_get_info()` PTA.

We also register the `stm32_rtc_alarm_wake_set_status()` callback.
This callback should be called when the callers knows that the platform
will go in sleep mode.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_rtc: add alarm related operations

The RTC framework allows the registration of function :
- `read_alarm()`
- `set_alarm()`
- `alarm_enable()`
- `wait_alarm()`
- `cancel_wait()`

Signe

drivers: stm32_rtc: add alarm related operations

The RTC framework allows the registration of function :
- `read_alarm()`
- `set_alarm()`
- `alarm_enable()`
- `wait_alarm()`
- `cancel_wait()`

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_rtc: add init configuration function

The init function aims to contains init configurations of the RTC
peripheral such as prescalers, config or calibration registers.
Add "CFG_STM32_H

drivers: stm32_rtc: add init configuration function

The init function aims to contains init configurations of the RTC
peripheral such as prescalers, config or calibration registers.
Add "CFG_STM32_HIGH_ACCURACY" (default to no) config to enable the
high accuracy mode which allow the highest refresh rate of the subsecond
register.
Also merge the functions `stm32_rtc_wait_sync()` with
`stm32_exit_init_mode()` as every stm32 exit init mode was followed
by a wait sync.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: rstctrl: add security check for STM32MP25 reset controller

Test if the id of the peripheral is not out of range.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-b

drivers: rstctrl: add security check for STM32MP25 reset controller

Test if the id of the peripheral is not out of range.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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clk: stm32mp25: cosmetic fixes for STM32MP25 clock driver

Cosmetic fixes to align STM32MP21 and STM32MP25 clock drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by

clk: stm32mp25: cosmetic fixes for STM32MP25 clock driver

Cosmetic fixes to align STM32MP21 and STM32MP25 clock drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: rstctrl: add reset controller for STM32MP21 platforms

Implement the STM32MP21 reset controller device by embedding it
with CFG_STM32_RSTCTRL=y and CFG_STM32MP21_RSTCTRL=y.

Signed-off-by: N

drivers: rstctrl: add reset controller for STM32MP21 platforms

Implement the STM32MP21 reset controller device by embedding it
with CFG_STM32_RSTCTRL=y and CFG_STM32MP21_RSTCTRL=y.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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clk: stm32mp21: introduce STM32MP21 clock driver

As the STM32MP25 clock driver, this driver is based on the
clk-stm32-core API to manage STM32 gates, dividers, and multiplexer.

Signed-off-by: Yann

clk: stm32mp21: introduce STM32MP21 clock driver

As the STM32MP25 clock driver, this driver is based on the
clk-stm32-core API to manage STM32 gates, dividers, and multiplexer.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: hfic: handle well-known interrupt IDs

The paravirtualized interrupt interface has a few interrupt IDs reserved
for special purposes, for instance, the timer interrupt ID. Trying to
manipula

drivers: hfic: handle well-known interrupt IDs

The paravirtualized interrupt interface has a few interrupt IDs reserved
for special purposes, for instance, the timer interrupt ID. Trying to
manipulate will often result in a returned error. However, these
interrupt are all edge-triggered so they can be ignored without being
reasserted immediately. So in the assert() that checks that the
operation was successful, allow operations on the well-known IDs to
fail.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz

When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
becau

clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz

When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
because the clkext2f frequency of 400MHz is not supported.

This patch also rename the function stm32mp2_a35_ss_on_hsi to
stm32mp2_a35_ss_on_bypass to be aligned with reference manual.

Fixes: 28c10f9efa6a ("clk: stm32mp25: Introduce STM32MP25 clocks platform")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_tamp: add tamper events detection support

The anti-tamper detection circuit is used to protect sensitive data
from external attacks. The backup registers, as well as other secrets in

drivers: stm32_tamp: add tamper events detection support

The anti-tamper detection circuit is used to protect sensitive data
from external attacks. The backup registers, as well as other secrets in
the device, are protected by this anti-tamper detection circuit with
some tamper pins and internal tampers. The external tamper pins can
be configured for edge detection, or level detection with or without
filtering, or active tamper which increases the security level by auto
checking that the tamper pins are not externally opened or shorted.

Add support for the device-tree configuration of internal and external
tamper events as well as the list hardware mapped pins with their
associated tamper ID for external tampers.

While there, fix the license for this driver.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rtc: add time stamping feature support

Support the time stamping features of the RTC. It is useful to generate
a timestamp whenever a particular event occurs.

Signed-off-by: Gatien C

drivers: stm32_rtc: add time stamping feature support

Support the time stamping features of the RTC. It is useful to generate
a timestamp whenever a particular event occurs.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: add stm32_gpio_get_bank_id() helper

Add stm32_gpio_get_bank_id() helper function to get the STM32
GPIO bank ID related to its GPIO chip

Signed-off-by: Gatien Chevallier <gatien

drivers: stm32_gpio: add stm32_gpio_get_bank_id() helper

Add stm32_gpio_get_bank_id() helper function to get the STM32
GPIO bank ID related to its GPIO chip

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: add stm32 EXTI support

The stm32 EXTI peripheral is an interrupt controller that routes
the incoming interrupts to the GIC parent interrupt controller.
The EXTI can trigger the wake-up of t

drivers: add stm32 EXTI support

The stm32 EXTI peripheral is an interrupt controller that routes
the incoming interrupts to the GIC parent interrupt controller.
The EXTI can trigger the wake-up of the system on the incoming
interrupts.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: add support of STM32MP21

Update RIMU table for SM32MP21.
RISAL is not supported on STM32MP21, so do not compile RISAL API in
RISFC for STM32MP21.

Signed-off-by: Thomas Bourgoi

drivers: stm32_rifsc: add support of STM32MP21

Update RIMU table for SM32MP21.
RISAL is not supported on STM32MP21, so do not compile RISAL API in
RISFC for STM32MP21.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ffa_console: register a DT_DRIVER_UART driver

This registers ffa_console driver as a DT_DRIVER_UART driver.

Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>
Acked-by: Jerome Forissier <jer

drivers: ffa_console: register a DT_DRIVER_UART driver

This registers ffa_console driver as a DT_DRIVER_UART driver.

Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: amd: Add PS GPIO Support

Add PS GPIO Driver support for AMD Platforms.

The PS GPIO Controller is managed through the PS subsystem and
can operate in either the Secure World or the Non-Secu

drivers: amd: Add PS GPIO Support

Add PS GPIO Driver support for AMD Platforms.

The PS GPIO Controller is managed through the PS subsystem and
can operate in either the Secure World or the Non-Secure World.
The driver utilizes the Device Tree Blob (DTB) to determine whether the
PS GPIO Controller should be supported in the Secure World.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

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drivers: stm32_omm: add OSPI Memory Manager driver

This patch adds OSPI Memory Manager driver.
It handles:
- IOM configuration
- OSPIs address mapping
- IOM sub-system firewall configuration

Signed

drivers: stm32_omm: add OSPI Memory Manager driver

This patch adds OSPI Memory Manager driver.
It handles:
- IOM configuration
- OSPIs address mapping
- IOM sub-system firewall configuration

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: fix RIMU configuration parsing

The RIF configuration of the first RIMU was incorrectly parsed over and
over again for each RIMU. Fix this by using the index that represents
the

drivers: stm32_rifsc: fix RIMU configuration parsing

The RIF configuration of the first RIMU was incorrectly parsed over and
over again for each RIMU. Fix this by using the index that represents
the RIMU ID.

Fixes: cd187630b280 ("drivers: add stm32 RIFSC support")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: remove redundant and incorrect parsing of RIMU conf

In case we're not TDCID, we cannot configure RIMUs. Plus, the call was
redundant with the lines above.

Fixes: 471cec144fa3

drivers: stm32_rifsc: remove redundant and incorrect parsing of RIMU conf

In case we're not TDCID, we cannot configure RIMUs. Plus, the call was
redundant with the lines above.

Fixes: 471cec144fa3 ("drivers: stm32_rifsc: update RIFSC as a firewall controller")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_hpdma: implement transient CID0 on AHB errata for HPDMAs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the comp

drivers: stm32_hpdma: implement transient CID0 on AHB errata for HPDMAs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compartment
filtering is enabled on RISAB3/4/5, this transient CID0 is interpreted
as a fault access by RISAB3/4/5 which aborts current access and returns
an IAC. Described in section 2.3.21 of errata sheet available here: [1].
Therefore, when CID filtering is enabled on RISAB, we must ban CID0 as
a possible CID value configured for any initiator on the bus.
This avoids a conflict between an initiator holding CID0 and the
transient CID0.

When "st,errata-ahbrisab" is set in the device tree, HPDMA channels cannot
hold the CID0 value on the bus.

Link: https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: implement transient CID0 on AHB errata for RIMUs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compa

drivers: stm32_rifsc: implement transient CID0 on AHB errata for RIMUs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compartment
filtering is enabled on RISAB3/4/5, this transient CID0 is interpreted
as a fault access by RISAB3/4/5 which aborts current access and returns
an IAC. Described in section 2.3.21 of errata sheet available here: [1].
Therefore, when CID filtering is enabled on RISAB, we must ban CID0 as
a possible CID value configured for any initiator on the bus.
This avoids a conflict between an initiator holding CID0 and the
transient CID0.

When "st,errata-ahbrisab" is set in the device tree, RIMUs cannot hold
the CID0 value on the bus.

Link: https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risab: implement transient CID0 on AHB errata for RISAB

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compa

drivers: stm32_risab: implement transient CID0 on AHB errata for RISAB

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compartment
filtering is enabled on RISAB3/4/5, this transient CID0 is interpreted
as a fault access by RISAB3/4/5 which aborts current access and returns
an IAC. Described in section 2.3.21 of errata sheet available here: [1].
Therefore, when CID filtering is enabled on RISAB, we must ban CID0 as
a possible CID value configured for any initiator on the bus.
This avoids a conflict between an initiator holding CID0 and the
transient CID0.

Force authorize CID0 access on RISAB so that it can always access
memories protected by RISABs when the "st,errata-ahbrisab" property is
set in the device tree.

Link: https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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caam: fix compilation when CFG_NXP_CAAM_AE_* are disabled

Similarly to other CAAM modules, define empty function if CAAM AE is
not used, to avoid undefined reference to caam_ae_init().

Signed-off-b

caam: fix compilation when CFG_NXP_CAAM_AE_* are disabled

Similarly to other CAAM modules, define empty function if CAAM AE is
not used, to avoid undefined reference to caam_ae_init().

Signed-off-by: Pavel Löbl <pavel@loebl.cz>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_iwdg: check for error on clk_enable during probe

Check for the error returned by clk_enable() during the driver's
probe.
While there, if watchdog is started but we cannot control it,

drivers: stm32_iwdg: check for error on clk_enable during probe

Check for the error returned by clk_enable() during the driver's
probe.
While there, if watchdog is started but we cannot control it,
trigger panic instead of return error. This also avoids adding
useless clk_disable() in the error exit path.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: add get_timeleft watchdog handler

Implement .get_timeleft() watchdog operation handler for non-secure
world to query the watchdog device state. System time is logged at each
wat

drivers: stm32_iwdg: add get_timeleft watchdog handler

Implement .get_timeleft() watchdog operation handler for non-secure
world to query the watchdog device state. System time is logged at each
watchdog refresh to estimate time remaining before the watchdog elapses.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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