drivers: stm32_iwdg: fix timeout configuration

Fix test on watchdog refresh command success used to program the
watchdog timeout.

Fixes: 0bdd7f5ba821 ("drivers: stm32_iwdg: implementation of indepe

drivers: stm32_iwdg: fix timeout configuration

Fix test on watchdog refresh command success used to program the
watchdog timeout.

Fixes: 0bdd7f5ba821 ("drivers: stm32_iwdg: implementation of independent watchdog")
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: Add stm32mp1 remoteproc driver

This driver is responsible for configuring the registers and memories of
the remote processor.
- It stores information about memories assigned to the remote p

drivers: Add stm32mp1 remoteproc driver

This driver is responsible for configuring the registers and memories of
the remote processor.
- It stores information about memories assigned to the remote processor
based on the device tree.
- It ensures consistency between the registered memory and the addresses
of the firmware segments to be loaded.
- Additionally, it is responsible for starting and stopping the remote
processor core.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: caam: provide plat_rng_init if CFG_WITH_SOFTWARE_PRNG=y

With CFG_NXP_CAAM_RNG_DRV enabled, OP-TEE will use the CAAM
to generate random numbers. Normal world access to the RNG is still
possi

drivers: caam: provide plat_rng_init if CFG_WITH_SOFTWARE_PRNG=y

With CFG_NXP_CAAM_RNG_DRV enabled, OP-TEE will use the CAAM
to generate random numbers. Normal world access to the RNG is still
possible as the CAAM is TrustZone aware and provides multiple separate
job rings.

For complete isolation, however, access to CAAM reset and clocks need to
be managed as well. This could be done in theory by restricting access
to the reset and clock controller peripherals to the secure world and
exporting limited access to some resources via SCMI. There is no such
support yet for the i.MX and thus some setups may prefer to avoid using
the CAAM in OP-TEE to stay safe from normal world inducing glitches.

These setups may still need random numbers in OP-TEE. Therefore, access
so have them
access the CAAM only once at startup to initialize OP-TEE's PRNG and
defer subsequent use of the CAAM to the normal world, whenever
CFG_WITH_SOFTWARE_PRNG=y.

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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drivers: caam: rng: enable prediction resistance if possible

OP-TEE sets the PR bit on shared descriptors since commit 4ff2ce818e56
("drivers: caam: instantiate RNG state handle with prediction resi

drivers: caam: rng: enable prediction resistance if possible

OP-TEE sets the PR bit on shared descriptors since commit 4ff2ce818e56
("drivers: caam: instantiate RNG state handle with prediction resistance"),
but did not make use of it for random number generation with the reason
explained inside the commit message:

Note: current patch does not deal with RNG state handles that have
already been initialized, but without PR support (this could happen if
U-boot would run before OP-TEE etc.). In this case, RNG state handle
would have to be deinstantiated first, and then reinstantiated with
PR support.

There is a simpler workaround than deinstantiation however: Check if the
state handles have been initialized with prediction resistance (whether
from OP-TEE or outside) and if they were, just set the prediction
resistance bit.

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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drivers: caam: support querying whether prediction resistance was setup

CAAM shared descriptors initialization may happen inside OP-TEE or
beforehand, either in the bootloader or system controller.

drivers: caam: support querying whether prediction resistance was setup

CAAM shared descriptors initialization may happen inside OP-TEE or
beforehand, either in the bootloader or system controller.

As it's not known at compile-time whether the shared descriptors were
initialized with prediction resistance or not, OP-TEE use of the CAAM
for random number generation omitted requesting prediction resistance.

In preparation for changing that, provide a caam_hal_rng_pr_enabled()
function that queries the state of the PR bits in the shared descriptors.

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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driver: crypto: hisilicon: fix an issue of multiple tasks using the same qp

Flag in the qp structure is used to indicate whether
the qp is occupied.The new task can find an unused qp
and use it.

Fi

driver: crypto: hisilicon: fix an issue of multiple tasks using the same qp

Flag in the qp structure is used to indicate whether
the qp is occupied.The new task can find an unused qp
and use it.

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) module")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: remove unused deprecated gic_cpu_init()

Remove the unused deprecated function gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.

core: remove unused deprecated gic_cpu_init()

Remove the unused deprecated function gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: caam: update return type of caam_sm_free()

Update return type of caam_sm_free() from TEE_Result
to enum caam_status.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jer

drivers: caam: update return type of caam_sm_free()

Update return type of caam_sm_free() from TEE_Result
to enum caam_status.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

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drivers: regulator: supported voltage consider levels bounds

Assert regulator_supported_voltages() provides a list that takes into
account the min/max voltage levels possibly set from the secure DT.

drivers: regulator: supported voltage consider levels bounds

Assert regulator_supported_voltages() provides a list that takes into
account the min/max voltage levels possibly set from the secure DT.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: stm32_vrefbuf: set voltage list at init

Change stm32_vrefbuf driver to set the supported voltage levels list
at driver initialization rather than at first list query.

Acked-by:

drivers: regulator: stm32_vrefbuf: set voltage list at init

Change stm32_vrefbuf driver to set the supported voltage levels list
at driver initialization rather than at first list query.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: allow GIC version 1

Before this patch with CFG_ARM_GICV3=n the GIC driver asserted that the
detected GIC version is 2. This is stricter than necessary and breaks
some older platforms so a

core: gic: allow GIC version 1

Before this patch with CFG_ARM_GICV3=n the GIC driver asserted that the
detected GIC version is 2. This is stricter than necessary and breaks
some older platforms so allow version 1 also.

Fixes: 69171bec89ce ("core: gic: check gic version")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Tested-by: Andrew Davis <afd@ti.com>

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core: gic: make GICR base optional

The physical address of the redistributor was, before this patch, always
used, regardless of whether affinity routing is enabled or otherwise not
needed.

Using th

core: gic: make GICR base optional

The physical address of the redistributor was, before this patch, always
used, regardless of whether affinity routing is enabled or otherwise not
needed.

Using the redistributor is optional if gic_init_donate_sgi_to_ns() isn't
called. So allow the GICR base address to be passed as zero if
gic_init_donate_sgi_to_ns() isn't called. However,
gic_init_donate_sgi_to_ns() will panic if called without a previously
configured GICR base address.

Fixes: 05089e5f9a56 ("core: gic: use redistributor CPU interface")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: fix variable sized voltages fallback

Fix build issue reported by Clang on variable size field desc
not being located at the end of struct voltages_fallback. The
error was reporte

drivers: regulator: fix variable sized voltages fallback

Fix build issue reported by Clang on variable size field desc
not being located at the end of struct voltages_fallback. The
error was reported with a trace message like below:

core/include/drivers/regulator.h:118:4: warning: field 'voltages_fallback' with variable sized type 'struct voltages_fallback' not at the end of a struct or class is a GNU extension [-Wgnu-variable-sized-type-not-at-end]
} voltages_fallback;
^
core/drivers/regulator/regulator_fixed.c:27:19: warning: field 'regulator' with variable sized type 'struct regulator' not at the end of a struct or class is a GNU extension [-Wgnu-variable-sized-type-not-at-end]
struct regulator regulator;
^
2 warnings generated.

To achieve this the variable size field entries is removed from
struct regulator_voltages that is renamed struct regulator_voltages_desc.
API function regulator_supported_voltages() and regulator drivers handler
function ::supported_voltages are updated the get 2 input arguments the
second being the levels arrays which size is defined by the description
argument.

Impacted sources files are updated accordingly.

Fixes: 43c155ba111d ("drivers: regulator: list supported levels")
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: hisilicon: fix QM cache start and done define

Address offset of qm_cache_wb_start and qm_cache_wb_done
is wrong.

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management

drivers: crypto: hisilicon: fix QM cache start and done define

Address offset of qm_cache_wb_start and qm_cache_wb_done
is wrong.

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) module")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
[Edit commit subject]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: print clock tree with debug trace level

Change clk_print_tree() to print the clock tree with debug trace
level instead of info trace level.

Add a test on TRACE_LEVEL >= TRACE_DEBUG in

drivers: clk: print clock tree with debug trace level

Change clk_print_tree() to print the clock tree with debug trace
level instead of info trace level.

Add a test on TRACE_LEVEL >= TRACE_DEBUG in clk_print_tree()
to ensures no unless code is embedded when the trace level is too low.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: remove spinlock in clk_print_tree()

Remove spinlock handling from clk_print_tree(). This lock may mask
interrupts for a long period of time which and may affect the system
behavior. Si

drivers: clk: remove spinlock in clk_print_tree()

Remove spinlock handling from clk_print_tree(). This lock may mask
interrupts for a long period of time which and may affect the system
behavior. Since there is no clock unregistering and clock destroying
function, all clock references used are safe to use, even outside
the locked state. Whether or not printed information is accurate is
not an issue as clk_print_tree() is concerned as the function is only
informative.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: print tree without recursion

Remove recursive calls used in clk_print_tree() implementation using
list parsing algorithm to prevent uncontrolled stack overflows.

Print "-- No register

drivers: clk: print tree without recursion

Remove recursive calls used in clk_print_tree() implementation using
list parsing algorithm to prevent uncontrolled stack overflows.

Print "-- No registered clock" instead of nothing after
"Clock tree summary" trace message when there are no registered clocks.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Co-developed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: assert registered clock pointer is not NULL

Fix clk_register() assertion entry instruction to print an assertion
error message on NULL clock pointer instead of issuing a segmentation
f

drivers: clk: assert registered clock pointer is not NULL

Fix clk_register() assertion entry instruction to print an assertion
error message on NULL clock pointer instead of issuing a segmentation
fault.

Fixes: 2305544b3b9b ("drivers: clk: add generic clock framework")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: change queue from STAILQ to SLIST

Replace registered clock list from a STAILQ queue to a SLIST queue
that is enough for our purpose.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro

drivers: clk: change queue from STAILQ to SLIST

Replace registered clock list from a STAILQ queue to a SLIST queue
that is enough for our purpose.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: add gic_init_donate_sgi_to_ns()

Adds gic_init_donate_sgi_to_ns() which changes a secure SGI to become
non-secure.

Secure world currently has a few SGIs to spare while normal world
typica

core: gic: add gic_init_donate_sgi_to_ns()

Adds gic_init_donate_sgi_to_ns() which changes a secure SGI to become
non-secure.

Secure world currently has a few SGIs to spare while normal world
typically have reserved each of the non-secure SGIs for different
purposes.

In case another non-secure SGI is needed secure world can donate one of
its unused SGIs. This configuration will then deviate from the standard
GIC configuration where SGI ID0-ID7 are non-secure and ID8-ID15 are
secure.

Platforms using gic_init_donate_sgi_to_ns() should also use
gic_init_per_cpu() instead of the deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: deprecate gic_cpu_init()

Deprecates gic_cpu_init() in favor of the new function
gic_init_per_cpu(). gic_cpu_init() is only supposed to be called by
secondary CPUs in non-TF-A configurations w

core: deprecate gic_cpu_init()

Deprecates gic_cpu_init() in favor of the new function
gic_init_per_cpu(). gic_cpu_init() is only supposed to be called by
secondary CPUs in non-TF-A configurations while gic_init_per_cpu()
should be called by all secondary CPUs. gic_init_per_cpu() itself takes
CFG_WITH_ARM_TRUSTED_FW into account instead of having each platform
doing that.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: use redistributor CPU interface

GICv3 has a redistributor CPU interface that until now hasn't been used.
To prepare for coming patches that need to access the redistributor
initialize a l

core: gic: use redistributor CPU interface

GICv3 has a redistributor CPU interface that until now hasn't been used.
To prepare for coming patches that need to access the redistributor
initialize a list with each CPU specific redistributor address. A new
function gic_init_v3() is added with a parameter for the redistributor
base address.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: check gic version

Adds a check to see that the version of the GIC matches the expected
version.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <e

core: gic: check gic version

Adds a check to see that the version of the GIC matches the expected
version.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: print regulator tree summary

Changes implementation of regulator_print_state() to better show
the regulator tree hierarchy and renames the function to
regulator_print_tree().

Th

drivers: regulator: print regulator tree summary

Changes implementation of regulator_print_state() to better show
the regulator tree hierarchy and renames the function to
regulator_print_tree().

The function now depends on CFG_DRIVERS_REGULATOR_PRINT_TREE
being enabled.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Co-developed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: fix getting GPIO for level control

Swap the 2 calls to find gpio property in "regulator-gpio" compatible
node. The call that expects to get a TEE_ERROR_ITEM_NOT_FOUND return
valu

drivers: regulator: fix getting GPIO for level control

Swap the 2 calls to find gpio property in "regulator-gpio" compatible
node. The call that expects to get a TEE_ERROR_ITEM_NOT_FOUND return
value (as described in the inline comment) for an unsupported 2nd level
control GPIO can fail with TEE_ERROR_DEFER_DRIVER_INIT return value
when the 1st GPIO phandle listed in the 'gpios' DT node property relates
to a GPIO driver that is not yet probed. Fix that by first getting the
required GPIO control level and then testing presence of other GPIO
phandle in the 'gpios' DT property.

Fixes: f164f0f83420 ("drivers: regulator: GPIO controlled regulator")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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