drivers: stm32_rng: ensure conditional reset sequence is done

Add a check on RNG_CR_CONDRST being cleared before continuing the
program to ensure that the conditional reset sequence is done.

Signed

drivers: stm32_rng: ensure conditional reset sequence is done

Add a check on RNG_CR_CONDRST being cleared before continuing the
program to ensure that the conditional reset sequence is done.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: fix comment in stm32_rng_pm_resume()

Fix comment about the application of the RNG configuration in
stm32_rng_pm_resume(). Old comment mentioned reserved bits.

Signed-off-by: Gat

drivers: stm32_rng: fix comment in stm32_rng_pm_resume()

Fix comment about the application of the RNG configuration in
stm32_rng_pm_resume(). Old comment mentioned reserved bits.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: remove __unused attribute

Removes a useless __unused attribute for stm32_rng_probe() argument.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etie

drivers: stm32_rng: remove __unused attribute

Removes a useless __unused attribute for stm32_rng_probe() argument.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: check clock enable call

Fixes clock enable request that does not check the return value.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Ca

drivers: stm32_rng: check clock enable call

Fixes clock enable request that does not check the return value.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: plic: Fix parameter type of plic_op_raise_sgi()

The commit ec740b9fe95e ("core: interrupt_raise_sgi() updates") changes
the cpu_mask parameter to a uint32_t. Apply this change onto
plic_op_

drivers: plic: Fix parameter type of plic_op_raise_sgi()

The commit ec740b9fe95e ("core: interrupt_raise_sgi() updates") changes
the cpu_mask parameter to a uint32_t. Apply this change onto
plic_op_raise_sgi().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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driver: crypto: hisilicon: Add the mailbox operation lock

refactor function of mailbox operation to ensure atomaticity

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) modul

driver: crypto: hisilicon: Add the mailbox operation lock

refactor function of mailbox operation to ensure atomaticity

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) module")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_gpio: add secure configuration for GPIOs

This change adds security support for GPIOS. A bank of GPIO now has a
secure support and configuration.

Secure support is defined in the devi

drivers: stm32_gpio: add secure configuration for GPIOs

This change adds security support for GPIOS. A bank of GPIO now has a
secure support and configuration.

Secure support is defined in the device tree. If a GPIO bank is defined
as secure, the secure configuration is read through st,protreg device
tree property and is applied during probe.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: fix coding style issues

Prefer U(x) in definition of macros for unsigned ints.

Signed-off-by: Gatien Chevallier <gatien.chevallier@st.com>
Reviewed-by: Etienne Carriere <etienn

drivers: stm32_gpio: fix coding style issues

Prefer U(x) in definition of macros for unsigned ints.

Signed-off-by: Gatien Chevallier <gatien.chevallier@st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: fix iteration in set_bank_gpio_non_secure()

The for loop iterates over one too many elements.

Fixes: be53ee7b15f6 ("plat-stm32mp1: fix default setting GPIO as non-secure")
Sign

drivers: stm32_gpio: fix iteration in set_bank_gpio_non_secure()

The for loop iterates over one too many elements.

Fixes: be53ee7b15f6 ("plat-stm32mp1: fix default setting GPIO as non-secure")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_iwdg: enable state helper functions

Add iwdg_wdt_set_enabled() to register the watchdog is activated
and rename is_enable() to iwdg_wdt_is_enabled() for consistency.

Acked-by: Jerome

drivers: stm32_iwdg: enable state helper functions

Add iwdg_wdt_set_enabled() to register the watchdog is activated
and rename is_enable() to iwdg_wdt_is_enabled() for consistency.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_iwdg: enable bus clock once for all

Enable STM32 IWDG driver bus clock together with the IWDG kernel
clock when the driver is initialized. This clock is needed to propagate
IWDG early

drivers: stm32_iwdg: enable bus clock once for all

Enable STM32 IWDG driver bus clock together with the IWDG kernel
clock when the driver is initialized. This clock is needed to propagate
IWDG early interrupt to the system.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>

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drivers: stm32_iwdg: rename bus clock to clk_pclk

Rename STM32 IWDG watchdog bus clock clk_pclk, matching the reference
manual naming instead of clock.

Acked-by: Jerome Forissier <jerome.forissier@

drivers: stm32_iwdg: rename bus clock to clk_pclk

Rename STM32 IWDG watchdog bus clock clk_pclk, matching the reference
manual naming instead of clock.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_iwdg: remove stm32_iwdg_refresh()

Remove unused stm32_iwdg_refresh() intended to refresh all registered
watchdog devices.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Rev

drivers: stm32_iwdg: remove stm32_iwdg_refresh()

Remove unused stm32_iwdg_refresh() intended to refresh all registered
watchdog devices.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_iwdg: provide timeout range

Implement watchdog service init handler that is needed by U-Boot
to get min/max timeout range.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Re

drivers: stm32_iwdg: provide timeout range

Implement watchdog service init handler that is needed by U-Boot
to get min/max timeout range.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>

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drivers: stm32_iwdg: fix timeout configuration

Fix test on watchdog refresh command success used to program the
watchdog timeout.

Fixes: 0bdd7f5ba821 ("drivers: stm32_iwdg: implementation of indepe

drivers: stm32_iwdg: fix timeout configuration

Fix test on watchdog refresh command success used to program the
watchdog timeout.

Fixes: 0bdd7f5ba821 ("drivers: stm32_iwdg: implementation of independent watchdog")
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: Add stm32mp1 remoteproc driver

This driver is responsible for configuring the registers and memories of
the remote processor.
- It stores information about memories assigned to the remote p

drivers: Add stm32mp1 remoteproc driver

This driver is responsible for configuring the registers and memories of
the remote processor.
- It stores information about memories assigned to the remote processor
based on the device tree.
- It ensures consistency between the registered memory and the addresses
of the firmware segments to be loaded.
- Additionally, it is responsible for starting and stopping the remote
processor core.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: caam: provide plat_rng_init if CFG_WITH_SOFTWARE_PRNG=y

With CFG_NXP_CAAM_RNG_DRV enabled, OP-TEE will use the CAAM
to generate random numbers. Normal world access to the RNG is still
possi

drivers: caam: provide plat_rng_init if CFG_WITH_SOFTWARE_PRNG=y

With CFG_NXP_CAAM_RNG_DRV enabled, OP-TEE will use the CAAM
to generate random numbers. Normal world access to the RNG is still
possible as the CAAM is TrustZone aware and provides multiple separate
job rings.

For complete isolation, however, access to CAAM reset and clocks need to
be managed as well. This could be done in theory by restricting access
to the reset and clock controller peripherals to the secure world and
exporting limited access to some resources via SCMI. There is no such
support yet for the i.MX and thus some setups may prefer to avoid using
the CAAM in OP-TEE to stay safe from normal world inducing glitches.

These setups may still need random numbers in OP-TEE. Therefore, access
so have them
access the CAAM only once at startup to initialize OP-TEE's PRNG and
defer subsequent use of the CAAM to the normal world, whenever
CFG_WITH_SOFTWARE_PRNG=y.

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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drivers: caam: rng: enable prediction resistance if possible

OP-TEE sets the PR bit on shared descriptors since commit 4ff2ce818e56
("drivers: caam: instantiate RNG state handle with prediction resi

drivers: caam: rng: enable prediction resistance if possible

OP-TEE sets the PR bit on shared descriptors since commit 4ff2ce818e56
("drivers: caam: instantiate RNG state handle with prediction resistance"),
but did not make use of it for random number generation with the reason
explained inside the commit message:

Note: current patch does not deal with RNG state handles that have
already been initialized, but without PR support (this could happen if
U-boot would run before OP-TEE etc.). In this case, RNG state handle
would have to be deinstantiated first, and then reinstantiated with
PR support.

There is a simpler workaround than deinstantiation however: Check if the
state handles have been initialized with prediction resistance (whether
from OP-TEE or outside) and if they were, just set the prediction
resistance bit.

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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drivers: caam: support querying whether prediction resistance was setup

CAAM shared descriptors initialization may happen inside OP-TEE or
beforehand, either in the bootloader or system controller.

drivers: caam: support querying whether prediction resistance was setup

CAAM shared descriptors initialization may happen inside OP-TEE or
beforehand, either in the bootloader or system controller.

As it's not known at compile-time whether the shared descriptors were
initialized with prediction resistance or not, OP-TEE use of the CAAM
for random number generation omitted requesting prediction resistance.

In preparation for changing that, provide a caam_hal_rng_pr_enabled()
function that queries the state of the PR bits in the shared descriptors.

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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driver: crypto: hisilicon: fix an issue of multiple tasks using the same qp

Flag in the qp structure is used to indicate whether
the qp is occupied.The new task can find an unused qp
and use it.

Fi

driver: crypto: hisilicon: fix an issue of multiple tasks using the same qp

Flag in the qp structure is used to indicate whether
the qp is occupied.The new task can find an unused qp
and use it.

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) module")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: remove unused deprecated gic_cpu_init()

Remove the unused deprecated function gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.

core: remove unused deprecated gic_cpu_init()

Remove the unused deprecated function gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: caam: update return type of caam_sm_free()

Update return type of caam_sm_free() from TEE_Result
to enum caam_status.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jer

drivers: caam: update return type of caam_sm_free()

Update return type of caam_sm_free() from TEE_Result
to enum caam_status.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

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drivers: regulator: supported voltage consider levels bounds

Assert regulator_supported_voltages() provides a list that takes into
account the min/max voltage levels possibly set from the secure DT.

drivers: regulator: supported voltage consider levels bounds

Assert regulator_supported_voltages() provides a list that takes into
account the min/max voltage levels possibly set from the secure DT.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: stm32_vrefbuf: set voltage list at init

Change stm32_vrefbuf driver to set the supported voltage levels list
at driver initialization rather than at first list query.

Acked-by:

drivers: regulator: stm32_vrefbuf: set voltage list at init

Change stm32_vrefbuf driver to set the supported voltage levels list
at driver initialization rather than at first list query.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: allow GIC version 1

Before this patch with CFG_ARM_GICV3=n the GIC driver asserted that the
detected GIC version is 2. This is stricter than necessary and breaks
some older platforms so a

core: gic: allow GIC version 1

Before this patch with CFG_ARM_GICV3=n the GIC driver asserted that the
detected GIC version is 2. This is stricter than necessary and breaks
some older platforms so allow version 1 also.

Fixes: 69171bec89ce ("core: gic: check gic version")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Tested-by: Andrew Davis <afd@ti.com>

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