History log of /optee_os/core/drivers/ (Results 801 – 825 of 1354)
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b676071202-Mar-2022 Clement Faure <clement.faure@nxp.com>

drivers: imx: dcp: workaround DCP errata 051292

The internal boot ROM should reset the DCP controller prior jumping to
bootloader execution. The current boot ROM implementation does not
assert a DCP

drivers: imx: dcp: workaround DCP errata 051292

The internal boot ROM should reset the DCP controller prior jumping to
bootloader execution. The current boot ROM implementation does not
assert a DCP reset.

To mitigate the issue, users can implement a DCP reset by setting
SFTRST[31] and CTRL_CLKGATE[30] bits in the DCP_CTRL_SET registers.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Ricardo Salveti <ricardo@foundries.io> (imx-mx6ullevk)

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bcf9ecad31-May-2022 Franck LENORMAND <franck.lenormand@nxp.com>

drivers: imx_snvs: re-work security state for imx8m platforms

The current implementation of snvs_get_security_cfg() for
imx8m platforms includes the read of SYS_SECURE_BOOT bit.
This fourth bit show

drivers: imx_snvs: re-work security state for imx8m platforms

The current implementation of snvs_get_security_cfg() for
imx8m platforms includes the read of SYS_SECURE_BOOT bit.
This fourth bit shows if the board boots from internal
ROM. This bit will reset to 1 for a board in the field
and 0 for a test chip.

The read of this bit is out of scope of the snvs_get_security_cfg()
purpose which is to return the system security configuration.
The SYS_SECURE_BOOT bit (msb) can be discarded.

Fixes: 5cd93c5a75 (drivers: imx_snvs: fix SNVS security configuration values)
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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1e1e5a4d07-Jun-2022 Gatien Chevallier <gatien.chevallier@foss.st.com>

drivers: stm32_shared_io: introduce shared io driver

This commit implements shared registers support, previously handled in
core/arch/arm/plat-stm32mp1/shared_resources.c, at platform level.

Defaul

drivers: stm32_shared_io: introduce shared io driver

This commit implements shared registers support, previously handled in
core/arch/arm/plat-stm32mp1/shared_resources.c, at platform level.

Default enable CFG_STM32_SHARED_IO.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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868937ee30-May-2022 Clement Faure <clement.faure@nxp.com>

drivers: caam: map the CAAM registers with the CAAM_SIZE value

Add the CAAM register MMU mapping with the appropriate size CAAM_SIZE.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by:

drivers: caam: map the CAAM registers with the CAAM_SIZE value

Add the CAAM register MMU mapping with the appropriate size CAAM_SIZE.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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37010ab707-Jun-2022 Gatien Chevallier <gatien.chevallier@foss.st.com>

plat-stm32mp1: use helper header file stm32mp_dt_bindings.h

Changes plat-stm32mp1 and its drivers to rely on stm32mp_dt_bindings.h
which simplifies support of both variants STM32MP15 and STM32MP13 t

plat-stm32mp1: use helper header file stm32mp_dt_bindings.h

Changes plat-stm32mp1 and its drivers to rely on stm32mp_dt_bindings.h
which simplifies support of both variants STM32MP15 and STM32MP13 that
will use each specific DT bindings.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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/optee_os/core/arch/arm/plat-stm32mp1/conf.mk
/optee_os/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_syscfg.c
/optee_os/core/arch/arm/plat-stm32mp1/main.c
/optee_os/core/arch/arm/plat-stm32mp1/pm/psci.c
/optee_os/core/arch/arm/plat-stm32mp1/scmi_server.c
/optee_os/core/arch/arm/plat-stm32mp1/shared_resources.c
/optee_os/core/arch/riscv/include/kernel/secure_partition.h
/optee_os/core/arch/riscv/include/kernel/stmm_sp.h
/optee_os/core/arch/riscv/include/kernel/tlb_helpers.h
/optee_os/core/arch/riscv/include/mm/generic_ram_layout.h
/optee_os/core/arch/riscv/kernel/link.mk
/optee_os/core/arch/riscv/kernel/spinlock.S
/optee_os/core/arch/riscv/kernel/sub.mk
/optee_os/core/arch/riscv/plat-spike/conf.mk
/optee_os/core/arch/riscv/plat-spike/drivers/htif.c
/optee_os/core/arch/riscv/plat-spike/drivers/htif.h
/optee_os/core/arch/riscv/plat-spike/drivers/sub.mk
/optee_os/core/arch/riscv/plat-spike/kern.ld.S
/optee_os/core/arch/riscv/plat-spike/main.c
/optee_os/core/arch/riscv/plat-spike/platform_config.h
/optee_os/core/arch/riscv/plat-spike/sub.mk
/optee_os/core/arch/riscv/riscv.mk
clk/clk-stm32mp15.c
/optee_os/core/include/drivers/stm32mp_dt_bindings.h
/optee_os/core/include/io.h
/optee_os/core/include/mm/vm.h
/optee_os/core/kernel/dt_driver.c
/optee_os/core/mm/vm.c
/optee_os/core/pta/scmi.c
/optee_os/ldelf/ta_elf_rel.c
/optee_os/lib/libutils/ext/arch/riscv/sub.mk
/optee_os/lib/libutils/isoc/arch/riscv/sub.mk
/optee_os/lib/libutils/isoc/include/string.h
/optee_os/lib/libutils/isoc/newlib/strtok_r.c
/optee_os/lib/libutils/isoc/newlib/sub.mk
d0d36df616-Jun-2022 Ludvig Pärsson <ludvig.parsson@axis.com>

drivers: scmi-msg: Fix parameter type

In order to make clock.c and voltage_domain.c compile on
64 bit architecture, we cannot use unsigned int in the
function prototype and size_t in the function de

drivers: scmi-msg: Fix parameter type

In order to make clock.c and voltage_domain.c compile on
64 bit architecture, we cannot use unsigned int in the
function prototype and size_t in the function definition.

Signed-off-by: Ludvig Pärsson <ludvig.parsson@axis.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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488c73c008-Jun-2022 Gatien Chevallier <gatien.chevallier@foss.st.com>

drivers: clk: remove stm32_clock_*() helpers

Removes function that were deprecated: stm32_clock_is_enabled(),
stm32_clock_enable(), stm32_clock_disable() and stm32_clock_get_rate().

Signed-off-by:

drivers: clk: remove stm32_clock_*() helpers

Removes function that were deprecated: stm32_clock_is_enabled(),
stm32_clock_enable(), stm32_clock_disable() and stm32_clock_get_rate().

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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b97479cb08-Jun-2022 Jorge Ramirez-Ortiz <jorge@foundries.io>

drivers: se050: scp: add support for more boards

Add the board specific persistent keys required to stablish the SCP03
sessions with the secure element.

See https://www.nxp.com/docs/en/application-

drivers: se050: scp: add support for more boards

Add the board specific persistent keys required to stablish the SCP03
sessions with the secure element.

See https://www.nxp.com/docs/en/application-note/AN12436.pdf

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dc0db86308-Jun-2022 Clément Léger <clement.leger@bootlin.com>

drivers: pm: sam: clarify that the pm_suspend.S file was relicensed

Clarify that this file was imported from Linux and relicensed to avoid
any licensing issue.

Acked-by: Nicolas Ferre <nicolas.ferr

drivers: pm: sam: clarify that the pm_suspend.S file was relicensed

Clarify that this file was imported from Linux and relicensed to avoid
any licensing issue.

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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0347e53f17-May-2022 Etienne Carriere <etienne.carriere@linaro.org>

drivers: smccc_trng: get entropy from secure monitor

Implements random noise generation interface from Arm SMCCC TRNG
specification. Configuration switch CFG_ARM_SMCCC_TRNG must be enabled
to embed

drivers: smccc_trng: get entropy from secure monitor

Implements random noise generation interface from Arm SMCCC TRNG
specification. Configuration switch CFG_ARM_SMCCC_TRNG must be enabled
to embed the RNG driver that use this interface.

When CFG_ARM_SMCCC_TRNG is enable and CFG_WITH_SOFTWARE_PRNG is
disable, use SMCCC TRNG driver as entropy source. When
both CFG_ARM_SMCCC_TRNG and CFG_WITH_SOFTWARE_PRNG are enable, seed
OP-TEE PRNG with 32byte of TRNG entropy.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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d922c31423-Jun-2021 Clément Léger <clement.leger@bootlin.com>

plat-sam: add timer clock driver

Add support for the TCB block that are present on the samad2. This
series add support for the TCB as a time source and register it using
REGISTER_TIME_SOURCE(). More

plat-sam: add timer clock driver

Add support for the TCB block that are present on the samad2. This
series add support for the TCB as a time source and register it using
REGISTER_TIME_SOURCE(). Moreover, on Linux, the tick is done using the
TCB since the sama5d2 does not have the ARM architected timers. Since
the time source used for the tick clocksource is probed early in the
boot process, the SCMI clock support which uses a platform driver is
not yet probed and thus the TCB can't be probe properly. To workaround
that problem, this driver enables the TCB clocks and the Linux
device-tree is modified to use "fixed-clock" clock instead of the TCB
SCMI ones.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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1fe98f8211-Jan-2022 Clément Léger <clement.leger@bootlin.com>

drivers: atmel_piobu: add driver

Add piobu driver which handle secumod GPIOs. This driver also handle
tampering interrupts on GPIOs which are configured as input with the
device-tree. For instance,

drivers: atmel_piobu: add driver

Add piobu driver which handle secumod GPIOs. This driver also handle
tampering interrupts on GPIOs which are configured as input with the
device-tree. For instance, the following device-tree excerpt allows to
set an input as an intrusion detection pin:

gpios = <0 PIOBU_PIN_INPUT(1, 1, PIOBU_PIN_PULL_DOWN,
PIOBU_PIN_DEF_LEVEL_LOW, PIOBU_PIN_WAKEUP_ENABLE)>;

In case of a tamper event, the source of the tampering will be
displayed.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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b2e4b77e29-Apr-2022 Clément Léger <clement.leger@bootlin.com>

drivers: atmel_rtc: add atmel_rtc_get_tamper_timestamp()

The sama5d2 RTC actually hold the timestamp of the last tampering
attempt. Add a function to get the last time of tampering detection.

Acked

drivers: atmel_rtc: add atmel_rtc_get_tamper_timestamp()

The sama5d2 RTC actually hold the timestamp of the last tampering
attempt. Add a function to get the last time of tampering detection.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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74c676be30-Jan-2022 Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>

drivers: xiphera_trng: Add support for XIP8001B TRNG

Adds support for Xiphera's XIP8001B true random number generator.

XIP8001B is a FPGA IP core that can be synthesized in FPGA devices to
provide

drivers: xiphera_trng: Add support for XIP8001B TRNG

Adds support for Xiphera's XIP8001B true random number generator.

XIP8001B is a FPGA IP core that can be synthesized in FPGA devices to
provide TRNG source for device where it is missing like Xilinx Zynq-7000
and Xilinx Zynq MPSoC.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Co-developed-by: Atte Tommiska <atte.tommiska@xiphera.com>
Signed-off-by: Atte Tommiska <atte.tommiska@xiphera.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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332dec4a23-May-2022 Franck LENORMAND <franck.lenormand@nxp.com>

drivers: imx_snvs: fix the is_otpmk_valid() logic

The logic wanted was the inverse of the one implemented.

Fixes: ea4f7ad67d ("drivers: imx_snvs: add master key selection")
Signed-off-by: Franck LE

drivers: imx_snvs: fix the is_otpmk_valid() logic

The logic wanted was the inverse of the one implemented.

Fixes: ea4f7ad67d ("drivers: imx_snvs: add master key selection")
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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de2fcd3423-May-2022 Franck LENORMAND <franck.lenormand@nxp.com>

drivers: imx_snvs: fix SNVS register read operation

A coding mistake in the precedence order of C operators is causing
an incorrect read of the SNVS register. This error would return a wrong
board l

drivers: imx_snvs: fix SNVS register read operation

A coding mistake in the precedence order of C operators is causing
an incorrect read of the SNVS register. This error would return a wrong
board lifecycle state by snvs_get_security_cfg().

Fixes: 5cd93c5a ("drivers: imx_snvs: fix SNVS security configuration values")
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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916cc52a29-Apr-2022 Etienne Carriere <etienne.carriere@linaro.org>

drivers: scmi-msg: add SCMI MSG message protocol

Implements MSG header protocol to handle SCMI messages. MSG header
protocol was introduced in Linux kernel v5.15 [1]. It relies on normal
cached shar

drivers: scmi-msg: add SCMI MSG message protocol

Implements MSG header protocol to handle SCMI messages. MSG header
protocol was introduced in Linux kernel v5.15 [1]. It relies on normal
cached shared memory buffer using a 32bit header followed by the SCMI
message payload.

To support this message interface, the SCMI PTA defines a new capability
and a new command. Capability PTA_SCMI_CAPS_MSG_HEADER allows client and
service to negotiate the desired transport configuration. Command
PTA_SCMI_CMD_PROCESS_MSG_CHANNEL allows client to request processing
of a message sent based on that message exchange protocol.

Platforms shall enable configuration switch CFG_SCMI_MSG_SHM_MSG to have
their SCMI service supporting that communication protocol.

Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f301bba0ca7392d16a6ea4f1d264a91f1fadea1a
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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4814157822-Mar-2022 Clement Faure <clement.faure@nxp.com>

drivers: imx_snvs: use snvs_is_device_closed() for RPMB key status

Call the function snvs_is_device_closed() to know if the platform is
closed or not in plat_rpmb_key_is_ready() instead of reading t

drivers: imx_snvs: use snvs_is_device_closed() for RPMB key status

Call the function snvs_is_device_closed() to know if the platform is
closed or not in plat_rpmb_key_is_ready() instead of reading the
platform security configuration.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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8dafb56815-Mar-2022 Clement Faure <clement.faure@nxp.com>

drivers: caam: set OTP as master key

Before the CAAM initialization, set the OTP as the SNVS master key
if the device is in closed state.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-

drivers: caam: set OTP as master key

Before the CAAM initialization, set the OTP as the SNVS master key
if the device is in closed state.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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ec93a5a202-Mar-2022 Clement Faure <clement.faure@nxp.com>

drivers: imx_snvs: fix SNVS_SSM_MODE_SECURE value

The value for SNVS_SSM_MODE_SECURE is 15 instead of 14.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.for

drivers: imx_snvs: fix SNVS_SSM_MODE_SECURE value

The value for SNVS_SSM_MODE_SECURE is 15 instead of 14.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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5cd93c5a02-Mar-2022 Clement Faure <clement.faure@nxp.com>

drivers: imx_snvs: fix SNVS security configuration values

The SYS_SECURITY_CFG field values of the HPSR register are different on
imx8m platforms. Also, this bit field is 4 bits wide on imx8m platfo

drivers: imx_snvs: fix SNVS security configuration values

The SYS_SECURITY_CFG field values of the HPSR register are different on
imx8m platforms. Also, this bit field is 4 bits wide on imx8m platforms
and 3 bits wide on the imx6/7 platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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ea4f7ad601-Mar-2022 Clement Faure <clement.faure@nxp.com>

drivers: imx_snvs: add master key selection

Select the OTPMK as the SNVS master key when the platforms is in closed
state.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Fori

drivers: imx_snvs: add master key selection

Select the OTPMK as the SNVS master key when the platforms is in closed
state.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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916e56ed28-Feb-2022 Clement Faure <clement.faure@nxp.com>

core: drivers: merge i.MX SNVS driver files

Move the implementation of plat_rpmb_key_is_ready() from
plat-imx/drivers/imx_snvs.c to drivers/imx_snvs.c

Signed-off-by: Clement Faure <clement.faure@nx

core: drivers: merge i.MX SNVS driver files

Move the implementation of plat_rpmb_key_is_ready() from
plat-imx/drivers/imx_snvs.c to drivers/imx_snvs.c

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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737ed93212-May-2022 Etienne Carriere <etienne.carriere@linaro.org>

drivers: scmi-msg: fix protocol list querying

Corrects the function reporting the SCMI protocols supported by the
platform to not assume 8 protocol IDs at most can be returned. Indeed
the number of

drivers: scmi-msg: fix protocol list querying

Corrects the function reporting the SCMI protocols supported by the
platform to not assume 8 protocol IDs at most can be returned. Indeed
the number of protocol IDs returned depends on the SCMI output buffer
size.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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f93760c412-May-2022 Etienne Carriere <etienne.carriere@linaro.org>

drivers: scmi-msg: fix protocol list response size

Corrects the size of the SCMI response payload when querying the list
of the supported protocol. This response payload size depends on the
number o

drivers: scmi-msg: fix protocol list response size

Corrects the size of the SCMI response payload when querying the list
of the supported protocol. This response payload size depends on the
number of protocols enumerated by the response.

Reported-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/lkml/1698297.NAKyZzlH2u@archbook
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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