rng: rename plat_rng_init() to plat_init_soft_prng()

plat_rng_init() has a misleading name as it could be seen as a function
which initializes the hardware RNG. It's job is to seed the software RNG

rng: rename plat_rng_init() to plat_init_soft_prng()

plat_rng_init() has a misleading name as it could be seen as a function
which initializes the hardware RNG. It's job is to seed the software RNG
though, so rename it to plat_init_soft_prng() and clarify the function
description to avoid confusion.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Acked-by: Jerome Forissier <jerome.forissier@arm.com>

show more ...

rng: only call plat_rng_init() with CFG_WITH_SOFTWARE_PRNG

OP-TEE can generate random numbers either using a hardware RNG or a
software RNG. In the latter case OP-TEE can only generate secure random

rng: only call plat_rng_init() with CFG_WITH_SOFTWARE_PRNG

OP-TEE can generate random numbers either using a hardware RNG or a
software RNG. In the latter case OP-TEE can only generate secure random
numbers when the software RNG is seeded by a hardware RNG.

Seeding the software RNG is done with plat_rng_init(). Many SoCs assume
their implementation is hardware RNG only, so they don't need seeding
the software RNG and provide an empty plat_rng_init() just because the
function is mandatory.

This has the result that if someone decides to use the software RNG on
one of these SoCs by enabling CFG_WITH_SOFTWARE_PRNG, he will end up
with an unseeded software RNG.

Prevent that by calling plat_rng_init() only when CFG_WITH_SOFTWARE_PRNG
is enabled and remove all empty plat_rng_init() implementations. That
way compiling with CFG_WITH_SOFTWARE_PRNG will result in a linker error
unless CFG_INSECURE is enabled as well, in which case the weak default
implementation is used.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Acked-by: Jerome Forissier <jerome.forissier@arm.com>

show more ...

clk: qcom: move PAS clock group to its own compilation unit

PAS clock configuration is conditionally compiled and platform-specific;
keeping it in the same file as the core clock setup adds unnecess

clk: qcom: move PAS clock group to its own compilation unit

PAS clock configuration is conditionally compiled and platform-specific;
keeping it in the same file as the core clock setup adds unnecessary
coupling and complicates maintenance.

No functional change.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

show more ...

pta: qcom_pas: Add support for ADSP

Add Peripheral Authentication Service (PAS) support for the
Audio DSP (ADSP), enabling loading of the ADSP firmware image.

Authentication not done yet.

Initial

pta: qcom_pas: Add support for ADSP

Add Peripheral Authentication Service (PAS) support for the
Audio DSP (ADSP), enabling loading of the ADSP firmware image.

Authentication not done yet.

Initial validation used https://github.com/qualcomm/fastrpc.git
(all tests pass)

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

show more ...

pta: qcom_pas: Add support for CDSP

Add Peripheral Authentication Service (PAS) support for the
Compute DSP (CDSP), enabling loading of the CDSP firmware image.

Authentication not done yet.

Initia

pta: qcom_pas: Add support for CDSP

Add Peripheral Authentication Service (PAS) support for the
Compute DSP (CDSP), enabling loading of the CDSP firmware image.

Authentication not done yet.

Initial validation used https://github.com/qualcomm/fastrpc.git
(all tests pass)

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

show more ...

plat: qcom: kodiak: move clock definitions to platform header

Move Kodiak-specific GCC clock register offsets out of the generic
clock-qcom driver into a platform header.

Introduce clock_group_qcom

plat: qcom: kodiak: move clock definitions to platform header

Move Kodiak-specific GCC clock register offsets out of the generic
clock-qcom driver into a platform header.

Introduce clock_group_qcom.h under platform/kodiak to hold the clock
register offsets required by the driver and update the build system so
the platform include path is visible to the clock driver.

Also move the GCC MMIO mapping from plat-qcom/main.c into the clock
driver. This keeps the mapping local to the driver that consumes the
registers and avoids exposing platform clock registers globally during
platform initialization.

This change is a preparation step to support additional Qualcomm
platforms while keeping the common clock driver platform-agnostic.

No functional change intended.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

show more ...

clk: Add initial clock framework for Qualcomm platforms

Add clock framework for Qualcomm platforms. Currently the support is
added for clocks related to WPSS subsystem on Kodiak SoC.

Co-developed-b

clk: Add initial clock framework for Qualcomm platforms

Add clock framework for Qualcomm platforms. Currently the support is
added for clocks related to WPSS subsystem on Kodiak SoC.

Co-developed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.rammirez@oss.qualcomm.com>

show more ...

drivers: versal_net: Add OCP driver

On Versal NET devices (only) PLM Firmware has a module called XilOCP,
providing services related to the Open Compute Project (OCP) security
standards (PCR handlin

drivers: versal_net: Add OCP driver

On Versal NET devices (only) PLM Firmware has a module called XilOCP,
providing services related to the Open Compute Project (OCP) security
standards (PCR handling, Device Management Endorsement, Attestation).

This commit adds functions which are more or less equivalent to the XilOCP
client side API offers.

Since most Versal and Versal NET drivers more or less re-implement rather
similar handling of struct versal_ipi_cmd, this commit also adds and hereby
proposes a new set of helper functions for commonly used operations on
struct versal_ipi_cmd. With these versal_ipi_cmd_*() functions data
words ("Values") and "IPI buffers" can easily be "pushed" onto a struct
versal_ipi_cmd.

For now, only this OCP driver makes use of these versal_ipi_cmd_*()
functions. Thus they have been placed directly in versal_ocp.c instead of
having them located in a separate drivers/ file, like
drivers/versal_ipi_cmd.c [1].

Link: https://github.com/OP-TEE/optee_os/pull/7726#issuecomment-4237954478 [1]
Signed-off-by: Dennis Ries <dennis.ries@missinglinkelectronics.com>
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: trng: Fix continuous random generation sequence

Don't toggle CTRL::PRNGSTART if not needed, as this can have undesired side
effects on the hardware and its produced data. CTRL:

drivers: versal_net: trng: Fix continuous random generation sequence

Don't toggle CTRL::PRNGSTART if not needed, as this can have undesired side
effects on the hardware and its produced data. CTRL::PRNGMODE does not
need resetting either.

Derived from a not yet unpublished AMD/Xilinx embeddedsw patch.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: trng: Add support for newer PKI TRNG and use in PKI driver

The TRNG IP Core included in Versal NET PKI Accelerator is close to Versal
PMC TRNG IP Core but includes hardware DF a

drivers: versal_net: trng: Add support for newer PKI TRNG and use in PKI driver

The TRNG IP Core included in Versal NET PKI Accelerator is close to Versal
PMC TRNG IP Core but includes hardware DF and can be called a 2nd version
of that IP Core.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com> and
huynhdanvo <dan.vo@provenrun.com>.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: trng: Add support for TRNG via PLM Firmware

In contrast to Versal, the PMC TRNG IP is driven by the PLM Firmware
exclusively, since the latter is also using it.

Largely based o

drivers: versal_net: trng: Add support for TRNG via PLM Firmware

In contrast to Versal, the PMC TRNG IP is driven by the PLM Firmware
exclusively, since the latter is also using it.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

plat-versal: Add support for Versal NET variant

Versal NET is a new SoC flavor based on the Versal architecture.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

plat-versal: Add support for Versal NET variant

Versal NET is a new SoC flavor based on the Versal architecture.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: pki: Enhance status and error checking; be verbose if needed

Mapping all PKI Engine status bits to TEE_ERROR_GENERIC is not suitable in
all cases. Especially SIGNATURENOTVALID s

drivers: versal_net: pki: Enhance status and error checking; be verbose if needed

Mapping all PKI Engine status bits to TEE_ERROR_GENERIC is not suitable in
all cases. Especially SIGNATURENOTVALID shall be mapped to
TEE_ERROR_SIGNATURE_INVALID. TEE_AsymmetricVerifyDigest() requires this to
work properly.

Moreover, this commit tries to introduce reasonable reporting of errors and
unexpected values, in case something goes wrong.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: pki: Fix queue alignment and DMA setup

The DMA part of the PKI Accelerator seems to support up to 4 equally sized
buffers to fetch requests and data from, and to return data to

drivers: versal_net: pki: Fix queue alignment and DMA setup

The DMA part of the PKI Accelerator seems to support up to 4 equally sized
buffers to fetch requests and data from, and to return data to
(RequestQueue). Such a buffer, also primarily called a "page", needs to be
aligned to a certain boundary which is NOT the cache line length!

Experiments showed that natural alignment does work. Thus, since the driver
uses a fixed size of 4 KiB (PKI_QUEUE_BUF_SIZE) for these "pages", we
enforce alignment to 4 KiB. It remains unknown whether smaller (but bigger
than cache line length) alignments do work or not.

Furthermore the DMA setup assumed a "page" size of 64 KiB, defined by the
very misleading symbol PKI_RQ_CFG_PAGE_SIZE_1024 with value 0x10, which
represents ln2(64KiB). In concert with this, the offset to write data back
to (5th descriptor word), also assumed the size of 64 KiB of a page. Since
only 4 KiB "pages" have been allocated in the first place, this setup is
rather dangerous, since the PKI Accelerator is under the impression that
the actual page size is bigger.
So, this commit makes the code consistent by using 4 KiB as "page" size in
all relevant places.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: pki: Add driver for Versal NET PKI Accelerator

The Versal NET variant comes with a dedicated PKI engine. This driver makes
use of the engine for ECDSA P-256, P-384, and P-521 si

drivers: versal_net: pki: Add driver for Versal NET PKI Accelerator

The Versal NET variant comes with a dedicated PKI engine. This driver makes
use of the engine for ECDSA P-256, P-384, and P-521 sign, verify and key
generation operations.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

For now, this commit omits the previous work's direct (memory-mapped) use
of one of the dedicated TRNG instances within the PKI Accelerator. Support
for it is to be added later. Instead the regular system random number
generator is used (=> crypto_rng_read()).

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal: ecc: Separate code using PLM firmware into its own file

In preparation for introducing a driver for Versal NET's PKI Accelerator
block.

Largely based on previous work by
Jeremie Co

drivers: versal: ecc: Separate code using PLM firmware into its own file

In preparation for introducing a driver for Versal NET's PKI Accelerator
block.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: puf: Add support for Versal NET

In case of Versal NET, structure XPuf_DataAddr in module XilPuf has the
additional u32 member RoSwapVal. Since PLM firmware release v2022.2 [1].

drivers: versal_net: puf: Add support for Versal NET

In case of Versal NET, structure XPuf_DataAddr in module XilPuf has the
additional u32 member RoSwapVal. Since PLM firmware release v2022.2 [1].

Link: https://github.com/Xilinx/embeddedsw/commit/943aa4479aad [1]
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: nvm: Add support for Versal NET

The XilNvm API has heavily changed between Versal and Versal NET.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.c

drivers: versal_net: nvm: Add support for Versal NET

The XilNvm API has heavily changed between Versal and Versal NET.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

In contrast to the previous work, this commit does NOT change the in-kernel
API (versal_nvm.h) regarding functions versal_efuse_read_revoke_id() and
versal_efuse_read_offchip_revoke_id(). These functions reflect what can be
found in the "client" side API of XilNvm for Versal _and_ Versal NET
(release v2025.1). There is no difference between the two platform flavors.

However, regarding function versal_efuse_write_offchip_ids(), corresponding
XilNvm "client" side API is indeed different between Versal and Versal
NET. To keep the API towards OP-TEE OS unchanged, the Versal NET version
translates the argument of type struct versal_efuse_offchip_ids into a
single OffChip Revoke Id eFuse bit number. Writing multiple eFuse bits is
not supported.

Moreover, generally use variable names "low" and "hi" instead of "a" and
"b" when handling 64 bit PLM Firmware API id parameters.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Dennis Ries <dennis.ries@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: nvm: Duplicate Versal driver for Versal NET

The XilNvm API has heavily changed between Versal and Versal NET.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelect

drivers: versal_net: nvm: Duplicate Versal driver for Versal NET

The XilNvm API has heavily changed between Versal and Versal NET.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: rsa: Add support for flavor-specific command RSA_PRIVATE_DECRYPT

In PLM Firmware release v2024.2 module XilSecure introduced a Versal NET
specific variant of API id 0x503 (RSA_P

drivers: versal_net: rsa: Add support for flavor-specific command RSA_PRIVATE_DECRYPT

In PLM Firmware release v2024.2 module XilSecure introduced a Versal NET
specific variant of API id 0x503 (RSA_PRIVATE_DECRYPT). In contrast to
Versal, XilSecure's XSecure_RsaInParam::KeyAddr is pointing to the
structure XSecure_RsaKeyParam instead of directly pointing to the buffer
comprising exponent and modulus. XSecure_RsaKeyParam has separate members
to point to exponent and modulus.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: aes: No alignment restrictions for payload on update

Like Versal ACAP, Versal NET platform does not allow zero-length payloads
due to limitations in the XilSecure DMA driver. Ho

drivers: versal_net: aes: No alignment restrictions for payload on update

Like Versal ACAP, Versal NET platform does not allow zero-length payloads
due to limitations in the XilSecure DMA driver. However, in contrast to
Versal ACAP, there are no additional alignment rules in effect.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: pm: Add Versal NET SiP UUID

By definition in Versal NET support for ARM Trusted Firmware, the SiP UUID
is different than the one used by Versal.

Signed-off-by: Joachim Foerster

drivers: versal_net: pm: Add Versal NET SiP UUID

By definition in Versal NET support for ARM Trusted Firmware, the SiP UUID
is different than the one used by Versal.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal: mbox: Rework

- Offer a generic IPI/Mailbox API in versal_mbox.c and ...
- ... provide the default IPI channel to the PMC for other drivers in
versal_pmc.c .

- Improve performance

drivers: versal: mbox: Rework

- Offer a generic IPI/Mailbox API in versal_mbox.c and ...
- ... provide the default IPI channel to the PMC for other drivers in
versal_pmc.c .

- Improve performance by doing notification by direct, memory-mapped
register access instead of doing it through the SecureMonitor.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal: mbox: Enhance buffer allocation

- Allow versal_mbox_alloc() to fail and properly handle this at all call
sites.

- Introduce versal_mbox_free() next to _alloc().

Largely based on

drivers: versal: mbox: Enhance buffer allocation

- Allow versal_mbox_alloc() to fail and properly handle this at all call
sites.

- Introduce versal_mbox_free() next to _alloc().

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

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drivers: versal: aes: Fix check for payload length on update

PLM Firmware does not allow zero-length payloads due to limitations in the
XilSecure DMA driver. Additionally further alignment rules are

drivers: versal: aes: Fix check for payload length on update

PLM Firmware does not allow zero-length payloads due to limitations in the
XilSecure DMA driver. Additionally further alignment rules are in effect,
depending on a regular update or a final update.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...