caam: fix compilation when CFG_NXP_CAAM_AE_* are disabled

Similarly to other CAAM modules, define empty function if CAAM AE is
not used, to avoid undefined reference to caam_ae_init().

Signed-off-b

caam: fix compilation when CFG_NXP_CAAM_AE_* are disabled

Similarly to other CAAM modules, define empty function if CAAM AE is
not used, to avoid undefined reference to caam_ae_init().

Signed-off-by: Pavel Löbl <pavel@loebl.cz>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_iwdg: check for error on clk_enable during probe

Check for the error returned by clk_enable() during the driver's
probe.
While there, if watchdog is started but we cannot control it,

drivers: stm32_iwdg: check for error on clk_enable during probe

Check for the error returned by clk_enable() during the driver's
probe.
While there, if watchdog is started but we cannot control it,
trigger panic instead of return error. This also avoids adding
useless clk_disable() in the error exit path.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: add get_timeleft watchdog handler

Implement .get_timeleft() watchdog operation handler for non-secure
world to query the watchdog device state. System time is logged at each
wat

drivers: stm32_iwdg: add get_timeleft watchdog handler

Implement .get_timeleft() watchdog operation handler for non-secure
world to query the watchdog device state. System time is logged at each
watchdog refresh to estimate time remaining before the watchdog elapses.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: wdt: add implementation of SMCWD_GET_TIMELEFT

Implement watchdog SMC service SMCWD_GET_TIMELEFT that is optional
and allows non-secure world to get information on watchdog state.
The servic

drivers: wdt: add implementation of SMCWD_GET_TIMELEFT

Implement watchdog SMC service SMCWD_GET_TIMELEFT that is optional
and allows non-secure world to get information on watchdog state.
The service is supported by new watchdog driver operation handler
get_timeleft.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: remove OTP access in driver

Now we know if the watchdog is running by reading the hardware,
there is no need to read the OTP fuses related to the watchdog.
This allows removing

drivers: stm32_iwdg: remove OTP access in driver

Now we know if the watchdog is running by reading the hardware,
there is no need to read the OTP fuses related to the watchdog.
This allows removing platform function stm32_get_iwdg_otp_config()
and consequently stm32_iwdg.h header file.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: probe if watchdog is running

Read from the hardware whether watchdog is already running when
core initializes. Relax timeout from 1 to 10ms to let the
watchdog warm-up when enab

drivers: stm32_iwdg: probe if watchdog is running

Read from the hardware whether watchdog is already running when
core initializes. Relax timeout from 1 to 10ms to let the
watchdog warm-up when enabled.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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crypto: stm32: fix stm32_saes CTR mode on small input buffers

Fix missing cast when saving pre-computed masks in STM32 SAES driver
CTR implementation when several small input data is provided to
the

crypto: stm32: fix stm32_saes CTR mode on small input buffers

Fix missing cast when saving pre-computed masks in STM32 SAES driver
CTR implementation when several small input data is provided to
the update handler.

The issue is revealed by xtest regression_4017 when run with at least
level 12, e.g. "xtest -l 15 regression_4017".

Fixes: 4320f5cf30c5 ("crypto: stm32: SAES cipher support")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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crypto: stm32: fix stm32_cryp CTR mode on small input buffers

Fix missing cast when saving pre-computed masks in STM32 CRYP driver
CTR implementation when several small input data is provided to
the

crypto: stm32: fix stm32_cryp CTR mode on small input buffers

Fix missing cast when saving pre-computed masks in STM32 CRYP driver
CTR implementation when several small input data is provided to
the update handler.

The issue could be found, for example, by assigning STM32 CRYP to OP-TEE
in stm32mp1-157C_DK2 board DTS file (patch below) and running xtest
regression_4017 with level 15 ("xtest -l 15 regression_4017").

Example of a patch on stm32mp157c-dk2.dts file to use CRYP driver for
AES operations:
+&cryp1 { status = "okay"; };
+
&etzpc {
st,decprot =
(...)
- <DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>,
+ <DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_S_RW, DECPROT_UNLOCK)>,
(...)
}

Fixes: 5e64ae6796b7 ("crypto: stm32: use CRYP IP for CIPHER algorithms")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: sam: fix getting interrupts from DT

The issue is found on sama5d2 platform.
Get interrupt fails due to the change of function parameter (from
count by bytes to count by words), fixed by mak

drivers: sam: fix getting interrupts from DT

The issue is found on sama5d2 platform.
Get interrupt fails due to the change of function parameter (from
count by bytes to count by words), fixed by making corresponding
changes to the function called later.

Fixes: 63873401cb04 ("core: interrupt: fix property count in dt_get_irq_type_prio()")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: stm32_rifsc: remove semaphore acquisition when applying the conf

Remove the semaphore acquisition when applying the configuration
so that they are taken, if necessary, during the firewall b

drivers: stm32_rifsc: remove semaphore acquisition when applying the conf

Remove the semaphore acquisition when applying the configuration
so that they are taken, if necessary, during the firewall bus probe.
This avoids semaphores from being taken by OP-TEE when the peripheral
isn't used.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: imx_csu: add SA settings for i.MX6ULL

Add the CSU SA settings for i.MX6ULL. The i.MX6ULL implements the same
non-Trustzone aware masters as the i.MX6UL, so the same settings can be
used. Th

drivers: imx_csu: add SA settings for i.MX6ULL

Add the CSU SA settings for i.MX6ULL. The i.MX6ULL implements the same
non-Trustzone aware masters as the i.MX6UL, so the same settings can be
used. This setting ensures that no non-TrustZone aware master is able
to read secure memory. Information on the CSU SA register values were
taken from i.MX6ULL Security Reference Manual rev 0.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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core: drivers: support SiFive UART

Add sifive uart support.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zo

core: drivers: support SiFive UART

Add sifive uart support.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Acked-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: scmi-msg: support performance domains for DVFS

Implement some of the SCMI performance domain management messages
in scmi-msg drivers to support basic DVFS scenario.

Co-developed-by: Etienn

drivers: scmi-msg: support performance domains for DVFS

Implement some of the SCMI performance domain management messages
in scmi-msg drivers to support basic DVFS scenario.

Co-developed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_cpu_opp: skip OPP unsupported by SOC

Use device ID to remove not supported OPP.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@fos

drivers: stm32_cpu_opp: skip OPP unsupported by SOC

Use device ID to remove not supported OPP.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>

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drivers: stm32_cpu_opp: skip OPP with unsupported voltage

Remove operating points that could not be handled
by the regulator supplying the CPU.

Signed-off-by: Patrick Delaunay <patrick.delaunay@fos

drivers: stm32_cpu_opp: skip OPP with unsupported voltage

Remove operating points that could not be handled
by the regulator supplying the CPU.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: add stm32 CPU DVFS driver

drivers/cpu_opp.c implements dynamic voltage and frequency
scaling for the CPU.
It is used at boot time to set an higher operating point than
the one used to boot.

drivers: add stm32 CPU DVFS driver

drivers/cpu_opp.c implements dynamic voltage and frequency
scaling for the CPU.
It is used at boot time to set an higher operating point than
the one used to boot.
It will be used by the SCMI performance service.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: remove test on CFG_DRIVERS_GPIO

Remove test on CFG_DRIVERS_GPIO inside stm32_gpio.c C source file.
CFG_* dependencies are addressed in makefile file (e.g. plat-*/conf.mk),
not i

drivers: stm32_gpio: remove test on CFG_DRIVERS_GPIO

Remove test on CFG_DRIVERS_GPIO inside stm32_gpio.c C source file.
CFG_* dependencies are addressed in makefile file (e.g. plat-*/conf.mk),
not in the driver source file.

Fixes: 1001585e2e56 ("drivers: stm32_gpio: remove GPIO access specific API functions")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: clk: sam: select AUDIOPLL as the source for sama7g5 I2SMCC0 GCLK

Initialize the generic clock used by for sama7g5 I2SMCC0 peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked

drivers: clk: sam: select AUDIOPLL as the source for sama7g5 I2SMCC0 GCLK

Initialize the generic clock used by for sama7g5 I2SMCC0 peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: sam: fix underflow of the divider for sama7g5 PLL clocks

Fix the underflow of the divider calculated when clock given rate is
greater than the rate of the clock parent.

Fixes: 4318c69

drivers: clk: sam: fix underflow of the divider for sama7g5 PLL clocks

Fix the underflow of the divider calculated when clock given rate is
greater than the rate of the clock parent.

Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers

When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in
PMC_PLL_UPDT specifies which PLL fields are written/read. Set

drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers

When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in
PMC_PLL_UPDT specifies which PLL fields are written/read. Set correct ID
to PMC_PLL_UPDT to avoid operating on wrong PMC_PLL_CTRLx.

Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: initialize the clocks used by sama7g5 PDMC0

Initialize the audio PLL and generic clocks used by for sama7g5 PDMC0
peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Ack

drivers: clk: sam: initialize the clocks used by sama7g5 PDMC0

Initialize the audio PLL and generic clocks used by for sama7g5 PDMC0
peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: initialize the clock range values for sama7g5 SCMI clocks

Initialize the clock range values for sama7g5 clocks so that they can be
used in responding SCMI CLOCK_DESCRIBE_RATES com

drivers: clk: sam: initialize the clock range values for sama7g5 SCMI clocks

Initialize the clock range values for sama7g5 clocks so that they can be
used in responding SCMI CLOCK_DESCRIBE_RATES command.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: add clock range support for the clocks used by SCMI

Add clock range attribute to the struct for the clocks.
New function for initializing the clock range for the clocks.
Implement "plat_sc

plat-sam: add clock range support for the clocks used by SCMI

Add clock range attribute to the struct for the clocks.
New function for initializing the clock range for the clocks.
Implement "plat_scmi_clock_rates_by_step()" to be used by SCMI.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_remote_proc: fix definition of stm32_rproc_compat_data

Fix compilation error of core/drivers/remoteproc/stm32_remoteproc.c
Move bool ns_loading from "struct stm32_rproc_instance" to
"

drivers: stm32_remote_proc: fix definition of stm32_rproc_compat_data

Fix compilation error of core/drivers/remoteproc/stm32_remoteproc.c
Move bool ns_loading from "struct stm32_rproc_instance" to
"struct stm32_rproc_compat_data".

Fixes: a03044318866 ("drivers: stm32_remote_proc: add stm32_rproc_is_secure()")
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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crypto: stm32: use HASH IP for HASH and HMAC algorithm

Add HASH IP drivers, and add hooks in OP-TEE crypto framework to use
HASH IP to do HASH and HMAC process

Signed-off-by: Nicolas Toromanoff <ni

crypto: stm32: use HASH IP for HASH and HMAC algorithm

Add HASH IP drivers, and add hooks in OP-TEE crypto framework to use
HASH IP to do HASH and HMAC process

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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