1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, STMicroelectronics 4 * Copyright (c) 2021, Microchip 5 */ 6 7 #include <at91_clk.h> 8 #include <confine_array_index.h> 9 #include <drivers/atmel_rstc.h> 10 #include <drivers/rstctrl.h> 11 #include <drivers/scmi-msg.h> 12 #include <drivers/scmi.h> 13 #include <dt-bindings/clock/at91.h> 14 #include <initcall.h> 15 #include <tee_api_defines.h> 16 17 static_assert(SMT_BUF_SLOT_SIZE <= CFG_SCMI_SHMEM_SIZE); 18 19 register_phys_mem(MEM_AREA_IO_NSEC, CFG_SCMI_SHMEM_START, CFG_SCMI_SHMEM_SIZE); 20 21 #define RESET_CELL(_scmi_id, _id, _name) \ 22 [(_scmi_id)] = { \ 23 .reset_id = (_id), \ 24 .name = (_name), \ 25 } 26 27 #define RST_SCMI_USB1 0 28 #define RST_SCMI_USB2 1 29 #define RST_SCMI_USB3 2 30 31 struct sam_scmi_rd { 32 unsigned int reset_id; 33 const char *name; 34 struct rstctrl *rstctrl; 35 }; 36 37 static struct sam_scmi_rd sam_scmi_reset_domain[] = { 38 #ifdef CFG_SAMA7G5 39 RESET_CELL(RST_SCMI_USB1, SHIFT_U32(0xE4, RESET_ID_SHIFT) | 4, "USB1"), 40 RESET_CELL(RST_SCMI_USB2, SHIFT_U32(0xE4, RESET_ID_SHIFT) | 5, "USB2"), 41 RESET_CELL(RST_SCMI_USB3, SHIFT_U32(0xE4, RESET_ID_SHIFT) | 6, "USB3"), 42 #endif 43 }; 44 45 struct channel_resources { 46 struct scmi_msg_channel *channel; 47 struct sam_scmi_rd *rd; 48 size_t rd_count; 49 }; 50 51 static const struct channel_resources scmi_channel[] = { 52 [0] = { 53 .channel = &(struct scmi_msg_channel){ 54 .shm_addr = { .pa = CFG_SCMI_SHMEM_START }, 55 .shm_size = SMT_BUF_SLOT_SIZE, 56 }, 57 .rd = sam_scmi_reset_domain, 58 .rd_count = ARRAY_SIZE(sam_scmi_reset_domain), 59 }, 60 }; 61 62 static const struct channel_resources *find_resource(unsigned int channel_id) 63 { 64 assert(channel_id < ARRAY_SIZE(scmi_channel)); 65 66 return scmi_channel + channel_id; 67 } 68 69 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 70 { 71 const size_t max_id = ARRAY_SIZE(scmi_channel); 72 unsigned int confined_id = confine_array_index(channel_id, max_id); 73 74 if (channel_id >= max_id) 75 return NULL; 76 77 return find_resource(confined_id)->channel; 78 } 79 80 static const char vendor[] = "Microchip"; 81 static const char sub_vendor[] = ""; 82 83 const char *plat_scmi_vendor_name(void) 84 { 85 return vendor; 86 } 87 88 const char *plat_scmi_sub_vendor_name(void) 89 { 90 return sub_vendor; 91 } 92 93 /* Currently supporting only SCMI Base protocol */ 94 static const uint8_t plat_protocol_list[] = { 95 SCMI_PROTOCOL_ID_CLOCK, 96 SCMI_PROTOCOL_ID_RESET_DOMAIN, 97 0 /* Null termination */ 98 }; 99 100 size_t plat_scmi_protocol_count(void) 101 { 102 return ARRAY_SIZE(plat_protocol_list) - 1; 103 } 104 105 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 106 { 107 return plat_protocol_list; 108 } 109 110 struct sam_pmc_clk { 111 unsigned int scmi_id; 112 unsigned int pmc_type; 113 unsigned int pmc_id; 114 struct clk_range output_range; 115 }; 116 117 #ifdef CFG_SAMA7G5 118 static struct sam_pmc_clk pmc_clks[] = { 119 { 120 .scmi_id = AT91_SCMI_CLK_CORE_MCK, 121 .pmc_type = PMC_TYPE_CORE, 122 .pmc_id = PMC_MCK 123 }, 124 { 125 .scmi_id = AT91_SCMI_CLK_CORE_UTMI, 126 .pmc_type = PMC_TYPE_CORE, 127 .pmc_id = PMC_UTMI 128 }, 129 { 130 .scmi_id = AT91_SCMI_CLK_CORE_CPUPLLCK, 131 .pmc_type = PMC_TYPE_CORE, 132 .pmc_id = PMC_CPUPLL 133 }, 134 { 135 .scmi_id = AT91_SCMI_CLK_CORE_MAIN, 136 .pmc_type = PMC_TYPE_CORE, 137 .pmc_id = PMC_MAIN 138 }, 139 { 140 .scmi_id = AT91_SCMI_CLK_CORE_SYSPLLCK, 141 .pmc_type = PMC_TYPE_CORE, 142 .pmc_id = PMC_SYSPLL 143 }, 144 145 { 146 .scmi_id = AT91_SCMI_CLK_CORE_AUDIOPLLCK, 147 .pmc_type = PMC_TYPE_CORE, 148 .pmc_id = PMC_AUDIOPMCPLL 149 }, 150 151 { 152 .scmi_id = AT91_SCMI_CLK_CORE_MCK_PRES, 153 .pmc_type = PMC_TYPE_CORE, 154 .pmc_id = PMC_MCK_PRES 155 }, 156 { 157 .scmi_id = AT91_SCMI_CLK_CORE_DDRPLLCK, 158 .pmc_type = PMC_TYPE_CORE, 159 .pmc_id = PMC_DDRPLL 160 }, 161 { 162 .scmi_id = AT91_SCMI_CLK_CORE_IMGPLLCK, 163 .pmc_type = PMC_TYPE_CORE, 164 .pmc_id = PMC_IMGPLL 165 }, 166 { 167 .scmi_id = AT91_SCMI_CLK_CORE_ETHPLLCK, 168 .pmc_type = PMC_TYPE_CORE, 169 .pmc_id = PMC_ETHPLL 170 }, 171 { 172 .scmi_id = AT91_SCMI_CLK_UTMI1, 173 .pmc_type = PMC_TYPE_CORE, 174 .pmc_id = PMC_UTMI1 175 }, 176 { 177 .scmi_id = AT91_SCMI_CLK_UTMI2, 178 .pmc_type = PMC_TYPE_CORE, 179 .pmc_id = PMC_UTMI2 180 }, 181 { 182 .scmi_id = AT91_SCMI_CLK_UTMI3, 183 .pmc_type = PMC_TYPE_CORE, 184 .pmc_id = PMC_UTMI3 185 }, 186 { 187 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK0, 188 .pmc_type = PMC_TYPE_SYSTEM, 189 .pmc_id = 8 190 }, 191 { 192 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK1, 193 .pmc_type = PMC_TYPE_SYSTEM, 194 .pmc_id = 9 195 }, 196 { 197 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK2, 198 .pmc_type = PMC_TYPE_SYSTEM, 199 .pmc_id = 10 200 }, 201 { 202 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK3, 203 .pmc_type = PMC_TYPE_SYSTEM, 204 .pmc_id = 11 205 }, 206 { 207 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK4, 208 .pmc_type = PMC_TYPE_SYSTEM, 209 .pmc_id = 12 210 }, 211 { 212 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK5, 213 .pmc_type = PMC_TYPE_SYSTEM, 214 .pmc_id = 13 215 }, 216 { 217 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK6, 218 .pmc_type = PMC_TYPE_SYSTEM, 219 .pmc_id = 14 220 }, 221 { 222 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK7, 223 .pmc_type = PMC_TYPE_SYSTEM, 224 .pmc_id = 15 225 }, 226 { 227 .scmi_id = AT91_SCMI_CLK_PERIPH_ASRC_CLK, 228 .pmc_type = PMC_TYPE_PERIPHERAL, 229 .pmc_id = ID_ASRC 230 }, 231 { 232 .scmi_id = AT91_SCMI_CLK_GCK_ASRC_GCLK, 233 .pmc_type = PMC_TYPE_GCK, 234 .pmc_id = ID_ASRC 235 }, 236 { 237 .scmi_id = AT91_SCMI_CLK_PERIPH_CSI_CLK, 238 .pmc_type = PMC_TYPE_PERIPHERAL, 239 .pmc_id = ID_CSI 240 }, 241 { 242 .scmi_id = AT91_SCMI_CLK_GCK_CSI_GCLK, 243 .pmc_type = PMC_TYPE_GCK, 244 .pmc_id = ID_CSI 245 }, 246 { 247 .scmi_id = AT91_SCMI_CLK_PERIPH_CSI2DC_CLK, 248 .pmc_type = PMC_TYPE_PERIPHERAL, 249 .pmc_id = ID_CSI2DC 250 }, 251 { 252 .scmi_id = AT91_SCMI_CLK_PERIPH_MACB0_CLK, 253 .pmc_type = PMC_TYPE_PERIPHERAL, 254 .pmc_id = ID_GMAC0 255 }, 256 { 257 .scmi_id = AT91_SCMI_CLK_GCK_MACB0_GCLK, 258 .pmc_type = PMC_TYPE_GCK, 259 .pmc_id = ID_GMAC0 260 }, 261 { 262 .scmi_id = AT91_SCMI_CLK_GCK_MACB0_TSU, 263 .pmc_type = PMC_TYPE_GCK, 264 .pmc_id = ID_GMAC0_TSU 265 }, 266 { 267 .scmi_id = AT91_SCMI_CLK_PERIPH_MACB1_CLK, 268 .pmc_type = PMC_TYPE_PERIPHERAL, 269 .pmc_id = ID_GMAC1 270 }, 271 { 272 .scmi_id = AT91_SCMI_CLK_GCK_MACB1_GCLK, 273 .pmc_type = PMC_TYPE_GCK, 274 .pmc_id = ID_GMAC1 275 }, 276 { 277 .scmi_id = AT91_SCMI_CLK_GCK_MACB1_TSU, 278 .pmc_type = PMC_TYPE_GCK, 279 .pmc_id = ID_GMAC1_TSU 280 }, 281 { 282 .scmi_id = AT91_SCMI_CLK_PERIPH_TDES_CLK, 283 .pmc_type = PMC_TYPE_PERIPHERAL, 284 .pmc_id = ID_TDES 285 }, 286 { 287 .scmi_id = AT91_SCMI_CLK_PERIPH_HSMC_CLK, 288 .pmc_type = PMC_TYPE_PERIPHERAL, 289 .pmc_id = ID_HSMC 290 }, 291 { 292 .scmi_id = AT91_SCMI_CLK_PERIPH_PIOA_CLK, 293 .pmc_type = PMC_TYPE_PERIPHERAL, 294 .pmc_id = ID_PIOA 295 }, 296 { 297 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX0_CLK, 298 .pmc_type = PMC_TYPE_PERIPHERAL, 299 .pmc_id = ID_FLEXCOM0 300 }, 301 { 302 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX1_CLK, 303 .pmc_type = PMC_TYPE_PERIPHERAL, 304 .pmc_id = ID_FLEXCOM1 305 }, 306 { 307 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX2_CLK, 308 .pmc_type = PMC_TYPE_PERIPHERAL, 309 .pmc_id = ID_FLEXCOM2 310 }, 311 { 312 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX3_CLK, 313 .pmc_type = PMC_TYPE_PERIPHERAL, 314 .pmc_id = ID_FLEXCOM3 315 }, 316 { 317 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX4_CLK, 318 .pmc_type = PMC_TYPE_PERIPHERAL, 319 .pmc_id = ID_FLEXCOM4 320 }, 321 { 322 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX5_CLK, 323 .pmc_type = PMC_TYPE_PERIPHERAL, 324 .pmc_id = ID_FLEXCOM5 325 }, 326 { 327 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX6_CLK, 328 .pmc_type = PMC_TYPE_PERIPHERAL, 329 .pmc_id = ID_FLEXCOM6 330 }, 331 { 332 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX7_CLK, 333 .pmc_type = PMC_TYPE_PERIPHERAL, 334 .pmc_id = ID_FLEXCOM7 335 }, 336 { 337 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX8_CLK, 338 .pmc_type = PMC_TYPE_PERIPHERAL, 339 .pmc_id = ID_FLEXCOM8 340 }, 341 { 342 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX9_CLK, 343 .pmc_type = PMC_TYPE_PERIPHERAL, 344 .pmc_id = ID_FLEXCOM9 345 }, 346 { 347 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX10_CLK, 348 .pmc_type = PMC_TYPE_PERIPHERAL, 349 .pmc_id = ID_FLEXCOM10 350 }, 351 { 352 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX11_CLK, 353 .pmc_type = PMC_TYPE_PERIPHERAL, 354 .pmc_id = ID_FLEXCOM11 355 }, 356 { 357 .scmi_id = AT91_SCMI_CLK_PERIPH_TCB0_CLK, 358 .pmc_type = PMC_TYPE_PERIPHERAL, 359 .pmc_id = ID_TC0_CHANNEL0 360 }, 361 { 362 .scmi_id = AT91_SCMI_CLK_PERIPH_TCB1_CLK, 363 .pmc_type = PMC_TYPE_PERIPHERAL, 364 .pmc_id = ID_TC1_CHANNEL0 365 }, 366 { 367 .scmi_id = AT91_SCMI_CLK_PERIPH_PWM_CLK, 368 .pmc_type = PMC_TYPE_PERIPHERAL, 369 .pmc_id = ID_PWM 370 }, 371 { 372 .scmi_id = AT91_SCMI_CLK_GCK_ADC_GCLK, 373 .pmc_type = PMC_TYPE_GCK, 374 .pmc_id = ID_ADC 375 }, 376 { 377 .scmi_id = AT91_SCMI_CLK_PERIPH_UHPHS_CLK, 378 .pmc_type = PMC_TYPE_PERIPHERAL, 379 .pmc_id = ID_UHPHS 380 }, 381 { 382 .scmi_id = AT91_SCMI_CLK_PERIPH_UDPHSA_CLK, 383 .pmc_type = PMC_TYPE_PERIPHERAL, 384 .pmc_id = ID_UDPHSA 385 }, 386 { 387 .scmi_id = AT91_SCMI_CLK_PERIPH_UDPHSB_CLK, 388 .pmc_type = PMC_TYPE_PERIPHERAL, 389 .pmc_id = ID_UDPHSB 390 }, 391 { 392 .scmi_id = AT91_SCMI_CLK_PERIPH_SSC0_CLK, 393 .pmc_type = PMC_TYPE_PERIPHERAL, 394 .pmc_id = ID_SSC0 395 }, 396 { 397 .scmi_id = AT91_SCMI_CLK_PERIPH_SSC1_CLK, 398 .pmc_type = PMC_TYPE_PERIPHERAL, 399 .pmc_id = ID_SSC1 400 }, 401 { 402 .scmi_id = AT91_SCMI_CLK_PERIPH_TRNG_CLK, 403 .pmc_type = PMC_TYPE_PERIPHERAL, 404 .pmc_id = ID_TRNG 405 }, 406 { 407 .scmi_id = AT91_SCMI_CLK_PERIPH_PDMC0_CLK, 408 .pmc_type = PMC_TYPE_PERIPHERAL, 409 .pmc_id = ID_PDMC0 410 }, 411 { 412 .scmi_id = AT91_SCMI_CLK_PERIPH_PDMC1_CLK, 413 .pmc_type = PMC_TYPE_PERIPHERAL, 414 .pmc_id = ID_PDMC1 415 }, 416 { 417 .scmi_id = AT91_SCMI_CLK_PERIPH_SECURAM_CLK, 418 .pmc_type = PMC_TYPE_PERIPHERAL, 419 .pmc_id = ID_SECURAM 420 }, 421 { 422 .scmi_id = AT91_SCMI_CLK_PERIPH_I2S0_CLK, 423 .pmc_type = PMC_TYPE_PERIPHERAL, 424 .pmc_id = ID_I2SMCC0 425 }, 426 { 427 .scmi_id = AT91_SCMI_CLK_PERIPH_I2S1_CLK, 428 .pmc_type = PMC_TYPE_PERIPHERAL, 429 .pmc_id = ID_I2SMCC1 430 }, 431 { 432 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN0_CLK, 433 .pmc_type = PMC_TYPE_PERIPHERAL, 434 .pmc_id = ID_MCAN0 435 }, 436 { 437 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN1_CLK, 438 .pmc_type = PMC_TYPE_PERIPHERAL, 439 .pmc_id = ID_MCAN1 440 }, 441 { 442 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN2_CLK, 443 .pmc_type = PMC_TYPE_PERIPHERAL, 444 .pmc_id = ID_MCAN2 445 }, 446 { 447 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN3_CLK, 448 .pmc_type = PMC_TYPE_PERIPHERAL, 449 .pmc_id = ID_MCAN3 450 }, 451 { 452 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN4_CLK, 453 .pmc_type = PMC_TYPE_PERIPHERAL, 454 .pmc_id = ID_MCAN4 455 }, 456 { 457 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN5_CLK, 458 .pmc_type = PMC_TYPE_PERIPHERAL, 459 .pmc_id = ID_MCAN5 460 }, 461 { 462 .scmi_id = AT91_SCMI_CLK_PERIPH_DMA0_CLK, 463 .pmc_type = PMC_TYPE_PERIPHERAL, 464 .pmc_id = ID_XDMAC0 465 }, 466 { 467 .scmi_id = AT91_SCMI_CLK_PERIPH_DMA1_CLK, 468 .pmc_type = PMC_TYPE_PERIPHERAL, 469 .pmc_id = ID_XDMAC1 470 }, 471 { 472 .scmi_id = AT91_SCMI_CLK_PERIPH_DMA2_CLK, 473 .pmc_type = PMC_TYPE_PERIPHERAL, 474 .pmc_id = ID_XDMAC2 475 }, 476 { 477 .scmi_id = AT91_SCMI_CLK_PERIPH_SPDIFRX_CLK, 478 .pmc_type = PMC_TYPE_PERIPHERAL, 479 .pmc_id = ID_SPDIFRX 480 }, 481 { 482 .scmi_id = AT91_SCMI_CLK_PERIPH_SPDIFTX_CLK, 483 .pmc_type = PMC_TYPE_PERIPHERAL, 484 .pmc_id = ID_SPDIFTX 485 }, 486 { 487 .scmi_id = AT91_SCMI_CLK_GCK_SPDIFRX_GCLK, 488 .pmc_type = PMC_TYPE_GCK, 489 .pmc_id = ID_SPDIFRX 490 }, 491 { 492 .scmi_id = AT91_SCMI_CLK_GCK_SPDIFTX_GCLK, 493 .pmc_type = PMC_TYPE_GCK, 494 .pmc_id = ID_SPDIFTX 495 }, 496 { 497 .scmi_id = AT91_SCMI_CLK_PERIPH_AES_CLK, 498 .pmc_type = PMC_TYPE_PERIPHERAL, 499 .pmc_id = ID_AES 500 }, 501 { 502 .scmi_id = AT91_SCMI_CLK_PERIPH_AESB_CLK, 503 .pmc_type = PMC_TYPE_PERIPHERAL, 504 .pmc_id = ID_TZAESBASC 505 }, 506 { 507 .scmi_id = AT91_SCMI_CLK_PERIPH_SHA_CLK, 508 .pmc_type = PMC_TYPE_PERIPHERAL, 509 .pmc_id = ID_SHA 510 }, 511 { 512 .scmi_id = AT91_SCMI_CLK_PERIPH_SDMMC0_HCLK, 513 .pmc_type = PMC_TYPE_PERIPHERAL, 514 .pmc_id = ID_SDMMC0 515 }, 516 { 517 .scmi_id = AT91_SCMI_CLK_PERIPH_SDMMC1_HCLK, 518 .pmc_type = PMC_TYPE_PERIPHERAL, 519 .pmc_id = ID_SDMMC1 520 }, 521 { 522 .scmi_id = AT91_SCMI_CLK_PERIPH_SDMMC2_HCLK, 523 .pmc_type = PMC_TYPE_PERIPHERAL, 524 .pmc_id = ID_SDMMC2 525 }, 526 { 527 .scmi_id = AT91_SCMI_CLK_PERIPH_ISC_CLK, 528 .pmc_type = PMC_TYPE_PERIPHERAL, 529 .pmc_id = ID_ISC 530 }, 531 { 532 .scmi_id = AT91_SCMI_CLK_PERIPH_QSPI0_CLK, 533 .pmc_type = PMC_TYPE_PERIPHERAL, 534 .pmc_id = ID_QSPI0 535 }, 536 { 537 .scmi_id = AT91_SCMI_CLK_PERIPH_QSPI1_CLK, 538 .pmc_type = PMC_TYPE_PERIPHERAL, 539 .pmc_id = ID_QSPI1 540 }, 541 { 542 .scmi_id = AT91_SCMI_CLK_GCK_QSPI0_GCLK, 543 .pmc_type = PMC_TYPE_GCK, 544 .pmc_id = ID_QSPI0 545 }, 546 { 547 .scmi_id = AT91_SCMI_CLK_GCK_QSPI1_GCLK, 548 .pmc_type = PMC_TYPE_GCK, 549 .pmc_id = ID_QSPI1 550 }, 551 { 552 .scmi_id = AT91_SCMI_CLK_GCK_SDMMC0_GCLK, 553 .pmc_type = PMC_TYPE_GCK, 554 .pmc_id = ID_SDMMC0 555 }, 556 { 557 .scmi_id = AT91_SCMI_CLK_GCK_SDMMC1_GCLK, 558 .pmc_type = PMC_TYPE_GCK, 559 .pmc_id = ID_SDMMC1 560 }, 561 { 562 .scmi_id = AT91_SCMI_CLK_GCK_SDMMC2_GCLK, 563 .pmc_type = PMC_TYPE_GCK, 564 .pmc_id = ID_SDMMC2 565 }, 566 { 567 .scmi_id = AT91_SCMI_CLK_GCK_TCB0_GCLK, 568 .pmc_type = PMC_TYPE_GCK, 569 .pmc_id = ID_TC0_CHANNEL0 570 }, 571 { 572 .scmi_id = AT91_SCMI_CLK_GCK_TCB1_GCLK, 573 .pmc_type = PMC_TYPE_GCK, 574 .pmc_id = ID_TC1_CHANNEL0 575 }, 576 { 577 .scmi_id = AT91_SCMI_CLK_GCK_I2S0_GCLK, 578 .pmc_type = PMC_TYPE_GCK, 579 .pmc_id = ID_I2SMCC0 580 }, 581 { 582 .scmi_id = AT91_SCMI_CLK_GCK_I2S1_GCLK, 583 .pmc_type = PMC_TYPE_GCK, 584 .pmc_id = ID_I2SMCC1 585 }, 586 { 587 .scmi_id = AT91_SCMI_CLK_GCK_CAN0_GCLK, 588 .pmc_type = PMC_TYPE_GCK, 589 .pmc_id = ID_MCAN0 590 }, 591 { 592 .scmi_id = AT91_SCMI_CLK_GCK_CAN1_GCLK, 593 .pmc_type = PMC_TYPE_GCK, 594 .pmc_id = ID_MCAN1 595 }, 596 { 597 .scmi_id = AT91_SCMI_CLK_GCK_CAN2_GCLK, 598 .pmc_type = PMC_TYPE_GCK, 599 .pmc_id = ID_MCAN2 600 }, 601 { 602 .scmi_id = AT91_SCMI_CLK_GCK_CAN3_GCLK, 603 .pmc_type = PMC_TYPE_GCK, 604 .pmc_id = ID_MCAN3 605 }, 606 { 607 .scmi_id = AT91_SCMI_CLK_GCK_CAN4_GCLK, 608 .pmc_type = PMC_TYPE_GCK, 609 .pmc_id = ID_MCAN4 610 }, 611 { 612 .scmi_id = AT91_SCMI_CLK_GCK_CAN5_GCLK, 613 .pmc_type = PMC_TYPE_GCK, 614 .pmc_id = ID_MCAN5 615 }, 616 }; 617 #else 618 static struct sam_pmc_clk pmc_clks[] = { 619 { 620 .scmi_id = AT91_SCMI_CLK_CORE_MCK, 621 .pmc_type = PMC_TYPE_CORE, 622 .pmc_id = PMC_MCK 623 }, 624 { 625 .scmi_id = AT91_SCMI_CLK_CORE_UTMI, 626 .pmc_type = PMC_TYPE_CORE, 627 .pmc_id = PMC_UTMI 628 }, 629 { 630 .scmi_id = AT91_SCMI_CLK_CORE_MAIN, 631 .pmc_type = PMC_TYPE_CORE, 632 .pmc_id = PMC_MAIN 633 }, 634 { 635 .scmi_id = AT91_SCMI_CLK_CORE_MCK2, 636 .pmc_type = PMC_TYPE_CORE, 637 .pmc_id = PMC_MCK2 638 }, 639 { 640 .scmi_id = AT91_SCMI_CLK_CORE_I2S0_MUX, 641 .pmc_type = PMC_TYPE_CORE, 642 .pmc_id = PMC_I2S0_MUX 643 }, 644 { 645 .scmi_id = AT91_SCMI_CLK_CORE_I2S1_MUX, 646 .pmc_type = PMC_TYPE_CORE, 647 .pmc_id = PMC_I2S1_MUX 648 }, 649 { 650 .scmi_id = AT91_SCMI_CLK_CORE_PLLACK, 651 .pmc_type = PMC_TYPE_CORE, 652 .pmc_id = PMC_PLLACK 653 }, 654 { 655 .scmi_id = AT91_SCMI_CLK_CORE_AUDIOPLLCK, 656 .pmc_type = PMC_TYPE_CORE, 657 .pmc_id = PMC_AUDIOPLLCK 658 }, 659 { 660 .scmi_id = AT91_SCMI_CLK_CORE_MCK_PRES, 661 .pmc_type = PMC_TYPE_CORE, 662 .pmc_id = PMC_MCK_PRES 663 }, 664 { 665 .scmi_id = AT91_SCMI_CLK_SYSTEM_DDRCK, 666 .pmc_type = PMC_TYPE_SYSTEM, 667 .pmc_id = 2 668 }, 669 { 670 .scmi_id = AT91_SCMI_CLK_SYSTEM_LCDCK, 671 .pmc_type = PMC_TYPE_SYSTEM, 672 .pmc_id = 3 673 }, 674 { 675 .scmi_id = AT91_SCMI_CLK_SYSTEM_UHPCK, 676 .pmc_type = PMC_TYPE_SYSTEM, 677 .pmc_id = 6 678 }, 679 { 680 .scmi_id = AT91_SCMI_CLK_SYSTEM_UDPCK, 681 .pmc_type = PMC_TYPE_SYSTEM, 682 .pmc_id = 7 683 }, 684 { 685 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK0, 686 .pmc_type = PMC_TYPE_SYSTEM, 687 .pmc_id = 8 688 }, 689 { 690 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK1, 691 .pmc_type = PMC_TYPE_SYSTEM, 692 .pmc_id = 9 693 }, 694 { 695 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK2, 696 .pmc_type = PMC_TYPE_SYSTEM, 697 .pmc_id = 10 698 }, 699 { 700 .scmi_id = AT91_SCMI_CLK_SYSTEM_ISCCK, 701 .pmc_type = PMC_TYPE_SYSTEM, 702 .pmc_id = 18 703 }, 704 { 705 .scmi_id = AT91_SCMI_CLK_PERIPH_MACB0_CLK, 706 .pmc_type = PMC_TYPE_PERIPHERAL, 707 .pmc_id = 5 708 }, 709 { 710 .scmi_id = AT91_SCMI_CLK_PERIPH_TDES_CLK, 711 .pmc_type = PMC_TYPE_PERIPHERAL, 712 .pmc_id = 11 713 }, 714 { 715 .scmi_id = AT91_SCMI_CLK_PERIPH_MATRIX1_CLK, 716 .pmc_type = PMC_TYPE_PERIPHERAL, 717 .pmc_id = 14 718 }, 719 { 720 .scmi_id = AT91_SCMI_CLK_PERIPH_HSMC_CLK, 721 .pmc_type = PMC_TYPE_PERIPHERAL, 722 .pmc_id = 17 723 }, 724 { 725 .scmi_id = AT91_SCMI_CLK_PERIPH_PIOA_CLK, 726 .pmc_type = PMC_TYPE_PERIPHERAL, 727 .pmc_id = 18 728 }, 729 { 730 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX0_CLK, 731 .pmc_type = PMC_TYPE_PERIPHERAL, 732 .pmc_id = 19 733 }, 734 { 735 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX1_CLK, 736 .pmc_type = PMC_TYPE_PERIPHERAL, 737 .pmc_id = 20 738 }, 739 { 740 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX2_CLK, 741 .pmc_type = PMC_TYPE_PERIPHERAL, 742 .pmc_id = 21 743 }, 744 { 745 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX3_CLK, 746 .pmc_type = PMC_TYPE_PERIPHERAL, 747 .pmc_id = 22 748 }, 749 { 750 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX4_CLK, 751 .pmc_type = PMC_TYPE_PERIPHERAL, 752 .pmc_id = 23 753 }, 754 { 755 .scmi_id = AT91_SCMI_CLK_PERIPH_UART0_CLK, 756 .pmc_type = PMC_TYPE_PERIPHERAL, 757 .pmc_id = 24 758 }, 759 { 760 .scmi_id = AT91_SCMI_CLK_PERIPH_UART1_CLK, 761 .pmc_type = PMC_TYPE_PERIPHERAL, 762 .pmc_id = 25 763 }, 764 { 765 .scmi_id = AT91_SCMI_CLK_PERIPH_UART2_CLK, 766 .pmc_type = PMC_TYPE_PERIPHERAL, 767 .pmc_id = 26 768 }, 769 { 770 .scmi_id = AT91_SCMI_CLK_PERIPH_UART3_CLK, 771 .pmc_type = PMC_TYPE_PERIPHERAL, 772 .pmc_id = 27 773 }, 774 { 775 .scmi_id = AT91_SCMI_CLK_PERIPH_UART4_CLK, 776 .pmc_type = PMC_TYPE_PERIPHERAL, 777 .pmc_id = 28 778 }, 779 { 780 .scmi_id = AT91_SCMI_CLK_PERIPH_TWI0_CLK, 781 .pmc_type = PMC_TYPE_PERIPHERAL, 782 .pmc_id = 29 783 }, 784 { 785 .scmi_id = AT91_SCMI_CLK_PERIPH_TWI1_CLK, 786 .pmc_type = PMC_TYPE_PERIPHERAL, 787 .pmc_id = 30 788 }, 789 { 790 .scmi_id = AT91_SCMI_CLK_PERIPH_SPI0_CLK, 791 .pmc_type = PMC_TYPE_PERIPHERAL, 792 .pmc_id = 33 793 }, 794 { 795 .scmi_id = AT91_SCMI_CLK_PERIPH_SPI1_CLK, 796 .pmc_type = PMC_TYPE_PERIPHERAL, 797 .pmc_id = 34 798 }, 799 { 800 .scmi_id = AT91_SCMI_CLK_PERIPH_TCB0_CLK, 801 .pmc_type = PMC_TYPE_PERIPHERAL, 802 .pmc_id = 35 803 }, 804 { 805 .scmi_id = AT91_SCMI_CLK_PERIPH_TCB1_CLK, 806 .pmc_type = PMC_TYPE_PERIPHERAL, 807 .pmc_id = 36 808 }, 809 { 810 .scmi_id = AT91_SCMI_CLK_PERIPH_PWM_CLK, 811 .pmc_type = PMC_TYPE_PERIPHERAL, 812 .pmc_id = 38 813 }, 814 { 815 .scmi_id = AT91_SCMI_CLK_PERIPH_ADC_CLK, 816 .pmc_type = PMC_TYPE_PERIPHERAL, 817 .pmc_id = 40 818 }, 819 { 820 .scmi_id = AT91_SCMI_CLK_PERIPH_UHPHS_CLK, 821 .pmc_type = PMC_TYPE_PERIPHERAL, 822 .pmc_id = 41 823 }, 824 { 825 .scmi_id = AT91_SCMI_CLK_PERIPH_UDPHS_CLK, 826 .pmc_type = PMC_TYPE_PERIPHERAL, 827 .pmc_id = 42 828 }, 829 { 830 .scmi_id = AT91_SCMI_CLK_PERIPH_SSC0_CLK, 831 .pmc_type = PMC_TYPE_PERIPHERAL, 832 .pmc_id = 43 833 }, 834 { 835 .scmi_id = AT91_SCMI_CLK_PERIPH_SSC1_CLK, 836 .pmc_type = PMC_TYPE_PERIPHERAL, 837 .pmc_id = 44 838 }, 839 { 840 .scmi_id = AT91_SCMI_CLK_PERIPH_TRNG_CLK, 841 .pmc_type = PMC_TYPE_PERIPHERAL, 842 .pmc_id = 47 843 }, 844 { 845 .scmi_id = AT91_SCMI_CLK_PERIPH_PDMIC_CLK, 846 .pmc_type = PMC_TYPE_PERIPHERAL, 847 .pmc_id = 48 848 }, 849 { 850 .scmi_id = AT91_SCMI_CLK_PERIPH_SECURAM_CLK, 851 .pmc_type = PMC_TYPE_PERIPHERAL, 852 .pmc_id = 51 853 }, 854 { 855 .scmi_id = AT91_SCMI_CLK_PERIPH_I2S0_CLK, 856 .pmc_type = PMC_TYPE_PERIPHERAL, 857 .pmc_id = 54 858 }, 859 { 860 .scmi_id = AT91_SCMI_CLK_PERIPH_I2S1_CLK, 861 .pmc_type = PMC_TYPE_PERIPHERAL, 862 .pmc_id = 55 863 }, 864 { 865 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN0_CLK, 866 .pmc_type = PMC_TYPE_PERIPHERAL, 867 .pmc_id = 56 868 }, 869 { 870 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN1_CLK, 871 .pmc_type = PMC_TYPE_PERIPHERAL, 872 .pmc_id = 57 873 }, 874 { 875 .scmi_id = AT91_SCMI_CLK_PERIPH_PTC_CLK, 876 .pmc_type = PMC_TYPE_PERIPHERAL, 877 .pmc_id = 58 878 }, 879 { 880 .scmi_id = AT91_SCMI_CLK_PERIPH_CLASSD_CLK, 881 .pmc_type = PMC_TYPE_PERIPHERAL, 882 .pmc_id = 59 883 }, 884 { 885 .scmi_id = AT91_SCMI_CLK_PERIPH_DMA0_CLK, 886 .pmc_type = PMC_TYPE_PERIPHERAL, 887 .pmc_id = 6 888 }, 889 { 890 .scmi_id = AT91_SCMI_CLK_PERIPH_DMA1_CLK, 891 .pmc_type = PMC_TYPE_PERIPHERAL, 892 .pmc_id = 7 893 }, 894 { 895 .scmi_id = AT91_SCMI_CLK_PERIPH_AES_CLK, 896 .pmc_type = PMC_TYPE_PERIPHERAL, 897 .pmc_id = 9 898 }, 899 { 900 .scmi_id = AT91_SCMI_CLK_PERIPH_AESB_CLK, 901 .pmc_type = PMC_TYPE_PERIPHERAL, 902 .pmc_id = 10 903 }, 904 { 905 .scmi_id = AT91_SCMI_CLK_PERIPH_SHA_CLK, 906 .pmc_type = PMC_TYPE_PERIPHERAL, 907 .pmc_id = 12 908 }, 909 { 910 .scmi_id = AT91_SCMI_CLK_PERIPH_MPDDR_CLK, 911 .pmc_type = PMC_TYPE_PERIPHERAL, 912 .pmc_id = 13 913 }, 914 { 915 .scmi_id = AT91_SCMI_CLK_PERIPH_MATRIX0_CLK, 916 .pmc_type = PMC_TYPE_PERIPHERAL, 917 .pmc_id = 15 918 }, 919 { 920 .scmi_id = AT91_SCMI_CLK_PERIPH_SDMMC0_HCLK, 921 .pmc_type = PMC_TYPE_PERIPHERAL, 922 .pmc_id = 31 923 }, 924 { 925 .scmi_id = AT91_SCMI_CLK_PERIPH_SDMMC1_HCLK, 926 .pmc_type = PMC_TYPE_PERIPHERAL, 927 .pmc_id = 32 928 }, 929 { 930 .scmi_id = AT91_SCMI_CLK_PERIPH_LCDC_CLK, 931 .pmc_type = PMC_TYPE_PERIPHERAL, 932 .pmc_id = 45 933 }, 934 { 935 .scmi_id = AT91_SCMI_CLK_PERIPH_ISC_CLK, 936 .pmc_type = PMC_TYPE_PERIPHERAL, 937 .pmc_id = 46 938 }, 939 { 940 .scmi_id = AT91_SCMI_CLK_PERIPH_QSPI0_CLK, 941 .pmc_type = PMC_TYPE_PERIPHERAL, 942 .pmc_id = 52 943 }, 944 { 945 .scmi_id = AT91_SCMI_CLK_PERIPH_QSPI1_CLK, 946 .pmc_type = PMC_TYPE_PERIPHERAL, 947 .pmc_id = 53 948 }, 949 { 950 .scmi_id = AT91_SCMI_CLK_GCK_SDMMC0_GCLK, 951 .pmc_type = PMC_TYPE_GCK, 952 .pmc_id = 31 953 }, 954 { 955 .scmi_id = AT91_SCMI_CLK_GCK_SDMMC1_GCLK, 956 .pmc_type = PMC_TYPE_GCK, 957 .pmc_id = 32 958 }, 959 { 960 .scmi_id = AT91_SCMI_CLK_GCK_TCB0_GCLK, 961 .pmc_type = PMC_TYPE_GCK, 962 .pmc_id = 35 963 }, 964 { 965 .scmi_id = AT91_SCMI_CLK_GCK_TCB1_GCLK, 966 .pmc_type = PMC_TYPE_GCK, 967 .pmc_id = 36 968 }, 969 { 970 .scmi_id = AT91_SCMI_CLK_GCK_PWM_GCLK, 971 .pmc_type = PMC_TYPE_GCK, 972 .pmc_id = 38 973 }, 974 { 975 .scmi_id = AT91_SCMI_CLK_GCK_ISC_GCLK, 976 .pmc_type = PMC_TYPE_GCK, 977 .pmc_id = 46 978 }, 979 { 980 .scmi_id = AT91_SCMI_CLK_GCK_PDMIC_GCLK, 981 .pmc_type = PMC_TYPE_GCK, 982 .pmc_id = 48 983 }, 984 { 985 .scmi_id = AT91_SCMI_CLK_GCK_I2S0_GCLK, 986 .pmc_type = PMC_TYPE_GCK, 987 .pmc_id = 54 988 }, 989 { 990 .scmi_id = AT91_SCMI_CLK_GCK_I2S1_GCLK, 991 .pmc_type = PMC_TYPE_GCK, 992 .pmc_id = 55 993 }, 994 { 995 .scmi_id = AT91_SCMI_CLK_GCK_CAN0_GCLK, 996 .pmc_type = PMC_TYPE_GCK, 997 .pmc_id = 56 998 }, 999 { 1000 .scmi_id = AT91_SCMI_CLK_GCK_CAN1_GCLK, 1001 .pmc_type = PMC_TYPE_GCK, 1002 .pmc_id = 57 1003 }, 1004 { 1005 .scmi_id = AT91_SCMI_CLK_GCK_CLASSD_GCLK, 1006 .pmc_type = PMC_TYPE_GCK, 1007 .pmc_id = 59 1008 }, 1009 { 1010 .scmi_id = AT91_SCMI_CLK_PROG_PROG0, 1011 .pmc_type = PMC_TYPE_PROGRAMMABLE, 1012 .pmc_id = 0 1013 }, 1014 { 1015 .scmi_id = AT91_SCMI_CLK_PROG_PROG1, 1016 .pmc_type = PMC_TYPE_PROGRAMMABLE, 1017 .pmc_id = 1 1018 }, 1019 { 1020 .scmi_id = AT91_SCMI_CLK_PROG_PROG2, 1021 .pmc_type = PMC_TYPE_PROGRAMMABLE, 1022 .pmc_id = 2 1023 }, 1024 }; 1025 #endif 1026 1027 static TEE_Result sam_init_scmi_clk(void) 1028 { 1029 unsigned int i = 0; 1030 struct clk *clk = NULL; 1031 TEE_Result res = TEE_ERROR_GENERIC; 1032 const struct sam_pmc_clk *pmc_clk = NULL; 1033 1034 for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) { 1035 pmc_clk = &pmc_clks[i]; 1036 res = at91_pmc_clk_get(pmc_clk->pmc_type, pmc_clk->pmc_id, 1037 &clk); 1038 if (res) { 1039 EMSG("Failed to get PMC clock type %u, id %u", 1040 pmc_clk->pmc_type, pmc_clk->pmc_id); 1041 return res; 1042 } 1043 res = scmi_clk_add(clk, 0, pmc_clk->scmi_id); 1044 if (res) { 1045 EMSG("Failed to add PMC SCMI clock id %u", 1046 pmc_clk->scmi_id); 1047 return res; 1048 } 1049 } 1050 1051 clk = at91_sckc_clk_get(); 1052 if (!clk) 1053 return TEE_ERROR_GENERIC; 1054 1055 res = scmi_clk_add(clk, 0, AT91_SCMI_CLK_SCKC_SLOWCK_32K); 1056 if (res) { 1057 EMSG("Failed to add slow clock to SCMI clocks"); 1058 return res; 1059 } 1060 1061 clk = at91_cpu_opp_clk_get(); 1062 if (clk) { 1063 res = scmi_clk_add(clk, 0, AT91_SCMI_CLK_CPU_OPP); 1064 if (res) { 1065 EMSG("Failed to add CPU OPP clock to SCMI clocks"); 1066 return res; 1067 } 1068 } 1069 1070 return TEE_SUCCESS; 1071 } 1072 1073 static struct sam_scmi_rd *find_rd(unsigned int channel_id, 1074 unsigned int scmi_id) 1075 { 1076 const struct channel_resources *resource = find_resource(channel_id); 1077 1078 if (resource && scmi_id < resource->rd_count) 1079 return &resource->rd[scmi_id]; 1080 1081 return NULL; 1082 } 1083 1084 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 1085 bool assert_not_deassert) 1086 { 1087 const struct sam_scmi_rd *rd = find_rd(channel_id, scmi_id); 1088 TEE_Result res = TEE_ERROR_GENERIC; 1089 1090 if (!rd) 1091 return SCMI_NOT_FOUND; 1092 1093 if (!rd->rstctrl) 1094 return SCMI_DENIED; 1095 1096 if (assert_not_deassert) { 1097 FMSG("SCMI reset %u set", scmi_id); 1098 res = rstctrl_assert(rd->rstctrl); 1099 } else { 1100 FMSG("SCMI reset %u release", scmi_id); 1101 res = rstctrl_deassert(rd->rstctrl); 1102 } 1103 1104 if (res) 1105 return SCMI_HARDWARE_ERROR; 1106 1107 return SCMI_SUCCESS; 1108 } 1109 1110 size_t plat_scmi_rd_count(unsigned int channel_id) 1111 { 1112 const struct channel_resources *resource = find_resource(channel_id); 1113 1114 if (!resource) 1115 return 0; 1116 1117 return resource->rd_count; 1118 } 1119 1120 void sam_set_clock_range(unsigned int pmc_type, unsigned int pmc_id, 1121 const struct clk_range *range) 1122 { 1123 struct sam_pmc_clk *p = NULL; 1124 1125 for (p = pmc_clks; p < pmc_clks + ARRAY_SIZE(pmc_clks); p++) { 1126 if (pmc_type == p->pmc_type && pmc_id == p->pmc_id) { 1127 p->output_range.min = range->min; 1128 p->output_range.max = range->max; 1129 return; 1130 } 1131 } 1132 } 1133 1134 int32_t plat_scmi_clock_rates_by_step(unsigned int channel_id, 1135 unsigned int scmi_id, 1136 unsigned long *steps) 1137 { 1138 const struct sam_pmc_clk *p = NULL; 1139 int32_t res = SCMI_NOT_SUPPORTED; 1140 1141 if (channel_id) 1142 return res; 1143 1144 for (p = pmc_clks; p < pmc_clks + ARRAY_SIZE(pmc_clks); p++) { 1145 if (scmi_id == p->scmi_id) { 1146 if (p->output_range.max) { 1147 steps[0] = p->output_range.min; 1148 steps[1] = p->output_range.max; 1149 steps[2] = 1; 1150 res = SCMI_SUCCESS; 1151 } 1152 break; 1153 } 1154 } 1155 1156 return res; 1157 } 1158 1159 /* 1160 * Initialize platform SCMI resources 1161 */ 1162 static TEE_Result sam_init_scmi_server(void) 1163 { 1164 size_t i = 0; 1165 size_t j = 0; 1166 1167 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 1168 const struct channel_resources *res = scmi_channel + i; 1169 struct scmi_msg_channel *chan = res->channel; 1170 1171 /* Enforce non-secure shm mapped as device memory */ 1172 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 1173 MEM_AREA_IO_NSEC, 1); 1174 assert(chan->shm_addr.va); 1175 1176 scmi_smt_init_agent_channel(chan); 1177 1178 for (j = 0; j < res->rd_count; j++) { 1179 struct sam_scmi_rd *rd = &res->rd[j]; 1180 struct rstctrl *rstctrl = NULL; 1181 1182 rstctrl = sam_get_rstctrl(rd->reset_id); 1183 assert(rstctrl); 1184 if (rstctrl_get_exclusive(rstctrl)) 1185 continue; 1186 1187 rd->rstctrl = rstctrl; 1188 } 1189 } 1190 1191 return sam_init_scmi_clk(); 1192 } 1193 1194 driver_init_late(sam_init_scmi_server); 1195