plat-rzn1: increase DDR size to 1GB

There are now some RZ/N1 devices with 1GB rather than 256MB. The
first-stage bootloader does not support passing a DT to OP-TEE, so
static values are set at compi

plat-rzn1: increase DDR size to 1GB

There are now some RZ/N1 devices with 1GB rather than 256MB. The
first-stage bootloader does not support passing a DT to OP-TEE, so
static values are set at compile time. Increase the DDR size so as to
avoid OP-TEE calls failing with TEEC_ERROR_OUT_OF_MEMORY.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

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core: riscv: kernel: Add missing initialization for core local stacks

The thread core local stacks should be initialized when the primary core
performs system initialization.

Fixes: ca8258906949 ("

core: riscv: kernel: Add missing initialization for core local stacks

The thread core local stacks should be initialized when the primary core
performs system initialization.

Fixes: ca8258906949 ("core: split core/arch/arm/kernel/thread.c")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: support physically relocatable OP-TEE binary

With CFG_CORE_PHYS_RELOCATABLE=y enable support in OP-TEE to relocate
itself to allow it to run from physical address that differs from the
link ad

core: support physically relocatable OP-TEE binary

With CFG_CORE_PHYS_RELOCATABLE=y enable support in OP-TEE to relocate
itself to allow it to run from physical address that differs from the
link address.

This feature is currently only supported with CFG_CORE_SEL2_SPMC=y since
the TEE core has to know the range of available memory. With SPMC at EL2
this is accomplished via get_sec_mem_from_manifest(). An SPMC at S-EL2
may need to load OP-TEE at a different address depending on
configuration.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: parse boot info

With CFG_CORE_SEL2_SPMC=y OP-TEE is executed as an SP at S-EL1. The
manifest describing the OP-TEE SP is passed as a boot argument.

The manifest contains among other thin

core: ffa: parse boot info

With CFG_CORE_SEL2_SPMC=y OP-TEE is executed as an SP at S-EL1. The
manifest describing the OP-TEE SP is passed as a boot argument.

The manifest contains among other things the two properties
"load-address" and "mem-size". These cover the secure memory allocated
for OP-TEE to cover core and TA memory. The retrieved memory range is
saved with a call to core_mmu_set_secure_memory() to be used when
initializing MMU and other memory configuration.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: add boot info structs and defines

Adds defines to interpret FF-A Boot Info header and descriptor using two
new structs and accompanying defines.

Acked-by: Etienne Carriere <etienne.carri

core: ffa: add boot info structs and defines

Adds defines to interpret FF-A Boot Info header and descriptor using two
new structs and accompanying defines.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: generic_ram_layout.h: remove TA_RAM_*

Removes the TA_RAM_START and TA_RAM_SIZE defines since core_mmu.c can
calculate the values based registered secure_only memory.

Reviewed-by: Etienne

core: arm: generic_ram_layout.h: remove TA_RAM_*

Removes the TA_RAM_START and TA_RAM_SIZE defines since core_mmu.c can
calculate the values based registered secure_only memory.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: virt: use core_mmu_get_ta_range()

In get_ta_ram_size() use core_mmu_get_ta_range() instead of the define
TA_RAM_SIZE.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by

core: virt: use core_mmu_get_ta_range()

In get_ta_ram_size() use core_mmu_get_ta_range() instead of the define
TA_RAM_SIZE.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: kernel: Fix stack pointer initialization for each hart

The RISC-V privileged specification defines that at least one hart must
have a hart ID of zero. Since at least one stack_tmp_strid

core: riscv: kernel: Fix stack pointer initialization for each hart

The RISC-V privileged specification defines that at least one hart must
have a hart ID of zero. Since at least one stack_tmp_stride is required
for calculating the initial SP value for each hart, the formula should
be address of stack_tmp plus (hartid+1) multiplied by stack_tmp_stride.

This commit fixes the formula for initializing SP of each hart,
otherwise the stack underflow happens to hart 0.

Fixes: 93e54a63925f ("riscv: kernel: entry.S: provide entry script")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: notif: fix input comment typo

Fixes inline comment typo in OP-TEE standard SMCs description and
CFG_CORE_ASYNC_NOTIF switch description.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org

core: notif: fix input comment typo

Fixes inline comment typo in OP-TEE standard SMCs description and
CFG_CORE_ASYNC_NOTIF switch description.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: Refactor macros for inline assembly of CSR operations

Current CSR macros with inline assembly will lead to compilation error,
because they use pre-processor stringizing not value substi

core: riscv: Refactor macros for inline assembly of CSR operations

Current CSR macros with inline assembly will lead to compilation error,
because they use pre-processor stringizing not value substitution. The
definitions such as CSR_XSTATUS are not sustituted to CSR encoding in
CSR macros and compiler generates: Error: unknown CSR `CSR_XSTATUS'.

This patch fixes it by making the given CSR to be an assembly input
operand with constraint "i", which is used to indicate the operand is
an immediate integer operand. Thus, the CSR encoding can be correctly
compiled.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-vexpress: remove TPM2 MMIO driver

Disable TPM2 MMIO driver and remove its integration from platform
vexpress. OP-TEE will instead rely on a remote REE TPM2 driver
allowing REE OS to embed TPM2

plat-vexpress: remove TPM2 MMIO driver

Disable TPM2 MMIO driver and remove its integration from platform
vexpress. OP-TEE will instead rely on a remote REE TPM2 driver
allowing REE OS to embed TPM2 software stack and leverage TPM2 features.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: mm: Add missing return for TLB helpers

These functions should contain tailing ret instruction to return to
caller.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome F

core: riscv: mm: Add missing return for TLB helpers

These functions should contain tailing ret instruction to return to
caller.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: ls: remove CFG_WITH_SOFTWARE_PRNG default definition for LS platforms

Remove the enablement of CFG_WITH_SOFTWARE_PRNG flag when the CAAM is
disabled. CFG_WITH_SOFTWARE_PRNG is enabled by defau

core: ls: remove CFG_WITH_SOFTWARE_PRNG default definition for LS platforms

Remove the enablement of CFG_WITH_SOFTWARE_PRNG flag when the CAAM is
disabled. CFG_WITH_SOFTWARE_PRNG is enabled by default.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: remove CFG_WITH_SOFTWARE_PRNG default definition for i.MX platforms

Remove the enablement of CFG_WITH_SOFTWARE_PRNG ?= y since it's already
globally enabled.

Signed-off-by: Clement Faure

core: imx: remove CFG_WITH_SOFTWARE_PRNG default definition for i.MX platforms

Remove the enablement of CFG_WITH_SOFTWARE_PRNG ?= y since it's already
globally enabled.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: remove drivers directory

Remove drivers directory from plat-imx/ since all drivers should go to
core/drivers/.
Move tzc380.c to plat-imx/

Signed-off-by: Clement Faure <clement.faure@nxp.

core: imx: remove drivers directory

Remove drivers directory from plat-imx/ since all drivers should go to
core/drivers/.
Move tzc380.c to plat-imx/

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: imx_csu: move imx_csu driver source file

Move imx_csu driver from plat-imx/ to core/drivers/
Rename CFG_CSU to CFG_IMX_CSU compilation flag.

Signed-off-by: Clement Faure <clement.faure@nxp

drivers: imx_csu: move imx_csu driver source file

Move imx_csu driver from plat-imx/ to core/drivers/
Rename CFG_CSU to CFG_IMX_CSU compilation flag.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: imx_scu: move imx_scu driver source file

Move imx_scu driver from plat-imx/ to core/drivers/
Rename CFG_SCU to CFG_IMX_SCU compilation flag.

Signed-off-by: Clement Faure <clement.faure@nxp

drivers: imx_scu: move imx_scu driver source file

Move imx_scu driver from plat-imx/ to core/drivers/
Rename CFG_SCU to CFG_IMX_SCU compilation flag.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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driver: imx_caam: move imx_caam driver source file

Move imx_caam driver from plat-imx/ to core/drivers/

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.fo

driver: imx_caam: move imx_caam driver source file

Move imx_caam driver from plat-imx/ to core/drivers/

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: caam: remove imx_caam.h header file

Remove imx_caam header file and move its content to source file.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jero

core: imx: caam: remove imx_caam.h header file

Remove imx_caam header file and move its content to source file.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: remove unnecessary preprocessor directive

Remove error regarding CFG_WITH_PAGER and CFG_WITH_LPAE on imx6ul/ull.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome For

core: imx: remove unnecessary preprocessor directive

Remove error regarding CFG_WITH_PAGER and CFG_WITH_LPAE on imx6ul/ull.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: scu: move SCU configuration values to source file

Move SCU configuration values from header file to the SCU source file.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Je

core: imx: scu: move SCU configuration values to source file

Move SCU configuration values from header file to the SCU source file.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: remove imx_sip.h

Remove imx_sip.h header file.
Move definitions to the source file.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@l

core: imx: remove imx_sip.h

Remove imx_sip.h header file.
Move definitions to the source file.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: kernel: Fix compilation error with missing parameter

This patch adds "unsigned long tos_fw_config" as second parameter for
RISC-V's boot_init_primary_late() to solve compilation error.

core: riscv: kernel: Fix compilation error with missing parameter

This patch adds "unsigned long tos_fw_config" as second parameter for
RISC-V's boot_init_primary_late() to solve compilation error.

Fixes: 809fa817ae63 ("core: ffa: add TOS_FW_CONFIG handling")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: spmc: handle HW feature info in SP manifest

Provide information to the SP about available HW features by updating
the relevant DT node in the SP manifest. Currently only the CRC32
feature is s

core: spmc: handle HW feature info in SP manifest

Provide information to the SP about available HW features by updating
the relevant DT node in the SP manifest. Currently only the CRC32
feature is supported.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: arm64: add CRC32 HW support discovery

Add helper function to check if the CRC32 instructions are implemented
by the PE.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: J

core: arm64: add CRC32 HW support discovery

Add helper function to check if the CRC32 instructions are implemented
by the PE.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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