core: riscv: Fix condition of is_from_user()

RISC-V defines that xPP(previous privilege mode) field of CSR status
indicates the previous privilege level prior to the trap. Since the
encoding of user

core: riscv: Fix condition of is_from_user()

RISC-V defines that xPP(previous privilege mode) field of CSR status
indicates the previous privilege level prior to the trap. Since the
encoding of user mode is 0, we should compare the xPP field with 0 here
to know that the trap is from user mode.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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riscv: plat-virt: Align PLIC configurations with QEMU v8.1.1

Align the PLIC configurations with RISC-V QEMU virtual platform based on
official QEMU v8.1.1 tag. The maximum size of PLIC should be 0x6

riscv: plat-virt: Align PLIC configurations with QEMU v8.1.1

Align the PLIC configurations with RISC-V QEMU virtual platform based on
official QEMU v8.1.1 tag. The maximum size of PLIC should be 0x600000,
and the number of interrupt sources should be 95.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: plic: Maintain controller data in driver source file

To align the design from other architecture, we move the interrupt
controller data instance from platform source file to driver source
f

drivers: plic: Maintain controller data in driver source file

To align the design from other architecture, we move the interrupt
controller data instance from platform source file to driver source
file. With this change, the PLIC initialization functions no more get
the controller data as input argument. Platforms do not need to care
about the interrupt controller data instance.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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plat-stm32mp1: enable support for regulators

Enables regulator framework on platform stm32mp1.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallie

plat-stm32mp1: enable support for regulators

Enables regulator framework on platform stm32mp1.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-mediatek: add support for MT8188 SoC

Add OP-TEE support for the MT8188 SoC.

Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: ls: enable CFG_PKCS11_TA

Enable PKCS11 TA by default for LS platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: imx: enable CFG_PKCS11_TA

Enable PKCS11 TA by default for i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: ls: enabled CFG_ENABLE_EMBEDDED_TESTS by default

Enable embedded tests by default on Layerscape platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jer

core: ls: enabled CFG_ENABLE_EMBEDDED_TESTS by default

Enable embedded tests by default on Layerscape platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: enabled CFG_ENABLE_EMBEDDED_TESTS by default

Enable embedded tests by default on i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.f

core: imx: enabled CFG_ENABLE_EMBEDDED_TESTS by default

Enable embedded tests by default on i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: ls: increase heap size to 128k

In xtest_regression_4011, with libtomcrypt enabled, the allocation of a 4k
buffer would eventually fail (TEE_ERROR_OUT_OF_MEMORY) during the
allocation.

Signed-

core: ls: increase heap size to 128k

In xtest_regression_4011, with libtomcrypt enabled, the allocation of a 4k
buffer would eventually fail (TEE_ERROR_OUT_OF_MEMORY) during the
allocation.

Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: increase heap size to 128k

In xtest_regression_4011, with libtomcrypt enabled, the allocation of a 4k
buffer would eventually fail (TEE_ERROR_OUT_OF_MEMORY) during the
allocation.

Signed

core: imx: increase heap size to 128k

In xtest_regression_4011, with libtomcrypt enabled, the allocation of a 4k
buffer would eventually fail (TEE_ERROR_OUT_OF_MEMORY) during the
allocation.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: add CFG_WDT_SM_HANDLER_ID in TOS fast call list

Add CFG_WDT_SM_HANDLER_ID as a TOS fast call entry to manage the
ARM watchdog service in 64 bit mode. Add also the associated ABI
description.
D

core: add CFG_WDT_SM_HANDLER_ID in TOS fast call list

Add CFG_WDT_SM_HANDLER_ID as a TOS fast call entry to manage the
ARM watchdog service in 64 bit mode. Add also the associated ABI
description.
Define the CFG_WDT_SM_HANDLER_ID with a default value.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: support fault mitigations in non-threaded code

Fault mitigation won't work in non-threaded code due to the following
error:
assertion 'ct >= 0 && ct < CFG_NUM_THREADS' failed at core/arch/arm/

core: support fault mitigations in non-threaded code

Fault mitigation won't work in non-threaded code due to the following
error:
assertion 'ct >= 0 && ct < CFG_NUM_THREADS' failed at core/arch/arm/kernel
/thread.c:799 <thread_get_id>

The problem is in __ftmn_get_tsd_func_arg_pp which calls thread_get_tsd
which thread_get_id. The reason is that the interrupt handler is not
associated with any thread, so the ct (current_thread_id) value is -1 which
would cause an assert problem.

The fix is to add ftmn_arg to thread_core_local and the new variable would
be used when the current thread is < 0.

Signed-off-by: Sichun Qin <sichun.qin@amlogic.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: implement boot-order support

Add support for boot-order property specified in the
SP manifest.

Signed-off-by: Gabor Ambrus <gabor.ambrus@arm.com>
Signed-off-by: Gabor Toth <gabor.toth2@

core: spmc: implement boot-order support

Add support for boot-order property specified in the
SP manifest.

Signed-off-by: Gabor Ambrus <gabor.ambrus@arm.com>
Signed-off-by: Gabor Toth <gabor.toth2@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: imx: relocate power management code

Relocate power management functions from plat-imx/pm to
core/drivers/pm/imx

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wikl

drivers: pm: imx: relocate power management code

Relocate power management functions from plat-imx/pm to
core/drivers/pm/imx

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: re-work GPCv2 driver

Re-work GPCv2 driver:
* use io_clr/set functions
* use timeout for register polling
Remove imx_gpcv2_set_core1_pdn_by_software() function.

Signed-off-by: Clement F

core: imx: re-work GPCv2 driver

Re-work GPCv2 driver:
* use io_clr/set functions
* use timeout for register polling
Remove imx_gpcv2_set_core1_pdn_by_software() function.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: move gpcv2 functions definitions to local.h

Move imx_gpcv2_set_core1_pdn_by_software() and
imx_gpcv2_set_core1_pup_by_software() definitions to local.h.
Make imx_gpcv2_set_core_pgc() stat

core: imx: move gpcv2 functions definitions to local.h

Move imx_gpcv2_set_core1_pdn_by_software() and
imx_gpcv2_set_core1_pup_by_software() definitions to local.h.
Make imx_gpcv2_set_core_pgc() static.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: cleanup imx-regs.h

Remove macros from imx-regs.h and relocate to appropriate source files.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@l

core: imx: cleanup imx-regs.h

Remove macros from imx-regs.h and relocate to appropriate source files.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: move PSCI SNVS operation to the driver

Create imx_snvs_shutdown() to use during psci_system_off() call.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jen

core: imx: move PSCI SNVS operation to the driver

Create imx_snvs_shutdown() to use during psci_system_off() call.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: fix IOMUXC GPR5 register read

Define IOMUXC_SIZE value for imx7 platforms and re-work the way the GPR
register is read.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jen

core: imx: fix IOMUXC GPR5 register read

Define IOMUXC_SIZE value for imx7 platforms and re-work the way the GPR
register is read.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: re-work SRC driver

Encapsulate all SRC register operations in dedicated functions.
Move SRC register offsets and values to SRC source file.
Define SRC_SIZE for i.MX6 and i.MX7 platforms.

core: imx: re-work SRC driver

Encapsulate all SRC register operations in dedicated functions.
Move SRC register offsets and values to SRC source file.
Define SRC_SIZE for i.MX6 and i.MX7 platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: move SRC driver to pm directory

Move the SRC driver to pm sub-directory since it is related to the power
management PSCI features.
Rename it from imx_src.c to src.c.
Create a local header

core: imx: move SRC driver to pm directory

Move the SRC driver to pm sub-directory since it is related to the power
management PSCI features.
Rename it from imx_src.c to src.c.
Create a local header file.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: remove PSCI_CPU_SUSPEND capability

Remove the PSCI_CPU_SUSPEND capability as it is not supported.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wikl

core: imx: remove PSCI_CPU_SUSPEND capability

Remove the PSCI_CPU_SUSPEND capability as it is not supported.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: remove power management code for imx7d platforms

The code for suspend and cpuidle is not functioning properly,
outdated and unmaintained.
Remove these two features and associated code.

S

core: imx: remove power management code for imx7d platforms

The code for suspend and cpuidle is not functioning properly,
outdated and unmaintained.
Remove these two features and associated code.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: tee: add entry_fast.c

This commit adds an implementation of fast call handers. It copies
the original implementation replacing thread_smc_args structures
with thread_abi_args counterpar

core: riscv: tee: add entry_fast.c

This commit adds an implementation of fast call handers. It copies
the original implementation replacing thread_smc_args structures
with thread_abi_args counterparts. tee_entry_fastcall_l2cc_mutex()
has been modified to return OPTEE_ABI_RETURN_UNKNOWN_FUNCTION.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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