1PLATFORM_FLAVOR ?= ls1012ardb 2 3$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 4$(call force,CFG_GIC,y) 5$(call force,CFG_16550_UART,y) 6$(call force,CFG_LS,y) 7 8$(call force,CFG_DRAM0_BASE,0x80000000) 9$(call force,CFG_TEE_OS_DRAM0_SIZE,0x4000000) 10 11CFG_CORE_HEAP_SIZE ?= 131072 12 13ifeq ($(PLATFORM_FLAVOR),ls1012ardb) 14include core/arch/arm/cpu/cortex-armv8-0.mk 15$(call force,CFG_TEE_CORE_NB_CORE,1) 16$(call force,CFG_DRAM0_SIZE,0x40000000) 17$(call force,CFG_CORE_CLUSTER_SHIFT,2) 18CFG_NUM_THREADS ?= 2 19CFG_SHMEM_SIZE ?= 0x00200000 20endif 21 22ifeq ($(PLATFORM_FLAVOR),ls1043ardb) 23include core/arch/arm/cpu/cortex-armv8-0.mk 24$(call force,CFG_TEE_CORE_NB_CORE,4) 25$(call force,CFG_DRAM0_SIZE,0x80000000) 26$(call force,CFG_CORE_CLUSTER_SHIFT,2) 27CFG_SHMEM_SIZE ?= 0x00200000 28endif 29 30ifeq ($(PLATFORM_FLAVOR),ls1046ardb) 31include core/arch/arm/cpu/cortex-armv8-0.mk 32$(call force,CFG_TEE_CORE_NB_CORE,4) 33$(call force,CFG_DRAM0_SIZE,0x80000000) 34$(call force,CFG_CORE_CLUSTER_SHIFT,2) 35CFG_SHMEM_SIZE ?= 0x00200000 36endif 37 38ifeq ($(PLATFORM_FLAVOR),ls1088ardb) 39include core/arch/arm/cpu/cortex-armv8-0.mk 40$(call force,CFG_TEE_CORE_NB_CORE,8) 41$(call force,CFG_DRAM0_SIZE,0x80000000) 42$(call force,CFG_CORE_CLUSTER_SHIFT,2) 43$(call force,CFG_ARM_GICV3,y) 44CFG_SHMEM_SIZE ?= 0x00200000 45endif 46 47ifeq ($(PLATFORM_FLAVOR),ls2088ardb) 48include core/arch/arm/cpu/cortex-armv8-0.mk 49$(call force,CFG_TEE_CORE_NB_CORE,8) 50$(call force,CFG_DRAM0_SIZE,0x80000000) 51$(call force,CFG_CORE_CLUSTER_SHIFT,1) 52$(call force,CFG_ARM_GICV3,y) 53CFG_SHMEM_SIZE ?= 0x00200000 54endif 55 56ifeq ($(PLATFORM_FLAVOR),lx2160aqds) 57include core/arch/arm/cpu/cortex-armv8-0.mk 58$(call force,CFG_TEE_CORE_NB_CORE,16) 59$(call force,CFG_DRAM0_SIZE,0x80000000) 60$(call force,CFG_DRAM1_BASE,0x2080000000) 61$(call force,CFG_DRAM1_SIZE,0x1F80000000) 62$(call force,CFG_CORE_CLUSTER_SHIFT,1) 63$(call force,CFG_ARM_GICV3,y) 64$(call force,CFG_PL011,y) 65$(call force,CFG_CORE_ARM64_PA_BITS,48) 66$(call force,CFG_EMBED_DTB,y) 67$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-qds.dts) 68CFG_LS_I2C ?= y 69CFG_LS_GPIO ?= y 70CFG_LS_DSPI ?= y 71CFG_SHMEM_SIZE ?= 0x00200000 72endif 73 74ifeq ($(PLATFORM_FLAVOR),lx2160ardb) 75include core/arch/arm/cpu/cortex-armv8-0.mk 76$(call force,CFG_TEE_CORE_NB_CORE,16) 77$(call force,CFG_DRAM0_SIZE,0x80000000) 78$(call force,CFG_DRAM1_BASE,0x2080000000) 79$(call force,CFG_DRAM1_SIZE,0x1F80000000) 80$(call force,CFG_CORE_CLUSTER_SHIFT,1) 81$(call force,CFG_ARM_GICV3,y) 82$(call force,CFG_PL011,y) 83$(call force,CFG_CORE_ARM64_PA_BITS,48) 84$(call force,CFG_EMBED_DTB,y) 85$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-rdb.dts) 86CFG_LS_I2C ?= y 87CFG_LS_GPIO ?= y 88CFG_LS_DSPI ?= y 89CFG_SHMEM_SIZE ?= 0x00200000 90endif 91 92ifeq ($(PLATFORM_FLAVOR),ls1028ardb) 93include core/arch/arm/cpu/cortex-armv8-0.mk 94$(call force,CFG_TEE_CORE_NB_CORE,2) 95$(call force,CFG_DRAM0_SIZE,0x80000000) 96$(call force,CFG_CORE_CLUSTER_SHIFT,1) 97$(call force,CFG_ARM_GICV3,y) 98CFG_SHMEM_SIZE ?= 0x00200000 99endif 100 101ifeq ($(platform-flavor-armv8),1) 102$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 103CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 104CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - CFG_SHMEM_SIZE) 105#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 106CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_SHMEM_SIZE) 107$(call force,CFG_ARM64_core,y) 108CFG_USER_TA_TARGETS ?= ta_arm64 109else 110#In ARMv7 platform CFG_SHMEM_SIZE is different to that of ARMv8 platforms. 111CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 112CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - (2*CFG_SHMEM_SIZE)) 113#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 114CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - (2*CFG_SHMEM_SIZE)) 115endif 116 117#Keeping Number of TEE thread equal to number of cores on the SoC 118CFG_NUM_THREADS ?= $(CFG_TEE_CORE_NB_CORE) 119 120ifneq ($(CFG_ARM64_core),y) 121$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 122endif 123 124CFG_CRYPTO_SIZE_OPTIMIZATION ?= n 125 126# NXP CAAM support is not enabled by default and can be enabled 127# on the command line 128CFG_NXP_CAAM ?= n 129