plat-stm32mp2: enable watchdog SMC service

Enable Arm watchdog SMC service using function ID 0xbc000000.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Gof

plat-stm32mp2: enable watchdog SMC service

Enable Arm watchdog SMC service using function ID 0xbc000000.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: conf: default enable CFG_STM32_IWDG

Default enable STM32 IWDG driver on STM32MP2 platforms.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le G

plat-stm32mp2: conf: default enable CFG_STM32_IWDG

Default enable STM32 IWDG driver on STM32MP2 platforms.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: enable IWDG1 on stm32mp215f-dk board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevall

dts: stm32: enable IWDG1 on stm32mp215f-dk board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: enable IWDG1 on stm32mp257f-ev1 board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.cheval

dts: stm32: enable IWDG1 on stm32mp257f-ev1 board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add IWDG[1-2] nodes in stm32mp21x soc device-tree

Add support for IWDG[1-2] in stm32mp21x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gat

dts: stm32: add IWDG[1-2] nodes in stm32mp21x soc device-tree

Add support for IWDG[1-2] in stm32mp21x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add IWDG[1-2] nodes in stm32mp25x soc device-tree

Add support for IWDG[1-2] in stm32mp25x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gat

dts: stm32: add IWDG[1-2] nodes in stm32mp25x soc device-tree

Add support for IWDG[1-2] in stm32mp25x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-versal2: use auto PA bit discovery

Removes hardcoded configuration for large physical address and
ARM64 PA bits, enabling automatic discovery of the maximal PA
supported by the hardware.

Signe

plat-versal2: use auto PA bit discovery

Removes hardcoded configuration for large physical address and
ARM64 PA bits, enabling automatic discovery of the maximal PA
supported by the hardware.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat: stm32mp2: sysconf: fix CA35SS register names

Align register names with the reference manuel for Arm Cortex-A35 (CA35SS)
- CA35SS SYSCFG registers (with 0x2000 offset)
- CA35SS Standardized sta

plat: stm32mp2: sysconf: fix CA35SS register names

Align register names with the reference manuel for Arm Cortex-A35 (CA35SS)
- CA35SS SYSCFG registers (with 0x2000 offset)
- CA35SS Standardized status and control (SSC) registers

This path removes the confusion between SSC and subsystem (SS).

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Co-developed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: sysconfig: fix ordering of SYSCFG defines

Reorder SYSCFG defines to prepare renaming so the defines use the same
name as the one in the reference manual.

Signed-off-by: Thomas Bourgo

plat-stm32mp2: sysconfig: fix ordering of SYSCFG defines

Reorder SYSCFG defines to prepare renaming so the defines use the same
name as the one in the reference manual.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: implement do_reset() API to force a system reset

Implement the do_reset() API that traps all cores if the SoC has multiple
cores, then prints a message and forces a system reset.

Sig

plat-stm32mp1: implement do_reset() API to force a system reset

Implement the do_reset() API that traps all cores if the SoC has multiple
cores, then prints a message and forces a system reset.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: implement do_reset() API to force a system reset

Implement the do_reset() API that traps all cores if the SoC has multiple
cores, then prints a message and forces a system reset.

Sig

plat-stm32mp2: implement do_reset() API to force a system reset

Implement the do_reset() API that traps all cores if the SoC has multiple
cores, then prints a message and forces a system reset.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: panic: allow core halting on SGI in other cases than panic()

There may be cases where we want to halt several cores outside of a
panic() sequence.

Therefore, add CFG_MULTI_CORE_HALTING switch

core: panic: allow core halting on SGI in other cases than panic()

There may be cases where we want to halt several cores outside of a
panic() sequence.

Therefore, add CFG_MULTI_CORE_HALTING switch that allows to register
an interrupt handler for the CFG_HALT_CORES_SGI that is dedicated to
halt other cores.

This reduces the scope of CFG_HALT_CORES_ON_PANIC that is now used only
for halting other cores in a panic() sequence.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add RTC RIF configuration for the stm32mp257f-ev1 board

Add the RTC RIF configuration for the stm32mp257f-ev1 board.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Revi

dts: stm32: add RTC RIF configuration for the stm32mp257f-ev1 board

Add the RTC RIF configuration for the stm32mp257f-ev1 board.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_rtc: add the capability to wakeup the platform

During probe, we look for the property "wakeup-source" that
will trigger the feature "RTC_WAKEUP_ALARM" which will
be send to the caller

drivers: stm32_rtc: add the capability to wakeup the platform

During probe, we look for the property "wakeup-source" that
will trigger the feature "RTC_WAKEUP_ALARM" which will
be send to the callers of the framework `rtc_get_info()` PTA.

We also register the `stm32_rtc_alarm_wake_set_status()` callback.
This callback should be called when the callers knows that the platform
will go in sleep mode.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_rtc: add init configuration function

The init function aims to contains init configurations of the RTC
peripheral such as prescalers, config or calibration registers.
Add "CFG_STM32_H

drivers: stm32_rtc: add init configuration function

The init function aims to contains init configurations of the RTC
peripheral such as prescalers, config or calibration registers.
Add "CFG_STM32_HIGH_ACCURACY" (default to no) config to enable the
high accuracy mode which allow the highest refresh rate of the subsecond
register.
Also merge the functions `stm32_rtc_wait_sync()` with
`stm32_exit_init_mode()` as every stm32 exit init mode was followed
by a wait sync.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: enable async notif with GIC PPI 15

Enables OP-TEE async notif (asynchronous notification from OP-TEE
to the non-secure world) using GIC PPI 15 (GIC interrupt line 31).

Signed-off-by:

plat-stm32mp2: enable async notif with GIC PPI 15

Enables OP-TEE async notif (asynchronous notification from OP-TEE
to the non-secure world) using GIC PPI 15 (GIC interrupt line 31).

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: add support for RTC PTA

Compile the RTC PTA and the RTC driver if the RTC driver for stm32 is
enabled.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Et

plat-stm32mp2: add support for RTC PTA

Compile the RTC PTA and the RTC driver if the RTC driver for stm32 is
enabled.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp1: add support for RTC PTA

Compile the RTC PTA and the RTC driver if the RTC driver for stm32 is
enabled.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Et

plat-stm32mp1: add support for RTC PTA

Compile the RTC PTA and the RTC driver if the RTC driver for stm32 is
enabled.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-marvell: Add support for CN20K SoCs

Add support for Octeon20(CN20K) SoCs from Marvell.

Only tested 64-bit mode with default configurations:

1. Build command
make PLATFORM=marvell-cn20ka
mak

plat-marvell: Add support for CN20K SoCs

Add support for Octeon20(CN20K) SoCs from Marvell.

Only tested 64-bit mode with default configurations:

1. Build command
make PLATFORM=marvell-cn20ka
make PLATFORM=marvell-cnf20ka
2. Passed xtest

Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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Revert "plat-rockchip: rk3399: remove GIC configuration"

With commit 4cb77793842a ("irqchip/gic-v3: Fix rk3399 workaround when
secure interrupts are enabled") in the Linux kernel OP-TEE panics after

Revert "plat-rockchip: rk3399: remove GIC configuration"

With commit 4cb77793842a ("irqchip/gic-v3: Fix rk3399 workaround when
secure interrupts are enabled") in the Linux kernel OP-TEE panics after
the kernel has booted with:
E/TC:3 0 Panic 'Secure interrupt handler not defined' at core/kernel/interrupt.c:105 <interrupt_main_handler>

So for kernels after v6.14 we need another workaround. The easiest is to
revert commit 447c5f6bc49ff5408c0543ceaaabf0cb8f23804d. The GIC is still
broken, but the device is still usable in other aspects.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (rockchip-rk3399) (Rockpi4B)
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-corstone1000: increase CFG_TZDRAM_SIZE

TZDRAM is a 4MB SRAM in Corstone-1000. Its start address is `0x0200_0000`
but the first 0x2000 bytes are reserved for future use. `CFG_TZDRAM_SIZE`
can be

plat-corstone1000: increase CFG_TZDRAM_SIZE

TZDRAM is a 4MB SRAM in Corstone-1000. Its start address is `0x0200_0000`
but the first 0x2000 bytes are reserved for future use. `CFG_TZDRAM_SIZE`
can be increased to `0x360000` so OP-TEE has more RAM.

Signed-off-by: Bence Balogh <bence.balogh@arm.com>
Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: remove activation of RTC nodes at board level

Remove unnecessary activation of RTC in stm32mp15xxdkx.dtsi and
stm32mp135f-dk.dts.
RTC node is default enabled in stm32mp131.dtsi and stm32

dts: stm32: remove activation of RTC nodes at board level

Remove unnecessary activation of RTC in stm32mp15xxdkx.dtsi and
stm32mp135f-dk.dts.
RTC node is default enabled in stm32mp131.dtsi and stm32mp151.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: default enable RTC on stm32mp1

TAMP peripheral has a dependency on RTC.
Since TAMP is enable by default in stm32mp131.dtsi and stm32mp151.dtsi.
Default probe RTC to solve TAMP's dependen

dts: stm32: default enable RTC on stm32mp1

TAMP peripheral has a dependency on RTC.
Since TAMP is enable by default in stm32mp131.dtsi and stm32mp151.dtsi.
Default probe RTC to solve TAMP's dependency on it.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: enable Reset and Clock Controller for stm32mp215f-dk

Add device tree files for stm32mp215f-dk board.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Etienne C

dts: stm32: enable Reset and Clock Controller for stm32mp215f-dk

Add device tree files for stm32mp215f-dk board.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: update reset and clocks driver flags for STM32MP21

Add CFG_STM32MP21_CLK and CFG_STM32MP21_RSTCTRL flags to enable
RCC drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@fo

plat-stm32mp2: update reset and clocks driver flags for STM32MP21

Add CFG_STM32MP21_CLK and CFG_STM32MP21_RSTCTRL flags to enable
RCC drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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