core: add compile check for CFG_TEE_RAM_VA_SIZE

Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
[jf: add comment, modify error message]

core: add compile check for CFG_TEE_RAM_VA_SIZE

Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
[jf: add comment, modify error message]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: relax verify_special_mem_areas()

Relaxes verify_special_mem_areas() with regards to MEM_AREA_RAM_NSEC and
MEM_AREA_NSEC_SHM. Those two regions are from now on allowed to overlap
as any overlap

core: relax verify_special_mem_areas()

Relaxes verify_special_mem_areas() with regards to MEM_AREA_RAM_NSEC and
MEM_AREA_NSEC_SHM. Those two regions are from now on allowed to overlap
as any overlap there is harmless and more trouble than it's worth to
avoid.

Fixes problem with panic() when booting on FVP.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Fixes: 70cdca357de9 ("plat-vexpress: use register_nsec_ddr()")
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: rename TLB maintenance files

ssvce_aXX.S and tz_ssvce.h now only provide TLB maintenance support.
This change renames the source and header files accordingly.

Signed-off-by: Etienne Carr

core: arm: rename TLB maintenance files

ssvce_aXX.S and tz_ssvce.h now only provide TLB maintenance support.
This change renames the source and header files accordingly.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: ssvce_a32.S, ssvce_a64.S: remove useless includes/comments

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-b

core: arm: ssvce_a32.S, ssvce_a64.S: remove useless includes/comments

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: tz_ssvce.h: remove deprecated declarations

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklande

core: arm: tz_ssvce.h: remove deprecated declarations

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: imx: add 6ULL EVK support

Add i.MX6 ULL EVK support.
i.MX6ULL is derivative from i.MX6UL, so reuse some code for i.MX6UL.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Car

core: arm: imx: add 6ULL EVK support

Add i.MX6 ULL EVK support.
i.MX6ULL is derivative from i.MX6UL, so reuse some code for i.MX6UL.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: imx6ul: add platform early init code

Add platform early init code.

Configure ACTLR to enable SMP.
Configure NSACR to let NS could access cp10/cp11 and NS_SMP.

Signed-off-by: Peng Fan <p

core: arm: imx6ul: add platform early init code

Add platform early init code.

Configure ACTLR to enable SMP.
Configure NSACR to let NS could access cp10/cp11 and NS_SMP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx6ul: switch to use CFG_SECURE_TIME_SOURCE_REE

Switch to use CFG_SECURE_TIME_SOURCE_REE.
Since we do not have RTC, and arm counter will lose power when suspend,
we use CFG_SECURE_TIME_SOURCE

core: imx6ul: switch to use CFG_SECURE_TIME_SOURCE_REE

Switch to use CFG_SECURE_TIME_SOURCE_REE.
Since we do not have RTC, and arm counter will lose power when suspend,
we use CFG_SECURE_TIME_SOURCE_REE now.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: imx support psci off and affinity

Support psci off and affinity.
To i.MX6, CPU could not offline itself, so needs to use core0 to
offline other cores.

Introduce imx-common.c to include t

core: arm: imx support psci off and affinity

Support psci off and affinity.
To i.MX6, CPU could not offline itself, so needs to use core0 to
offline other cores.

Introduce imx-common.c to include the common code for i.MX family,
SRC operation is used by i.MX6/7, so move them to imx-common.c

Use CFG_BOOT_SECONDARY_REQUEST to wrap the psci_cpu_on/off/affinity
functions, these functions are only needed by SMP systems.To i.MX6UL,
they are not needed.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: imx: use one imx-regs.h file

Clean up to use one imx-regs.h for i.MX SoC family.
If there are different IP address, use CFG_MX6[Q,D,UL]
and etc to differentiate them.

Signed-off-by: Peng

core: arm: imx: use one imx-regs.h file

Clean up to use one imx-regs.h for i.MX SoC family.
If there are different IP address, use CFG_MX6[Q,D,UL]
and etc to differentiate them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: mx6ulevk: refine the tee address map

There is 512M DDR Memory on i.MX6UL-EVK board.
Reserve high 32M for TEE usage. The highest 2M for SHMEM.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
A

core: arm: mx6ulevk: refine the tee address map

There is 512M DDR Memory on i.MX6UL-EVK board.
Reserve high 32M for TEE usage. The highest 2M for SHMEM.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: psci: add helper functions

Add helper function psci_armv7_cpu_off.
This function will be used when use psci to offline a cpu.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etie

core: arm: psci: add helper functions

Add helper function psci_armv7_cpu_off.
This function will be used when use psci to offline a cpu.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix TODOs related to TLB maintenance in the pager

Invalidate TLBs for target references instead of invalidating the
whole tables.

Some changes affect places where several references are modif

core: fix TODOs related to TLB maintenance in the pager

Invalidate TLBs for target references instead of invalidating the
whole tables.

Some changes affect places where several references are modified and
must be invalidated in the TLBs. This change aims at lowering the
synchronization barrier required before/after the TLB maintenance
operations.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey AArch{32,64} pager)

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core: deprecate core_tlb_maintenance()

The core_tlb_maintenance() indirection is not useful. This function is
now deprecated and one shall straight call tlbi_xxx() function instead.

Signed-off-by:

core: deprecate core_tlb_maintenance()

The core_tlb_maintenance() indirection is not useful. This function is
now deprecated and one shall straight call tlbi_xxx() function instead.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix AArch64 implementation of tlbi_asid()

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add TLB invalidation by-mva-all-asid

tlbi_mva_allasid(): TLB invalidation by MVA for all ASID with all
synchronisation support.

tlbi_mva_allasid_nosync(): same invalidation but without the
sy

core: add TLB invalidation by-mva-all-asid

tlbi_mva_allasid(): TLB invalidation by MVA for all ASID with all
synchronisation support.

tlbi_mva_allasid_nosync(): same invalidation but without the
synchronization barriers.

Remove tlbi_mva_curasid that was disabled and not used.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: rename secure_mmu_unifiedtlbinvXXX() into tlbi_XXX()

secure_mmu_unifiedtlbinvall() => tlbi_all()
secure_mmu_unifiedtlbinv_byasid() => tlbi_asid()
secure_mmu_unifiedtlbinvbymva() => tlbi_mva_cu

core: rename secure_mmu_unifiedtlbinvXXX() into tlbi_XXX()

secure_mmu_unifiedtlbinvall() => tlbi_all()
secure_mmu_unifiedtlbinv_byasid() => tlbi_asid()
secure_mmu_unifiedtlbinvbymva() => tlbi_mva_curasid()

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: review TLB invalidation sequences

Align the AArch64 and AArch32 implementation of the TLB invalidation
sequences, mainly on synchronization barrier and implementation comments.

Signed-off-by:

core: review TLB invalidation sequences

Align the AArch64 and AArch32 implementation of the TLB invalidation
sequences, mainly on synchronization barrier and implementation comments.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove secure_mmu_unifiedtlbinv_curasid()

Remove duplicated code.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add tlbi and dsb instructions

Add 32bit and 64bit dsbish and dsbishst instructions.
Add 32bit write_tlbimvaais macro for TLB maintenance.

Signed-off-by: Etienne Carriere <etienne.carriere@lin

core: add tlbi and dsb instructions

Add 32bit and 64bit dsbish and dsbishst instructions.
Add 32bit write_tlbimvaais macro for TLB maintenance.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: assign non-sec DDR configuration from DT

Assigns non-secure DDR configuration from device tree if CFG_DT=y. Already
present DDR configuration from register_nsec_ddr() is overridden.

Reviewed-

core: assign non-sec DDR configuration from DT

Assigns non-secure DDR configuration from device tree if CFG_DT=y. Already
present DDR configuration from register_nsec_ddr() is overridden.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: use register_nsec_ddr()

Plat-vexpress uses register_nsec_ddr() to define the non-secure DDR
memory.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carri

plat-vexpress: use register_nsec_ddr()

Plat-vexpress uses register_nsec_ddr() to define the non-secure DDR
memory.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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ABI change: add OPTEE_MSG_ATTR_NONCONTIG handling

This patch introduces new attribute OPTEE_MSG_ATTR_NONCONTIG to allow
Normal World pass arbitrary list of physical pages as a shared buffer.

To rea

ABI change: add OPTEE_MSG_ATTR_NONCONTIG handling

This patch introduces new attribute OPTEE_MSG_ATTR_NONCONTIG to allow
Normal World pass arbitrary list of physical pages as a shared buffer.

To read this list of page address two new functions are added:
- msg_param_extract_pages() is a helper function that read pages list
into provided array

- msg_param_mobj_from_noncontig_param() constructs mobj from provided
struct optee_msg_param parameter. This mobj then can be used in
various parts of OP-TEE

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: update cache helpers

Updates AArch64 and ARMv7 cache helpers from lib/aarch32/cache_helpers.S
and lib/aarch64/cache_helpers.S in ARM-TF,
https://github.com/ARM-software/arm-trusted-firmware/tr

core: update cache helpers

Updates AArch64 and ARMv7 cache helpers from lib/aarch32/cache_helpers.S
and lib/aarch64/cache_helpers.S in ARM-TF,
https://github.com/ARM-software/arm-trusted-firmware/tree/2bd26faf62411c75111fea4b23c542865383b068

The imported routines only covers the inner cache. Already present ARMv7
cache routines are replaced by the new equivalent routines. The AArch64
routines are updated with the resent changes in ARM-TF.

The imported files are modified to better fit into OP-TEE, some
functions and defines are renamed.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey AArch{32,64} pager)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno AArch{32,64} pager)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32_macros.S: add cache related macros

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>