xref: /optee_os/core/arch/arm/plat-imx/imx-common.c (revision 552cad358e8ae5723dfbe468e624dc2975d987ec)
1 /*
2  * Copyright (C) 2016 Freescale Semiconductor, Inc.
3  * Copyright 2017 NXP
4  * All rights reserved.
5  *
6  * Peng Fan <peng.fan@nxp.com>
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions are met:
10  *
11  * 1. Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the following disclaimer.
13  *
14  * 2. Redistributions in binary form must reproduce the above copyright notice,
15  * this list of conditions and the following disclaimer in the documentation
16  * and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  * POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 #include <console.h>
32 #include <io.h>
33 #include <imx.h>
34 #include <mm/core_mmu.h>
35 #include <mm/core_memprot.h>
36 #include <platform_config.h>
37 
38 uint32_t imx_get_src_gpr(int cpu)
39 {
40 	vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC);
41 
42 	return read32(va + SRC_GPR1 + cpu * 8 + 4);
43 }
44 
45 void imx_set_src_gpr(int cpu, uint32_t val)
46 {
47 	vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC);
48 
49 	write32(val, va + SRC_GPR1 + cpu * 8 + 4);
50 }
51