core: always save non-secure vfp state

Prior to this patch the non-secure VFP state was only saved when it
seemed necessary based on control registers.

To make sure that non-secure VFP state isn't

core: always save non-secure vfp state

Prior to this patch the non-secure VFP state was only saved when it
seemed necessary based on control registers.

To make sure that non-secure VFP state isn't corrupted always save the
entire register file before modifying it. This is now the same behavior
on both ARMv8-A and ARMv7-A platforms.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: introduce is_unpaged() functions

Helper function to test if a virtual address points to an
unpaged memory section that is the linear address space when
pager is enabled.

When pager is disable

core: introduce is_unpaged() functions

Helper function to test if a virtual address points to an
unpaged memory section that is the linear address space when
pager is enabled.

When pager is disabled, is_unpaged() always returns true.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: pager: make sure __thread_enter_user_mode is unpaged

__thread_enter_user_mode() cannot be paged out, because the pager cannot
be invoked to restore any faulting code page after SP has b

core: arm64: pager: make sure __thread_enter_user_mode is unpaged

__thread_enter_user_mode() cannot be paged out, because the pager cannot
be invoked to restore any faulting code page after SP has been switched to
use SP_EL1. At this point, a synchronous exception would take the CPU to
the 0x200 offset in the exception vector, which corresponds to
[workaround_]el1_sync_sp1 and is an error-catching infinite loop. This
explains the behavior described in [1].

Add the requisite KEEP_PAGER so that the function is kept in the unpaged
area.

Fixes: [1] https://github.com/OP-TEE/optee_os/issues/2684
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: update boot image header script tool

Introduce the binary image type information to the STM32 header
used for OP-TEE boot images.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: update boot image header script tool

Introduce the binary image type information to the STM32 header
used for OP-TEE boot images.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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Remove Secure Element API support

There is probably no-one using the Secure Element API. We have never heard
anyone asking questions about it, have no way to test it and we believe
it is not even wo

Remove Secure Element API support

There is probably no-one using the Secure Element API. We have never heard
anyone asking questions about it, have no way to test it and we believe
it is not even working right now. Therefore, remove it.

- The reserved syscalls are still present, but return
TEE_ERROR_NOT_SUPPORTED
- The TEE_SE* functions (GlobalPlatform TEE Secure Element API,
GPD_SPE_024) are removed from libutee.a and the header file
tee_internal_se_api.h is removed as well

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-ls: NXP LX2160ARDB platform support is added

Added support for armv8 platform flavour.
- PLATFORM = ls-lx2160ardb

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Acked-by: Jerome Foris

plat-ls: NXP LX2160ARDB platform support is added

Added support for armv8 platform flavour.
- PLATFORM = ls-lx2160ardb

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-imx: add i.MX8MQ/MM EVK support

Add i.MX8MQ/MM EVK support.

i.MX8M family use Cortex-A53 as the CPU core, the i.MX8MQ EVK has
3GB DRAM memory, and i.MX8MM EVK has 2GB DRAM memory.

Signed-off-

plat-imx: add i.MX8MQ/MM EVK support

Add i.MX8MQ/MM EVK support.

i.MX8M family use Cortex-A53 as the CPU core, the i.MX8MQ EVK has
3GB DRAM memory, and i.MX8MM EVK has 2GB DRAM memory.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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tee: entry_fast: correct tee_entry_generic_get_api_call_count

There are actually 11 API calls in tee_entry_fast.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@

tee: entry_fast: correct tee_entry_generic_get_api_call_count

There are actually 11 API calls in tee_entry_fast.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: concurrent external and embedded DTBs

Introduce get_external_dt() as opposed to get_embedded_dt().

Change get_dt() to return embedded DTB location and falls back
to external DTB location.

Si

core: concurrent external and embedded DTBs

Introduce get_external_dt() as opposed to get_embedded_dt().

Change get_dt() to return embedded DTB location and falls back
to external DTB location.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: introduce get_embedded_dt()

get_embedded_dt() returns the location (virtual address) of the
embedded DTB or NULL if there is no embedded DTB.

Signed-off-by: Etienne Carriere <etienne.carriere

core: introduce get_embedded_dt()

get_embedded_dt() returns the location (virtual address) of the
embedded DTB or NULL if there is no embedded DTB.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: dt: discover memory before updating external DTB

When core updates the external DTB with OP-TEE node resources
it may load memory address ranges node that depend of information
read from the D

core: dt: discover memory before updating external DTB

When core updates the external DTB with OP-TEE node resources
it may load memory address ranges node that depend of information
read from the DTB. This change ensures non-secure memory is
discovered (possibly from the external DTB) before core modifies
the external DTB for a former boot stage.

Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: explicit external DTB scope in generic boot

Rename few functions, routines and variables dedicated to the
external DTB with an explicit `external_dt` labeling reference.

reset_dt_references()

core: explicit external DTB scope in generic boot

Rename few functions, routines and variables dedicated to the
external DTB with an explicit `external_dt` labeling reference.

reset_dt_references() is renamed release_external_dt() as more
explicit.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: rename get_dt_blob() into get_dt()

Rename get_dt_blob() into get_dt() to get some consistency in `dt`,
`dtb`, `fdt` labelling in generic_boot.c

Signed-off-by: Etienne Carriere <etienne.carrie

core: rename get_dt_blob() into get_dt()

Rename get_dt_blob() into get_dt() to get some consistency in `dt`,
`dtb`, `fdt` labelling in generic_boot.c

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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stm32mp1: add a platform banner

Platform banner stating platform flavor and embedded DTB if any.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissi

stm32mp1: add a platform banner

Platform banner stating platform flavor and embedded DTB if any.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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stm32mp1: device tree platform description

This change introduces the device tree source files describing boards
EV1 and ED1 and the related bindings.

The stm32mp1 DTS files and bindings header fil

stm32mp1: device tree platform description

This change introduces the device tree source files describing boards
EV1 and ED1 and the related bindings.

The stm32mp1 DTS files and bindings header files are dumped from
latest Linux kernel (v4.19). Bindings documentation is not stored in
OP-TEE OS source tree, one shall refer to the bindings documentation
from latest Linux kernel source tree.

Note that license terms where changed for binding header file gpio.h
to release them under dual 2-Clause DSB/GPLv2.0 instead of GPLv2.0 as
release in the Linux kernel.

Platform relies on DT source file (CFG_EMBED_DTB_SOURCE_FILE) to
distinguish between the platform flavors for the few configuration
directive that are static and cannot be provided only through FDT.

Default configuration locates the secure DDR area (TZDRAM) from
the base address of the last 32MBytes of the DDR over 30Mbyte.
The last 2MBytes of the DDR are the OP-TEE static shared memory.

Many contributors not listed below.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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stm32mp1: release constraint on core count

Minor cleaning and allow CFG_TEE_CORE_NB_CORE to be set to 1.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wik

stm32mp1: release constraint on core count

Minor cleaning and allow CFG_TEE_CORE_NB_CORE to be set to 1.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: generic_boot: Add init_dt_overlay()

This patch adds init_dt_overlay() into to the DT boot flow.

init_dt_overlay() operates in one of two ways.

1. By appending to a DT overlay passed from a p

core: generic_boot: Add init_dt_overlay()

This patch adds init_dt_overlay() into to the DT boot flow.

init_dt_overlay() operates in one of two ways.

1. By appending to a DT overlay passed from a prior boot stage such as ATF.
In this case OPTEE DT nodes will be appended to the existing DT overlay.

2. By creating an OPTEE specific DT overlay at CFG_DT_ADDR.

A subsequent boot phase must then pick up the DT overlay in-memory and
merge that overlay into a main DTB structure.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: generic_boot: Add device-tree fragments

This patch adds a call into add_dt_overlay_fragment() at
add_dt_path_subnode() affecting at the time of writing

- /firmware/optee
- /psci
- /memory/res

core: generic_boot: Add device-tree fragments

This patch adds a call into add_dt_overlay_fragment() at
add_dt_path_subnode() affecting at the time of writing

- /firmware/optee
- /psci
- /memory/reserved

if CFG_EXTERNAL_DTB_OVERLAY is defined then the set of OPTEE DTB entries is
treated as a set of DT overlay fragments to be populated into the specified
address at CFG_DTB_ADDR.

This allows ATF or u-boot to pass a blank DTB instead of a populated DTB
into OPTEE and for OPTEE then to return back a DTB with overlay fragments.

A subsequent boot stage can then merge the OPTEE provided overlay into the
main DTB.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: generic_boot: Add add_dt_overlay_fragment()

This patch adds a dt routine add_dt_overlay_fragment(). This purpose of
which is to encapsulate the dynamic FDT node entries OPTEE provides inside
o

core: generic_boot: Add add_dt_overlay_fragment()

This patch adds a dt routine add_dt_overlay_fragment(). This purpose of
which is to encapsulate the dynamic FDT node entries OPTEE provides inside
of a

fragment@0 {
target-path = "/";
__overlay__ {
/* OPTEE nodes go here */
};
};

A subsequent set of patches will wrapper up existing dynamic OPTEE nodes

- /firmware/optee
- /psci
- /reserved/memory
optee@0xaddress

Once done it will be possible for a DTB in memory to be populated
with OPTEE fragments and for a subsequent bootloader to merge the OPTEE
populated overlay into a DTB loaded by a later stage.

if CFG_EXTERNAL_DTB_OVERLAY is not defined then this code has no effect.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: generic_boot: Utilize add_dt_path_subnode where appropriate

This patch replaces some repetitive code of the form

offs = fdt_path_offset(fdt, "path");
if (offs < 0)
return -1;
offs = fdt_add_

core: generic_boot: Utilize add_dt_path_subnode where appropriate

This patch replaces some repetitive code of the form

offs = fdt_path_offset(fdt, "path");
if (offs < 0)
return -1;
offs = fdt_add_subnode(fdt, offs, "subnode");

with

offs = add_dt_path_subnode(fdt, "path", "subnode");

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: generic_boot: Add helper add_dt_path_subnode()

A common pattern in the DT code is

offs = fdt_path_offset(fdt, "/");
if (offs < 0)
return -1;
offs = fdt_add_subnode(fdt, offs, "newnode");
if

core: generic_boot: Add helper add_dt_path_subnode()

A common pattern in the DT code is

offs = fdt_path_offset(fdt, "/");
if (offs < 0)
return -1;
offs = fdt_add_subnode(fdt, offs, "newnode");
if (offs < 0)
return -1;

as was pointed out by Jerome in a related PR to-do with adding overlays
this is a candidate for functional decomposition.

This patch adds the necessary helper function.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Suggested-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: base TA store on scatter array

The TA store interface is now implemented using scatter array.

The priorities of the different TA store are also changed to use 2, 4
and 9 instead or 5, 9, 10 a

core: base TA store on scatter array

The TA store interface is now implemented using scatter array.

The priorities of the different TA store are also changed to use 2, 4
and 9 instead or 5, 9, 10 as they are now sorted alphabetically. The new
allocation makes it easier to stick something between "Secure Storage
TA" and the "REE" stores. It's doubtful that anyone would ever want to
make something higher priority than the "early TA" store, but just in
case a few numbers are reserved.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: base memory registration on scatter array

The register_*() macros are now implemented using scatter array.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissi

core: base memory registration on scatter array

The register_*() macros are now implemented using scatter array.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: base pseudo_ta_register() on scatter array

The pseudo_ta_register() implementation is now based on scatter array.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome

core: base pseudo_ta_register() on scatter array

The pseudo_ta_register() implementation is now based on scatter array.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: initcall.h use scattered array

Initcalls uses generic scattered array instead of special
implementation.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier

core: initcall.h use scattered array

Initcalls uses generic scattered array instead of special
implementation.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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