core: stmm: set panic flag when secure partition panics

Set the panic flag, that is in struct ta_ctx of the ts_ctx
(trusted service context) instance, when the secure partition
panics. This allows g

core: stmm: set panic flag when secure partition panics

Set the panic flag, that is in struct ta_ctx of the ts_ctx
(trusted service context) instance, when the secure partition
panics. This allows generic sequence to possibly release resources
related to the secure partition instance.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: stmm: support 32bit execution

Add support for 32bit EL0 secure partition StMM when Core is 32bit.

Defines 32bit FFA identifiers FFA_SVC_*_32 and FFA_MSG_*_32.
Defines SVC_REGS_Ax() macros to

core: stmm: support 32bit execution

Add support for 32bit EL0 secure partition StMM when Core is 32bit.

Defines 32bit FFA identifiers FFA_SVC_*_32 and FFA_MSG_*_32.
Defines SVC_REGS_Ax() macros to wrap 32b/64b thread_svc_regs structure
fields in StMM secure partition driver.
Defines __FFA_* local macros to wrap 32b/64b service IDs.

Save usr_sp banked register in return_helper() has it shall be preserved
when we will enter again the secure partition.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: stmm: fix storage syscalls return value

Fix the return value for the RPMB storage service where syscalls
returned a TEE_Result value instead of a STMM_RET_* value.

Fixes: 42471ecf25b7 ("core:

core: stmm: fix storage syscalls return value

Fix the return value for the RPMB storage service where syscalls
returned a TEE_Result value instead of a STMM_RET_* value.

Fixes: 42471ecf25b7 ("core: load stmm via secure partition")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: helper function to read 32bit usr_sp banked register

Helper function thread_get_usr_sp() allows Core threaded execution
to read usr_sp CPU register. This is needed as part of the secure
p

core: arm: helper function to read 32bit usr_sp banked register

Helper function thread_get_usr_sp() allows Core threaded execution
to read usr_sp CPU register. This is needed as part of the secure
partition execution context when a secure partition execution is
about to return to normal world.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: build: se050 driver

Core work to support building the platform independent se050 crypto
driver.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome@fori

core: build: se050 driver

Core work to support building the platform independent se050 crypto
driver.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-imx: conf: don't force CRYPTO_DRIVER

A platform independent driver could be providing the CRYPTO_DRIVER
functionality.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Etie

plat-imx: conf: don't force CRYPTO_DRIVER

A platform independent driver could be providing the CRYPTO_DRIVER
functionality.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-imx: conf: don't force SOFTWARE_PRNG

A platform independent driver could be providing a real RNG and
therefore have different requirements with respect to the PRNG.

Signed-off-by: Jorge Ramire

plat-imx: conf: don't force SOFTWARE_PRNG

A platform independent driver could be providing a real RNG and
therefore have different requirements with respect to the PRNG.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: scmi: remove unused references

SCMI power domain and performance monitoring protocols are not
implemented hence removing related references in STM32MP1 SCMI server.

Acked-by: Jerome

plat-stm32mp1: scmi: remove unused references

SCMI power domain and performance monitoring protocols are not
implemented hence removing related references in STM32MP1 SCMI server.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: scmi: make local arrays static

Change local structures to static attribute since not exported
outside scmi_server.c

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: E

plat-stm32mp1: scmi: make local arrays static

Change local structures to static attribute since not exported
outside scmi_server.c

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: scmi: handlers for STPMIC1 regulators

Add SCMI regulator platform handlers for regulators driven from STPMIC1
companion power chip.

STPMIC1 is under secure world exclusive access whe

plat-stm32mp1: scmi: handlers for STPMIC1 regulators

Add SCMI regulator platform handlers for regulators driven from STPMIC1
companion power chip.

STPMIC1 is under secure world exclusive access when its bus
interface is secure. In such case voltage regulators controller by
STPMIC1 can still be assigned to non-secure world control using SCMI
Voltage Domain protocol to expose services for these regulators.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: stub stm32mp_nsec_can_access_pmic_regu() when no PMIC

Define a stub implementation for stm32mp_nsec_can_access_pmic_regu()
when the platform does not embed its PMIC driver.

Acked-by:

plat-stm32mp1: stub stm32mp_nsec_can_access_pmic_regu() when no PMIC

Define a stub implementation for stm32mp_nsec_can_access_pmic_regu()
when the platform does not embed its PMIC driver.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: print "TEE load address" message on abort

Commit 02d307b7db90 ("core: use libunw") has involuntarily removed the
"TEE load address @ ..." message when a TEE core abort occurs. This
information

core: print "TEE load address" message on abort

Commit 02d307b7db90 ("core: use libunw") has involuntarily removed the
"TEE load address @ ..." message when a TEE core abort occurs. This
information is essential to be able to resolve function addresses when
ASLR is enabled, and scripts/symbolize.py needs this line. Add it back.

Fixes: 02d307b7db90 ("core: use libunw")
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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hikey: increase CFG_CORE_HEAP_SIZE from 64 to 72 KB

HiKey 620 uses the default core heap size which is 64 KB. This seems to
be a bit small now and the likely reason of some IBART failures [1]:

283

hikey: increase CFG_CORE_HEAP_SIZE from 64 to 72 KB

HiKey 620 uses the default core heap size which is 64 KB. This seems to
be a bit small now and the likely reason of some IBART failures [1]:

2833: regression_6018.2 OK
2834: o regression_6018.3 Storage id: 80000100
[...]
2846: E/TC:? 0 TA panicked with code 0xffff000c

Increase the size to 72 KB.

Link: [1] https://optee.mooo.com:5000/logs/OP-TEE/build/441/518642707/65112f06d1ffdd93762acdd1d8a8a06e9bebdd1d
Signed-off-by: Jerome Forissier <jerome@forissier.org>

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core: move non TA specific fields from user_ta_ctx

Moves fields from user_ta_ctx to user_mode_ctx, which are not specific
to user TAs. This is needed to prepare for handling Secure Partitions,
user_

core: move non TA specific fields from user_ta_ctx

Moves fields from user_ta_ctx to user_mode_ctx, which are not specific
to user TAs. This is needed to prepare for handling Secure Partitions,
user_mode_ctx will be the common ground for the fields used by both TAs
and SPs.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: extract ldelf related code from user_ta.c

Moves ldelf functionality from user_ta.c to a separate file.
This is the first step for decoupling ldelf from user TAs.

Reviewed-by: Jens Wiklander <

core: extract ldelf related code from user_ta.c

Moves ldelf functionality from user_ta.c to a separate file.
This is the first step for decoupling ldelf from user TAs.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: pass user_mode_ctx to thread_user_clear_vfp()

Changes the parameter type of thread_user_clear_vfp() to struct
user_mode_ctx. This makes using the function more convenient, now it
doesn't have

core: pass user_mode_ctx to thread_user_clear_vfp()

Changes the parameter type of thread_user_clear_vfp() to struct
user_mode_ctx. This makes using the function more convenient, now it
doesn't have to be surrounded with conditional directives on each use.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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drivers: imx_i2c: move utility macros

Move I2C utility macros (driver specific) from SoC specific register
definition files to the driver.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Re

drivers: imx_i2c: move utility macros

Move I2C utility macros (driver specific) from SoC specific register
definition files to the driver.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: imx_i2c: add support for imx6ull

Support native I2C access on imx6ull (this SoC has an additional
register - compared to the imx8mm - to configure the daisy chain in
the iomuxc).

A patch [

drivers: imx_i2c: add support for imx6ull

Support native I2C access on imx6ull (this SoC has an additional
register - compared to the imx8mm - to configure the daisy chain in
the iomuxc).

A patch [1] has been sent to U-boot to address their current release
as of Oct 23, 2020 - where the peripheral clock is still set to 66MHz
instead of 24MHz.

Tested on imx6ull-evk 14x14 with the bus at 400Kbps.
[1] https://lists.denx.de/pipermail/u-boot/2020-October/430482.html

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: add secure partitions store

SPs need to be started as part of the initialisation process of the
OP-TEE kernel. The secure partition store uses the embedded_ts store to
load SPs

Signed-off-by:

core: add secure partitions store

SPs need to be started as part of the initialisation process of the
OP-TEE kernel. The secure partition store uses the embedded_ts store to
load SPs

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: move early_ta implementation to embedded_ts

Ealy_ta's are similar to embedded SPs. Move all shared logic to the
embedded_ts.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens W

core: move early_ta implementation to embedded_ts

Ealy_ta's are similar to embedded SPs. Move all shared logic to the
embedded_ts.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: create embedded_ts

Create an embedded ts struct which will encapsulate both early_ta's
and embedded SPs.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wikla

core: create embedded_ts

Create an embedded ts struct which will encapsulate both early_ta's
and embedded SPs.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: rename ta_store to ts_store

Rename the ta_store to the ts_store. We will need the stores to load
SPs (secure partitions). By renaming ta_store to ts_store
(trusted service) we indicate that th

core: rename ta_store to ts_store

Rename the ta_store to the ts_store. We will need the stores to load
SPs (secure partitions). By renaming ta_store to ts_store
(trusted service) we indicate that the stores are not only used by the
TAs but that they can also be used by SPs.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: rename secure_partition to stmm_sp

The current secure partition code is used for the stmm SP. Rename it so
we can start integrating the FF-A secure partitions.

Backwards compatibility is main

core: rename secure_partition to stmm_sp

The current secure partition code is used for the stmm SP. Rename it so
we can start integrating the FF-A secure partitions.

Backwards compatibility is maintained when CFG_STMM_PATH is used to
enable support for STMM. The internal configuration flag
CFG_WITH_SECURE_PARTITION is renamed to CFG_WITH_STMM_SP.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>

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core: replace tee_mmu prefix with vm

Replaces the tee_mmu prefix with vm. tee_mmu.h is renamed to vm.h and
core/arch/arm/mm/tee_mmu.c is moved to core/mm/vm.c. Public functions
belonging to these fi

core: replace tee_mmu prefix with vm

Replaces the tee_mmu prefix with vm. tee_mmu.h is renamed to vm.h and
core/arch/arm/mm/tee_mmu.c is moved to core/mm/vm.c. Public functions
belonging to these files are renamed with a vm prefix.

Introduces: vm_map_param(), vm_clean_param(),
vm_buf_is_inside_private(), vm_buf_intersects_private(),
vm_buf_to_mboj_offs(), vm_buf_is_inside_um_private(),
vm_buf_intersects_um_private(), vm_add_rwmem(), vm_rem_rwmem(),
vm_va2pa(), vm_pa2va(), vm_check_access_rights(), vm_set_ctx() replacing
their tee_mmu_*() counterpart.

Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: rename to core_mmu_init_ta_ram()

Renames teecore_init_ta_ram() to core_mmu_init_ta_ram() and moves it
to core_mmu.c.

Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier

core: rename to core_mmu_init_ta_ram()

Renames teecore_init_ta_ram() to core_mmu_init_ta_ram() and moves it
to core_mmu.c.

Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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