1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * (c) 2020 Jorge Ramirez <jorge@foundries.io>, Foundries Ltd. 4 */ 5 #include <arm.h> 6 #include <drivers/imx_i2c.h> 7 #include <initcall.h> 8 #include <io.h> 9 #include <kernel/delay.h> 10 #include <mm/core_memprot.h> 11 #include <mm/core_mmu.h> 12 #include <platform_config.h> 13 #include <stdlib.h> 14 #include <trace.h> 15 #include <util.h> 16 17 #define I2C_CLK_RATE 24000000 /* Bits per second */ 18 19 /* SoC optional: iomuxc daisy configuration register */ 20 #ifndef I2C_INP_SCL 21 #define I2C_INP_SCL(__x) 0 22 #define I2C_INP_SDA(__x) 0 23 #define I2C_INP_VAL(__x) 0 24 #endif 25 26 /* SoC optional: clock gate bitmask */ 27 #ifndef I2C_CLK_CGRBM 28 #define I2C_CLK_CGRBM(__x) 0 29 #endif 30 31 static struct io_pa_va i2c_bus[] = { 32 { .pa = I2C1_BASE, }, 33 { .pa = I2C2_BASE, }, 34 { .pa = I2C3_BASE, }, 35 }; 36 37 static struct imx_i2c_clk { 38 struct io_pa_va base; 39 uint32_t i2c[ARRAY_SIZE(i2c_bus)]; 40 uint32_t cgrbm[ARRAY_SIZE(i2c_bus)]; 41 } i2c_clk = { 42 .base.pa = CCM_BASE, 43 .i2c = { I2C_CLK_CGR(1), I2C_CLK_CGR(2), I2C_CLK_CGR(3), }, 44 .cgrbm = { I2C_CLK_CGRBM(1), I2C_CLK_CGRBM(2), I2C_CLK_CGRBM(3), }, 45 }; 46 47 static struct imx_i2c_mux { 48 struct io_pa_va base; 49 struct imx_i2c_mux_regs { 50 uint32_t scl_mux; 51 uint32_t scl_cfg; 52 uint32_t scl_inp; 53 uint32_t sda_mux; 54 uint32_t sda_cfg; 55 uint32_t sda_inp; 56 } i2c[ARRAY_SIZE(i2c_bus)]; 57 } i2c_mux = { 58 .base.pa = IOMUXC_BASE, 59 .i2c = {{ .scl_mux = I2C_MUX_SCL(1), .scl_cfg = I2C_CFG_SCL(1), 60 .scl_inp = I2C_INP_SCL(1), .sda_mux = I2C_MUX_SDA(1), 61 .sda_cfg = I2C_CFG_SDA(1), .sda_inp = I2C_INP_SDA(1), }, 62 { .scl_mux = I2C_MUX_SCL(2), .scl_cfg = I2C_CFG_SCL(2), 63 .scl_inp = I2C_INP_SCL(2), .sda_mux = I2C_MUX_SDA(2), 64 .sda_cfg = I2C_CFG_SDA(2), .sda_inp = I2C_INP_SDA(2), }, 65 { .scl_mux = I2C_MUX_SCL(3), .scl_cfg = I2C_CFG_SCL(3), 66 .scl_inp = I2C_INP_SCL(3), .sda_mux = I2C_MUX_SDA(3), 67 .sda_cfg = I2C_CFG_SDA(3), .sda_inp = I2C_INP_SDA(3), },}, 68 }; 69 70 #define I2DR 0x10 71 #define I2SR 0x0C 72 #define I2CR 0x08 73 #define IFDR 0x04 74 75 #define I2CR_IEN BIT(7) 76 #define I2CR_IIEN BIT(6) 77 #define I2CR_MSTA BIT(5) 78 #define I2CR_MTX BIT(4) 79 #define I2CR_TX_NO_AK BIT(3) 80 #define I2CR_RSTA BIT(2) 81 82 #define I2SR_ICF BIT(7) 83 #define I2SR_IBB BIT(5) 84 #define I2SR_IAL BIT(4) 85 #define I2SR_IIF BIT(1) 86 #define I2SR_RX_NO_AK BIT(0) 87 88 static uint8_t i2c_io_read8(uint8_t bid, uint32_t address) 89 { 90 return io_read8(i2c_bus[bid].va + address); 91 } 92 93 static void i2c_io_write8(uint8_t bid, uint32_t address, uint8_t data) 94 { 95 return io_write8(i2c_bus[bid].va + address, data); 96 } 97 98 static bool bus_is_idle(uint32_t sr) 99 { 100 return (sr & I2SR_IBB) == 0; 101 } 102 103 static bool bus_is_busy(uint32_t sr) 104 { 105 return !bus_is_idle(sr); 106 } 107 108 static bool isr_active(uint32_t sr) 109 { 110 return (sr & I2SR_IIF) == I2SR_IIF; 111 } 112 113 static struct ifdr_pair { 114 uint32_t divider; 115 uint8_t prescaler; 116 } ifdr_table[] = { 117 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 118 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 119 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 120 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 121 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 122 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 123 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 124 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 125 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 126 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 127 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 128 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 129 { 3072, 0x1E }, { 3840, 0x1F } 130 }; 131 132 static void i2c_set_prescaler(uint8_t bid, uint32_t bps) 133 { 134 struct ifdr_pair *p = ifdr_table; 135 struct ifdr_pair *q = p + ARRAY_SIZE(ifdr_table) - 1; 136 uint32_t div = (I2C_CLK_RATE + bps - 1) / bps; 137 138 if (div < p->divider) 139 q = p; 140 else if (div > q->divider) 141 p = q; 142 143 while (p != q) { 144 if (div <= p->divider) 145 break; 146 p++; 147 } 148 149 i2c_io_write8(bid, IFDR, p->prescaler); 150 } 151 152 static void i2c_set_bus_speed(uint8_t bid, int bps) 153 { 154 vaddr_t addr = i2c_clk.base.va; 155 uint32_t val = 0; 156 157 #if defined(CFG_MX8MM) 158 addr += CCM_CCGRx_SET(i2c_clk.i2c[bid]); 159 val = CCM_CCGRx_ALWAYS_ON(0); 160 #elif defined(CFG_MX6ULL) 161 addr += i2c_clk.i2c[bid]; 162 val = i2c_clk.cgrbm[bid] | io_read32(addr); 163 #endif 164 io_write32(addr, val); 165 i2c_set_prescaler(bid, bps); 166 } 167 168 static TEE_Result i2c_sync_bus(uint8_t bid, bool (*match)(uint32_t), 169 uint32_t *status) 170 { 171 uint64_t tref = timeout_init_us(100000); 172 uint32_t sr = 0; 173 174 while (!timeout_elapsed(tref)) { 175 sr = i2c_io_read8(bid, I2SR); 176 if (sr & I2SR_IAL) { 177 EMSG("bus arbitration lost"); 178 i2c_io_write8(bid, I2SR, sr & ~I2SR_IAL); 179 return TEE_ERROR_COMMUNICATION; 180 } 181 if ((*match)(sr)) { 182 if (status) 183 *status = sr; 184 return TEE_SUCCESS; 185 } 186 } 187 188 return TEE_ERROR_BUSY; 189 } 190 191 static TEE_Result i2c_idle_bus(uint8_t bid) 192 { 193 uint8_t tmp = i2c_io_read8(bid, I2CR) & ~I2CR_MSTA; 194 TEE_Result ret = TEE_SUCCESS; 195 196 i2c_io_write8(bid, I2CR, tmp); 197 ret = i2c_sync_bus(bid, &bus_is_idle, NULL); 198 i2c_io_write8(bid, I2SR, 0); 199 200 return ret; 201 } 202 203 static TEE_Result i2c_write_byte(uint8_t bid, uint8_t byte) 204 { 205 TEE_Result ret = TEE_SUCCESS; 206 uint32_t status = 0; 207 208 i2c_io_write8(bid, I2DR, byte); 209 ret = i2c_sync_bus(bid, &isr_active, &status); 210 i2c_io_write8(bid, I2SR, 0); 211 212 if (!ret && (status & I2SR_RX_NO_AK)) 213 return TEE_ERROR_BAD_STATE; 214 215 return ret; 216 } 217 218 static TEE_Result i2c_read_byte(uint8_t bid, uint8_t *p) 219 { 220 TEE_Result ret = TEE_SUCCESS; 221 222 *p = i2c_io_read8(bid, I2DR); 223 ret = i2c_sync_bus(bid, &isr_active, NULL); 224 i2c_io_write8(bid, I2SR, 0); 225 226 return ret; 227 } 228 229 static TEE_Result i2c_write_data(uint8_t bid, const uint8_t *buf, int len) 230 { 231 TEE_Result ret = TEE_SUCCESS; 232 uint32_t tmp = 0; 233 234 if (!len) 235 return TEE_SUCCESS; 236 237 tmp = i2c_io_read8(bid, I2CR) | I2CR_MTX | I2CR_TX_NO_AK; 238 i2c_io_write8(bid, I2CR, tmp); 239 240 while (len--) { 241 ret = i2c_write_byte(bid, *buf++); 242 if (ret) 243 return ret; 244 } 245 246 return ret; 247 } 248 249 static TEE_Result i2c_read_data(uint8_t bid, uint8_t *buf, int len) 250 { 251 TEE_Result ret = TEE_SUCCESS; 252 uint8_t dummy = 0; 253 uint32_t tmp = 0; 254 255 if (!len) 256 return TEE_SUCCESS; 257 258 tmp = i2c_io_read8(bid, I2CR) & ~I2CR_MTX; 259 tmp = (len == 1) ? tmp | I2CR_TX_NO_AK : tmp & ~I2CR_TX_NO_AK; 260 i2c_io_write8(bid, I2CR, tmp); 261 i2c_io_read8(bid, I2DR); 262 263 ret = i2c_read_byte(bid, &dummy); 264 if (ret) 265 return ret; 266 267 /* 268 * A data transfer ends when the master signals a stop; for a master 269 * receiver to terminate a transfer it must inform the slave transmiter 270 * by not acknowledging the last data byte. This is done by setting the 271 * transmit acknowledge bit before reading the next-to-last byte. 272 */ 273 do { 274 if (len == 2) { 275 tmp = i2c_io_read8(bid, I2CR) | I2CR_TX_NO_AK; 276 i2c_io_write8(bid, I2CR, tmp); 277 } 278 279 ret = i2c_read_byte(bid, buf++); 280 if (ret) 281 return ret; 282 } while (len--); 283 284 return ret; 285 } 286 287 static TEE_Result i2c_init_transfer(uint8_t bid, uint8_t chip) 288 { 289 TEE_Result ret = TEE_SUCCESS; 290 uint32_t tmp = 0; 291 292 ret = i2c_idle_bus(bid); 293 if (ret) 294 return ret; 295 296 /* Enable the interface */ 297 i2c_io_write8(bid, I2CR, I2CR_IEN); 298 299 tmp = i2c_io_read8(bid, I2CR) | I2CR_MSTA; 300 i2c_io_write8(bid, I2CR, tmp); 301 302 /* Wait until the bus is active */ 303 ret = i2c_sync_bus(bid, &bus_is_busy, NULL); 304 if (ret) 305 return ret; 306 307 /* Slave address on the bus */ 308 return i2c_write_data(bid, &chip, 1); 309 } 310 311 TEE_Result imx_i2c_read(uint8_t bid, uint8_t chip, uint8_t *buf, int len) 312 { 313 TEE_Result ret = TEE_SUCCESS; 314 315 if (bid >= ARRAY_SIZE(i2c_bus)) 316 return TEE_ERROR_BAD_PARAMETERS; 317 318 if ((len && !buf) || chip > 0x7F) 319 return TEE_ERROR_BAD_PARAMETERS; 320 321 ret = i2c_init_transfer(bid, chip << 1 | BIT(0)); 322 if (!ret) 323 ret = i2c_read_data(bid, buf, len); 324 325 if (i2c_idle_bus(bid)) 326 IMSG("bus not idle"); 327 328 return ret; 329 } 330 331 TEE_Result imx_i2c_write(uint8_t bid, uint8_t chip, const uint8_t *buf, int len) 332 { 333 TEE_Result ret = TEE_SUCCESS; 334 335 if (bid >= ARRAY_SIZE(i2c_bus)) 336 return TEE_ERROR_BAD_PARAMETERS; 337 338 if ((len && !buf) || chip > 0x7F) 339 return TEE_ERROR_BAD_PARAMETERS; 340 341 ret = i2c_init_transfer(bid, chip << 1); 342 if (!ret) 343 ret = i2c_write_data(bid, buf, len); 344 345 if (i2c_idle_bus(bid)) 346 IMSG("bus not idle"); 347 348 return ret; 349 } 350 351 TEE_Result imx_i2c_probe(uint8_t bid, uint8_t chip) 352 { 353 if (bid >= ARRAY_SIZE(i2c_bus)) 354 return TEE_ERROR_BAD_PARAMETERS; 355 356 if (chip > 0x7F) 357 return TEE_ERROR_BAD_PARAMETERS; 358 359 return imx_i2c_write(bid, chip, NULL, 0); 360 } 361 362 /* 363 * I2C bus initialization: configure the IOMUX and enable the clock. 364 * @bid: Bus ID: (0=I2C1), (1=I2C2), (2=I2C3). 365 * @bps: Bus baud rate, in bits per second. 366 */ 367 TEE_Result imx_i2c_init(uint8_t bid, int bps) 368 { 369 struct imx_i2c_mux *mux = &i2c_mux; 370 371 if (bid >= ARRAY_SIZE(i2c_bus)) 372 return TEE_ERROR_BAD_PARAMETERS; 373 374 if (!bps) 375 return TEE_ERROR_BAD_PARAMETERS; 376 377 io_write32(mux->base.va + mux->i2c[bid].scl_mux, I2C_MUX_VAL(bid)); 378 io_write32(mux->base.va + mux->i2c[bid].scl_cfg, I2C_CFG_VAL(bid)); 379 if (mux->i2c[bid].scl_inp) 380 io_write32(mux->base.va + mux->i2c[bid].scl_inp, 381 I2C_INP_VAL(mux->i2c[bid].scl_inp)); 382 383 io_write32(mux->base.va + mux->i2c[bid].sda_mux, I2C_MUX_VAL(bid)); 384 io_write32(mux->base.va + mux->i2c[bid].sda_cfg, I2C_CFG_VAL(bid)); 385 if (mux->i2c[bid].sda_inp) 386 io_write32(mux->base.va + mux->i2c[bid].sda_inp, 387 I2C_INP_VAL(mux->i2c[bid].sda_inp)); 388 389 /* Baud rate in bits per second */ 390 i2c_set_bus_speed(bid, bps); 391 392 return TEE_SUCCESS; 393 } 394 395 static TEE_Result get_va(paddr_t pa, vaddr_t *va) 396 { 397 if (!core_mmu_add_mapping(MEM_AREA_IO_SEC, pa, 0x10000)) 398 return TEE_ERROR_GENERIC; 399 400 *va = (vaddr_t)phys_to_virt(pa, MEM_AREA_IO_SEC); 401 if (*va) 402 return TEE_SUCCESS; 403 404 return TEE_ERROR_GENERIC; 405 } 406 407 static TEE_Result i2c_init(void) 408 { 409 size_t n = 0; 410 411 if (get_va(i2c_clk.base.pa, &i2c_clk.base.va)) 412 return TEE_ERROR_GENERIC; 413 414 if (get_va(i2c_mux.base.pa, &i2c_mux.base.va)) 415 return TEE_ERROR_GENERIC; 416 417 for (n = 0; n < ARRAY_SIZE(i2c_bus); n++) { 418 if (get_va(i2c_bus[n].pa, &i2c_bus[n].va)) 419 return TEE_ERROR_GENERIC; 420 } 421 422 return TEE_SUCCESS; 423 } 424 425 early_init(i2c_init); 426