1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <drivers/scmi-msg.h> 8 #include <drivers/scmi.h> 9 #include <drivers/stm32mp1_pmic.h> 10 #include <drivers/stm32mp1_pwr.h> 11 #include <drivers/stpmic1.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/regulator/st,stm32mp15-regulator.h> 14 #include <dt-bindings/reset/stm32mp1-resets.h> 15 #include <initcall.h> 16 #include <mm/core_memprot.h> 17 #include <mm/core_mmu.h> 18 #include <platform_config.h> 19 #include <stdint.h> 20 #include <speculation_barrier.h> 21 #include <stm32_util.h> 22 #include <string.h> 23 #include <tee_api_defines.h> 24 #include <util.h> 25 26 #define TIMEOUT_US_1MS 1000 27 28 #define SCMI_CLOCK_NAME_SIZE 16 29 #define SCMI_RD_NAME_SIZE 16 30 #define SCMI_VOLTD_NAME_SIZE 16 31 32 /* 33 * struct stm32_scmi_clk - Data for the exposed clock 34 * @clock_id: Clock identifier in RCC clock driver 35 * @name: Clock string ID exposed to agent 36 * @enabled: State of the SCMI clock 37 */ 38 struct stm32_scmi_clk { 39 unsigned long clock_id; 40 const char *name; 41 bool enabled; 42 }; 43 44 /* 45 * struct stm32_scmi_rd - Data for the exposed reset controller 46 * @reset_id: Reset identifier in RCC reset driver 47 * @name: Reset string ID exposed to agent 48 */ 49 struct stm32_scmi_rd { 50 unsigned long reset_id; 51 const char *name; 52 }; 53 54 enum voltd_device { 55 VOLTD_PWR, 56 VOLTD_PMIC, 57 }; 58 59 /* 60 * struct stm32_scmi_voltd - Data for the exposed voltage domains 61 * @name: Power regulator string ID exposed to agent 62 * @priv_id: Internal string ID for the regulator 63 * @priv_dev: Internal ID for the device implementing the regulator 64 */ 65 struct stm32_scmi_voltd { 66 const char *name; 67 const char *priv_id; 68 enum voltd_device priv_dev; 69 70 }; 71 72 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 73 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 74 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 75 #define SMT_BUFFER1_BASE (SMT_BUFFER_BASE + 0x200) 76 77 #if (SMT_BUFFER1_BASE + SMT_BUF_SLOT_SIZE > \ 78 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 79 #error "SCMI shared memory mismatch" 80 #endif 81 82 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 83 CFG_STM32MP1_SCMI_SHM_SIZE); 84 85 static struct scmi_msg_channel scmi_channel[] = { 86 [0] = { 87 .agent_name = "stm32mp1-agent-0", 88 .shm_addr = { .pa = SMT_BUFFER0_BASE, }, 89 .shm_size = SMT_BUF_SLOT_SIZE, 90 }, 91 [1] = { 92 .agent_name = "stm32mp1-agent-1", 93 .shm_addr = { .pa = SMT_BUFFER1_BASE, }, 94 .shm_size = SMT_BUF_SLOT_SIZE, 95 }, 96 }; 97 98 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id) 99 { 100 assert(agent_id < ARRAY_SIZE(scmi_channel)); 101 102 return &scmi_channel[agent_id]; 103 } 104 105 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 106 [_scmi_id] = { \ 107 .clock_id = _id, \ 108 .name = _name, \ 109 .enabled = _init_enabled, \ 110 } 111 112 struct stm32_scmi_clk stm32_scmi0_clock[] = { 113 CLOCK_CELL(CK_SCMI0_HSE, CK_HSE, "ck_hse", true), 114 CLOCK_CELL(CK_SCMI0_HSI, CK_HSI, "ck_hsi", true), 115 CLOCK_CELL(CK_SCMI0_CSI, CK_CSI, "ck_csi", true), 116 CLOCK_CELL(CK_SCMI0_LSE, CK_LSE, "ck_lse", true), 117 CLOCK_CELL(CK_SCMI0_LSI, CK_LSI, "ck_lsi", true), 118 CLOCK_CELL(CK_SCMI0_PLL2_Q, PLL2_Q, "pll2_q", true), 119 CLOCK_CELL(CK_SCMI0_PLL2_R, PLL2_R, "pll2_r", true), 120 CLOCK_CELL(CK_SCMI0_MPU, CK_MPU, "ck_mpu", true), 121 CLOCK_CELL(CK_SCMI0_AXI, CK_AXI, "ck_axi", true), 122 CLOCK_CELL(CK_SCMI0_BSEC, BSEC, "bsec", true), 123 CLOCK_CELL(CK_SCMI0_CRYP1, CRYP1, "cryp1", false), 124 CLOCK_CELL(CK_SCMI0_GPIOZ, GPIOZ, "gpioz", false), 125 CLOCK_CELL(CK_SCMI0_HASH1, HASH1, "hash1", false), 126 CLOCK_CELL(CK_SCMI0_I2C4, I2C4_K, "i2c4_k", false), 127 CLOCK_CELL(CK_SCMI0_I2C6, I2C6_K, "i2c6_k", false), 128 CLOCK_CELL(CK_SCMI0_IWDG1, IWDG1, "iwdg1", false), 129 CLOCK_CELL(CK_SCMI0_RNG1, RNG1_K, "rng1_k", true), 130 CLOCK_CELL(CK_SCMI0_RTC, RTC, "ck_rtc", true), 131 CLOCK_CELL(CK_SCMI0_RTCAPB, RTCAPB, "rtcapb", true), 132 CLOCK_CELL(CK_SCMI0_SPI6, SPI6_K, "spi6_k", false), 133 CLOCK_CELL(CK_SCMI0_USART1, USART1_K, "usart1_k", false), 134 }; 135 136 struct stm32_scmi_clk stm32_scmi1_clock[] = { 137 CLOCK_CELL(CK_SCMI1_PLL3_Q, PLL3_Q, "pll3_q", true), 138 CLOCK_CELL(CK_SCMI1_PLL3_R, PLL3_R, "pll3_r", true), 139 CLOCK_CELL(CK_SCMI1_MCU, CK_MCU, "ck_mcu", false), 140 }; 141 142 #define RESET_CELL(_scmi_id, _id, _name) \ 143 [_scmi_id] = { \ 144 .reset_id = _id, \ 145 .name = _name, \ 146 } 147 148 struct stm32_scmi_rd stm32_scmi0_reset_domain[] = { 149 RESET_CELL(RST_SCMI0_SPI6, SPI6_R, "spi6"), 150 RESET_CELL(RST_SCMI0_I2C4, I2C4_R, "i2c4"), 151 RESET_CELL(RST_SCMI0_I2C6, I2C6_R, "i2c6"), 152 RESET_CELL(RST_SCMI0_USART1, USART1_R, "usart1"), 153 RESET_CELL(RST_SCMI0_STGEN, STGEN_R, "stgen"), 154 RESET_CELL(RST_SCMI0_GPIOZ, GPIOZ_R, "gpioz"), 155 RESET_CELL(RST_SCMI0_CRYP1, CRYP1_R, "cryp1"), 156 RESET_CELL(RST_SCMI0_HASH1, HASH1_R, "hash1"), 157 RESET_CELL(RST_SCMI0_RNG1, RNG1_R, "rng1"), 158 RESET_CELL(RST_SCMI0_MDMA, MDMA_R, "mdma"), 159 RESET_CELL(RST_SCMI0_MCU, MCU_R, "mcu"), 160 RESET_CELL(RST_SCMI0_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 161 }; 162 163 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _name) \ 164 [_scmi_id] = { \ 165 .priv_id = (_priv_id), \ 166 .priv_dev = (_dev_id), \ 167 .name = (_name), \ 168 } 169 170 #define PWR_REG11_NAME_ID "0" 171 #define PWR_REG18_NAME_ID "1" 172 #define PWR_USB33_NAME_ID "2" 173 174 struct stm32_scmi_voltd scmi0_voltage_domain[] = { 175 VOLTD_CELL(VOLTD_SCMI0_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 176 VOLTD_CELL(VOLTD_SCMI0_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 177 VOLTD_CELL(VOLTD_SCMI0_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 178 }; 179 180 struct scmi_agent_resources { 181 struct stm32_scmi_clk *clock; 182 size_t clock_count; 183 struct stm32_scmi_rd *rd; 184 size_t rd_count; 185 struct stm32_scmi_pd *pd; 186 size_t pd_count; 187 struct stm32_scmi_perfs *perfs; 188 size_t perfs_count; 189 struct stm32_scmi_voltd *voltd; 190 size_t voltd_count; 191 }; 192 193 const struct scmi_agent_resources agent_resources[] = { 194 [0] = { 195 .clock = stm32_scmi0_clock, 196 .clock_count = ARRAY_SIZE(stm32_scmi0_clock), 197 .rd = stm32_scmi0_reset_domain, 198 .rd_count = ARRAY_SIZE(stm32_scmi0_reset_domain), 199 .voltd = scmi0_voltage_domain, 200 .voltd_count = ARRAY_SIZE(scmi0_voltage_domain), 201 }, 202 [1] = { 203 .clock = stm32_scmi1_clock, 204 .clock_count = ARRAY_SIZE(stm32_scmi1_clock), 205 }, 206 }; 207 208 static const struct scmi_agent_resources *find_resource(unsigned int agent_id) 209 { 210 assert(agent_id < ARRAY_SIZE(agent_resources)); 211 212 return &agent_resources[agent_id]; 213 } 214 215 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 216 { 217 unsigned int n = 0; 218 unsigned int count = 0; 219 const size_t agent_count = ARRAY_SIZE(agent_resources); 220 221 for (n = 0; n < agent_count; n++) 222 if (agent_resources[n].clock_count) 223 break; 224 if (n < agent_count) 225 count++; 226 227 for (n = 0; n < agent_count; n++) 228 if (agent_resources[n].rd_count) 229 break; 230 if (n < agent_count) 231 count++; 232 233 for (n = 0; n < agent_count; n++) 234 if (agent_resources[n].pd_count) 235 break; 236 if (n < agent_count) 237 count++; 238 239 for (n = 0; n < agent_count; n++) 240 if (agent_resources[n].perfs_count) 241 break; 242 if (n < agent_count) 243 count++; 244 245 for (n = 0; n < agent_count; n++) 246 if (agent_resources[n].voltd_count) 247 break; 248 if (n < agent_count) 249 count++; 250 251 return count; 252 } 253 254 static const char vendor[] = "ST"; 255 static const char sub_vendor[] = ""; 256 257 const char *plat_scmi_vendor_name(void) 258 { 259 return vendor; 260 } 261 262 const char *plat_scmi_sub_vendor_name(void) 263 { 264 return sub_vendor; 265 } 266 267 /* Currently supporting Clocks and Reset Domains */ 268 static const uint8_t plat_protocol_list[] = { 269 SCMI_PROTOCOL_ID_CLOCK, 270 SCMI_PROTOCOL_ID_RESET_DOMAIN, 271 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 272 0 /* Null termination */ 273 }; 274 275 size_t plat_scmi_protocol_count(void) 276 { 277 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 278 279 assert(count == plat_scmi_protocol_count_paranoid()); 280 281 return count; 282 } 283 284 const uint8_t *plat_scmi_protocol_list(unsigned int agent_id __unused) 285 { 286 assert(plat_scmi_protocol_count_paranoid() == 287 (ARRAY_SIZE(plat_protocol_list) - 1)); 288 289 return plat_protocol_list; 290 } 291 292 /* 293 * Platform SCMI clocks 294 */ 295 static struct stm32_scmi_clk *find_clock(unsigned int agent_id, 296 unsigned int scmi_id) 297 { 298 const struct scmi_agent_resources *resource = find_resource(agent_id); 299 size_t n = 0; 300 301 if (resource) { 302 for (n = 0; n < resource->clock_count; n++) 303 if (n == scmi_id) 304 return &resource->clock[n]; 305 } 306 307 return NULL; 308 } 309 310 size_t plat_scmi_clock_count(unsigned int agent_id) 311 { 312 const struct scmi_agent_resources *resource = find_resource(agent_id); 313 314 if (!resource) 315 return 0; 316 317 return resource->clock_count; 318 } 319 320 const char *plat_scmi_clock_get_name(unsigned int agent_id, 321 unsigned int scmi_id) 322 { 323 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 324 325 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 326 return NULL; 327 328 return clock->name; 329 } 330 331 int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id, 332 size_t start_index, unsigned long *array, 333 size_t *nb_elts) 334 { 335 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 336 337 if (!clock) 338 return SCMI_NOT_FOUND; 339 340 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 341 return SCMI_DENIED; 342 343 /* Exposed clocks are currently fixed rate clocks */ 344 if (start_index) 345 return SCMI_INVALID_PARAMETERS; 346 347 if (!array) 348 *nb_elts = 1; 349 else if (*nb_elts == 1) 350 *array = stm32_clock_get_rate(clock->clock_id); 351 else 352 return SCMI_GENERIC_ERROR; 353 354 return SCMI_SUCCESS; 355 } 356 357 unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, 358 unsigned int scmi_id) 359 { 360 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 361 362 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 363 return 0; 364 365 return stm32_clock_get_rate(clock->clock_id); 366 } 367 368 int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id) 369 { 370 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 371 372 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 373 return 0; 374 375 return (int32_t)clock->enabled; 376 } 377 378 int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id, 379 bool enable_not_disable) 380 { 381 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 382 383 if (!clock) 384 return SCMI_NOT_FOUND; 385 386 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 387 return SCMI_DENIED; 388 389 if (enable_not_disable) { 390 if (!clock->enabled) { 391 DMSG("SCMI clock %u enable", scmi_id); 392 stm32_clock_enable(clock->clock_id); 393 clock->enabled = true; 394 } 395 } else { 396 if (clock->enabled) { 397 DMSG("SCMI clock %u disable", scmi_id); 398 stm32_clock_disable(clock->clock_id); 399 clock->enabled = false; 400 } 401 } 402 403 return SCMI_SUCCESS; 404 } 405 406 /* 407 * Platform SCMI reset domains 408 */ 409 static struct stm32_scmi_rd *find_rd(unsigned int agent_id, 410 unsigned int scmi_id) 411 { 412 const struct scmi_agent_resources *resource = find_resource(agent_id); 413 size_t n = 0; 414 415 if (resource) { 416 for (n = 0; n < resource->rd_count; n++) 417 if (n == scmi_id) 418 return &resource->rd[n]; 419 } 420 421 return NULL; 422 } 423 424 const char *plat_scmi_rd_get_name(unsigned int agent_id, unsigned int scmi_id) 425 { 426 const struct stm32_scmi_rd *rd = find_rd(agent_id, scmi_id); 427 428 if (!rd) 429 return NULL; 430 431 return rd->name; 432 } 433 434 size_t plat_scmi_rd_count(unsigned int agent_id) 435 { 436 const struct scmi_agent_resources *resource = find_resource(agent_id); 437 438 if (!resource) 439 return 0; 440 441 return resource->rd_count; 442 } 443 444 int32_t plat_scmi_rd_autonomous(unsigned int agent_id, unsigned int scmi_id, 445 uint32_t state) 446 { 447 const struct stm32_scmi_rd *rd = find_rd(agent_id, scmi_id); 448 449 if (!rd) 450 return SCMI_NOT_FOUND; 451 452 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 453 return SCMI_DENIED; 454 455 if (rd->reset_id == MCU_HOLD_BOOT_R) 456 return SCMI_NOT_SUPPORTED; 457 458 /* Supports only reset with context loss */ 459 if (state) 460 return SCMI_NOT_SUPPORTED; 461 462 DMSG("SCMI reset %u cycle", scmi_id); 463 464 if (stm32_reset_assert(rd->reset_id, TIMEOUT_US_1MS)) 465 return SCMI_HARDWARE_ERROR; 466 467 if (stm32_reset_deassert(rd->reset_id, TIMEOUT_US_1MS)) 468 return SCMI_HARDWARE_ERROR; 469 470 return SCMI_SUCCESS; 471 } 472 473 int32_t plat_scmi_rd_set_state(unsigned int agent_id, unsigned int scmi_id, 474 bool assert_not_deassert) 475 { 476 const struct stm32_scmi_rd *rd = find_rd(agent_id, scmi_id); 477 478 if (!rd) 479 return SCMI_NOT_FOUND; 480 481 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 482 return SCMI_DENIED; 483 484 if (rd->reset_id == MCU_HOLD_BOOT_R) { 485 DMSG("SCMI MCU hold boot %s", 486 assert_not_deassert ? "set" : "release"); 487 stm32_reset_assert_deassert_mcu(assert_not_deassert); 488 return SCMI_SUCCESS; 489 } 490 491 if (assert_not_deassert) { 492 DMSG("SCMI reset %u set", scmi_id); 493 stm32_reset_set(rd->reset_id); 494 } else { 495 DMSG("SCMI reset %u release", scmi_id); 496 stm32_reset_release(rd->reset_id); 497 } 498 499 return SCMI_SUCCESS; 500 } 501 502 /* 503 * Platform SCMI voltage domains 504 */ 505 static struct stm32_scmi_voltd *find_voltd(unsigned int agent_id, 506 unsigned int scmi_id) 507 { 508 const struct scmi_agent_resources *resource = find_resource(agent_id); 509 size_t n = 0; 510 511 if (resource) { 512 for (n = 0; n < resource->voltd_count; n++) 513 if (n == scmi_id) 514 return &resource->voltd[n]; 515 } 516 517 return NULL; 518 } 519 520 size_t plat_scmi_voltd_count(unsigned int agent_id) 521 { 522 const struct scmi_agent_resources *resource = find_resource(agent_id); 523 524 if (!resource) 525 return 0; 526 527 return resource->voltd_count; 528 } 529 530 const char *plat_scmi_voltd_get_name(unsigned int agent_id, 531 unsigned int scmi_id) 532 { 533 struct stm32_scmi_voltd *voltd = find_voltd(agent_id, scmi_id); 534 535 /* Currently non-secure is allowed to access all PWR regulators */ 536 if (!voltd) 537 return NULL; 538 539 return voltd->name; 540 } 541 542 static enum pwr_regulator pwr_scmi_to_regu_id(struct stm32_scmi_voltd *voltd) 543 { 544 if (!strcmp(voltd->priv_id, PWR_REG11_NAME_ID)) 545 return PWR_REG11; 546 if (!strcmp(voltd->priv_id, PWR_REG18_NAME_ID)) 547 return PWR_REG18; 548 if (!strcmp(voltd->priv_id, PWR_USB33_NAME_ID)) 549 return PWR_USB33; 550 551 panic(); 552 } 553 554 static long pwr_get_level(struct stm32_scmi_voltd *voltd) 555 { 556 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 557 558 return (long)stm32mp1_pwr_regulator_mv(regu_id) * 1000; 559 } 560 561 static int32_t pwr_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 562 { 563 if (level_uv != pwr_get_level(voltd)) 564 return SCMI_INVALID_PARAMETERS; 565 566 return SCMI_SUCCESS; 567 } 568 569 static int32_t pwr_describe_levels(struct stm32_scmi_voltd *voltd, 570 size_t start_index, long *microvolt, 571 size_t *nb_elts) 572 { 573 if (start_index) 574 return SCMI_INVALID_PARAMETERS; 575 576 if (!microvolt) { 577 *nb_elts = 1; 578 return SCMI_SUCCESS; 579 } 580 581 if (*nb_elts < 1) 582 return SCMI_GENERIC_ERROR; 583 584 *nb_elts = 1; 585 *microvolt = pwr_get_level(voltd); 586 587 return SCMI_SUCCESS; 588 } 589 590 static uint32_t pwr_get_state(struct stm32_scmi_voltd *voltd) 591 { 592 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 593 594 if (stm32mp1_pwr_regulator_is_enabled(regu_id)) 595 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 596 597 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 598 } 599 600 static void pwr_set_state(struct stm32_scmi_voltd *voltd, bool enable) 601 { 602 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 603 604 DMSG("%sable PWR %s (was %s)", enable ? "En" : "Dis", voltd->name, 605 stm32mp1_pwr_regulator_is_enabled(regu_id) ? "on" : "off"); 606 607 stm32mp1_pwr_regulator_set_state(regu_id, enable); 608 } 609 610 static int32_t pmic_describe_levels(struct stm32_scmi_voltd *voltd, 611 size_t start_index, long *microvolt, 612 size_t *nb_elts) 613 { 614 const uint16_t *levels = NULL; 615 size_t full_count = 0; 616 size_t out_count = 0; 617 size_t i = 0; 618 619 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 620 return SCMI_DENIED; 621 622 stpmic1_regulator_levels_mv(voltd->priv_id, &levels, &full_count); 623 624 if (!microvolt) { 625 *nb_elts = full_count - start_index; 626 return SCMI_SUCCESS; 627 } 628 629 if (SUB_OVERFLOW(full_count, start_index, &out_count)) 630 return SCMI_GENERIC_ERROR; 631 632 out_count = MIN(out_count, *nb_elts); 633 634 FMSG("%zu levels: start %zu requested %zu output %zu", 635 full_count, start_index, *nb_elts, out_count); 636 637 for (i = 0; i < out_count; i++) 638 microvolt[i] = levels[start_index + i] * 1000; 639 640 *nb_elts = out_count; 641 642 return SCMI_SUCCESS; 643 } 644 645 static long pmic_get_level(struct stm32_scmi_voltd *voltd) 646 { 647 unsigned long level_mv = 0; 648 649 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 650 return 0; 651 652 stm32mp_get_pmic(); 653 level_mv = stpmic1_regulator_voltage_get(voltd->priv_id); 654 stm32mp_put_pmic(); 655 656 return (long)level_mv * 1000; 657 } 658 659 static int32_t pmic_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 660 { 661 int rc = 0; 662 unsigned int level_mv = 0; 663 664 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 665 return SCMI_DENIED; 666 667 if (level_uv < 0 || level_uv > (UINT16_MAX * 1000)) 668 return SCMI_INVALID_PARAMETERS; 669 670 level_mv = (unsigned int)level_uv / 1000; 671 672 DMSG("Set STPMIC1 regulator %s level to %dmV", voltd->name, level_mv); 673 674 stm32mp_get_pmic(); 675 rc = stpmic1_regulator_voltage_set(voltd->priv_id, level_mv); 676 stm32mp_put_pmic(); 677 678 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 679 } 680 681 static uint32_t pmic_get_state(struct stm32_scmi_voltd *voltd) 682 { 683 bool enabled = false; 684 685 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 686 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 687 688 stm32mp_get_pmic(); 689 enabled = stpmic1_is_regulator_enabled(voltd->priv_id); 690 stm32mp_put_pmic(); 691 692 if (enabled) 693 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 694 695 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 696 } 697 698 static int32_t pmic_set_state(struct stm32_scmi_voltd *voltd, bool enable) 699 { 700 int rc = 0; 701 702 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 703 return SCMI_DENIED; 704 705 stm32mp_get_pmic(); 706 707 DMSG("%sable STPMIC1 %s (was %s)", enable ? "En" : "Dis", voltd->name, 708 stpmic1_is_regulator_enabled(voltd->priv_id) ? "on" : "off"); 709 710 if (enable) 711 rc = stpmic1_regulator_enable(voltd->priv_id); 712 else 713 rc = stpmic1_regulator_disable(voltd->priv_id); 714 715 stm32mp_put_pmic(); 716 717 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 718 } 719 720 int32_t plat_scmi_voltd_levels_array(unsigned int agent_id, 721 unsigned int scmi_id, size_t start_index, 722 long *levels, size_t *nb_elts) 723 724 { 725 struct stm32_scmi_voltd *voltd = find_voltd(agent_id, scmi_id); 726 727 if (!voltd) 728 return SCMI_NOT_FOUND; 729 730 switch (voltd->priv_dev) { 731 case VOLTD_PWR: 732 return pwr_describe_levels(voltd, start_index, levels, nb_elts); 733 case VOLTD_PMIC: 734 return pmic_describe_levels(voltd, start_index, levels, 735 nb_elts); 736 default: 737 return SCMI_GENERIC_ERROR; 738 } 739 } 740 741 long plat_scmi_voltd_get_level(unsigned int agent_id, unsigned int scmi_id) 742 { 743 struct stm32_scmi_voltd *voltd = find_voltd(agent_id, scmi_id); 744 745 if (!voltd) 746 return 0; 747 748 switch (voltd->priv_dev) { 749 case VOLTD_PWR: 750 return pwr_get_level(voltd); 751 case VOLTD_PMIC: 752 return pmic_get_level(voltd); 753 default: 754 panic(); 755 } 756 } 757 758 int32_t plat_scmi_voltd_set_level(unsigned int agent_id, unsigned int scmi_id, 759 long level) 760 { 761 struct stm32_scmi_voltd *voltd = find_voltd(agent_id, scmi_id); 762 763 if (!voltd) 764 return SCMI_NOT_FOUND; 765 766 switch (voltd->priv_dev) { 767 case VOLTD_PWR: 768 return pwr_set_level(voltd, level); 769 case VOLTD_PMIC: 770 return pmic_set_level(voltd, level); 771 default: 772 return SCMI_GENERIC_ERROR; 773 } 774 } 775 776 int32_t plat_scmi_voltd_get_config(unsigned int agent_id, unsigned int scmi_id, 777 uint32_t *config) 778 { 779 struct stm32_scmi_voltd *voltd = find_voltd(agent_id, scmi_id); 780 781 if (!voltd) 782 return SCMI_NOT_FOUND; 783 784 switch (voltd->priv_dev) { 785 case VOLTD_PWR: 786 *config = pwr_get_state(voltd); 787 break; 788 case VOLTD_PMIC: 789 *config = pmic_get_state(voltd); 790 break; 791 default: 792 return SCMI_GENERIC_ERROR; 793 } 794 795 return SCMI_SUCCESS; 796 } 797 798 int32_t plat_scmi_voltd_set_config(unsigned int agent_id, unsigned int scmi_id, 799 uint32_t config) 800 { 801 struct stm32_scmi_voltd *voltd = find_voltd(agent_id, scmi_id); 802 int32_t rc = SCMI_SUCCESS; 803 804 if (!voltd) 805 return SCMI_NOT_FOUND; 806 807 switch (voltd->priv_dev) { 808 case VOLTD_PWR: 809 pwr_set_state(voltd, config); 810 break; 811 case VOLTD_PMIC: 812 rc = pmic_set_state(voltd, config); 813 break; 814 default: 815 return SCMI_GENERIC_ERROR; 816 } 817 818 return rc; 819 } 820 821 /* 822 * Initialize platform SCMI resources 823 */ 824 static TEE_Result stm32mp1_init_scmi_server(void) 825 { 826 size_t i = 0; 827 size_t j = 0; 828 829 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 830 struct scmi_msg_channel *chan = &scmi_channel[i]; 831 832 /* Enforce non-secure shm mapped as device memory */ 833 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 834 MEM_AREA_IO_NSEC); 835 assert(chan->shm_addr.va); 836 837 scmi_smt_init_agent_channel(chan); 838 } 839 840 for (i = 0; i < ARRAY_SIZE(agent_resources); i++) { 841 const struct scmi_agent_resources *res = &agent_resources[i]; 842 843 for (j = 0; j < res->clock_count; j++) { 844 struct stm32_scmi_clk *clk = &res->clock[j]; 845 846 if (!clk->name || 847 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 848 panic("SCMI clock name invalid"); 849 850 /* Sync SCMI clocks with their targeted initial state */ 851 if (clk->enabled && 852 stm32mp_nsec_can_access_clock(clk->clock_id)) 853 stm32_clock_enable(clk->clock_id); 854 } 855 856 for (j = 0; j < res->rd_count; j++) { 857 struct stm32_scmi_rd *rd = &res->rd[j]; 858 859 if (!rd->name || 860 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 861 panic("SCMI reset domain name invalid"); 862 } 863 864 for (j = 0; j < res->voltd_count; j++) { 865 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 866 867 if (!voltd->name || 868 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 869 panic("SCMI voltage domain name invalid"); 870 } 871 } 872 873 return TEE_SUCCESS; 874 } 875 876 driver_init_late(stm32mp1_init_scmi_server); 877