dts: stm32mp15: bump to Linux v5.19-rc6 dts files
Synchronize with stm32mp15 dts(i) files from Linux v5.19-rc6.

Changes made to imported dts(i) files:
- stm32mp151.dtsi: add ETZPC node, declare PSCI

dts: stm32mp15: bump to Linux v5.19-rc6 dts files
Synchronize with stm32mp15 dts(i) files from Linux v5.19-rc6.

Changes made to imported dts(i) files:
- stm32mp151.dtsi: add ETZPC node, declare PSCI v1.0.
- stm32mp151.dtsi: add iwdg1 node as before
- stm32mp151.dtsi: add iwdg2 interrupt definition
- stm32mp151.dtsi: add tamp node clocks definition
- stm32mp151.dtsi: keep pin-controller{,-z} node names
- stm32mp157a-dk1.dts: disable RCC secure-status.
- stm32mp157c-dk2.dts: disable RCC secure-status.
- stm32mp157c-dk2.dts: drop cryp1 okay status
- stm32mp157c-ed1.dts (included by ev1): disable RCC secure-status.
- stm32mp157c-ed1.dts: (included by ev1): drop cryp1 okay status
- Remove resources related to input DT bindings using explicit inline
comments as those are under Linux kernel GPLv2 licensing model.

This update is required to add a new board based on Linux 5.19-rc6
dts file.

Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-totalcompute: Introduce TC2

Added TC2 platform support

Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Fo

plat-totalcompute: Introduce TC2

Added TC2 platform support

Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm: Switch to hw_get_random_bytes()

hw_get_random_byte() is no longer used. The default crypto_rng_read()
calls hw_get_random_bytes() now so implement just hw_get_random_bytes().

Signed-off-b

plat-stm: Switch to hw_get_random_bytes()

hw_get_random_byte() is no longer used. The default crypto_rng_read()
calls hw_get_random_bytes() now so implement just hw_get_random_bytes().

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-rcar: Switch to hw_get_random_bytes()

hw_get_random_byte() is no longer used. The default crypto_rng_read()
calls hw_get_random_bytes() now so implement just hw_get_random_bytes().

Signed-off-

plat-rcar: Switch to hw_get_random_bytes()

hw_get_random_byte() is no longer used. The default crypto_rng_read()
calls hw_get_random_bytes() now so implement just hw_get_random_bytes().

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-k3: Switch to hw_get_random_bytes()

hw_get_random_byte() is no longer used. The default crypto_rng_read()
calls hw_get_random_bytes() now so implement just hw_get_random_bytes().

Signed-off-by

plat-k3: Switch to hw_get_random_bytes()

hw_get_random_byte() is no longer used. The default crypto_rng_read()
calls hw_get_random_bytes() now so implement just hw_get_random_bytes().

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-k3: Factor out sa2ul_rng_read128()

The core function is a 128bit RNG read. Factor this out into
its own function to help with the switch to hw_get_random_bytes().

Signed-off-by: Andrew Davis <

plat-k3: Factor out sa2ul_rng_read128()

The core function is a 128bit RNG read. Factor this out into
its own function to help with the switch to hw_get_random_bytes().

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plar: rcar: Use common crypto_rng_read() over hw_get_random_byte()

This has the same effect and removes the last user of
hw_get_random_byte() allowing us to start converting platforms
to hw_get_rand

plar: rcar: Use common crypto_rng_read() over hw_get_random_byte()

This has the same effect and removes the last user of
hw_get_random_byte() allowing us to start converting platforms
to hw_get_random_bytes() and removing hw_get_random_byte().

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-rcar: Software PRNG should be disabled when using hardware generator

On RCAR_GEN3 platforms, a hardware random number generator is available
and the HWRNG_PTA is enabled. For this to work right

plat-rcar: Software PRNG should be disabled when using hardware generator

On RCAR_GEN3 platforms, a hardware random number generator is available
and the HWRNG_PTA is enabled. For this to work right the software PRNG
should be disabled.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_gpio: temporary GPIO configuration for STM32MP13

This temporary change set all configured GPIOs to non-secure state
on STM32MP13 platform. This change is needed while we align all
com

drivers: stm32_gpio: temporary GPIO configuration for STM32MP13

This temporary change set all configured GPIOs to non-secure state
on STM32MP13 platform. This change is needed while we align all
components.

Changes I2C driver to assign I2C pins to secure world for STM32MP13.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: temporary ETZPC configuration

As device-tree configuration for the ETZPC is not yet handled,
add a temporary configuration in the platform main.

Signed-off-by: Gatien Chevallier <gat

plat-stm32mp1: temporary ETZPC configuration

As device-tree configuration for the ETZPC is not yet handled,
add a temporary configuration in the platform main.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: add APB6 memory mapping

This patch adds the secure memory mapping for APB6.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.ca

plat-stm32mp1: add APB6 memory mapping

This patch adds the secure memory mapping for APB6.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: define specific STM32MP13 peripheral addresses

Some peripheral addresses differ from STM32MP15 to STM32MP13.
This change adds support for those differences.

Signed-off-by: Gatien Che

plat-stm32mp1: define specific STM32MP13 peripheral addresses

Some peripheral addresses differ from STM32MP15 to STM32MP13.
This change adds support for those differences.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: tzc400: support STM32MP13

On STM32MP13 platforms, there is only one TZC filter unit.
Therefore, differentiate the TZC_FILTERS_MASK from the STM32MP15,
which has two.

Signed-off-by: G

plat-stm32mp1: tzc400: support STM32MP13

On STM32MP13 platforms, there is only one TZC filter unit.
Therefore, differentiate the TZC_FILTERS_MASK from the STM32MP15,
which has two.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: conf: introduce STM32MP13 configuration

This change introduces STM32MP13 minimal configuration and
differentiates STM32MP15 platform from the STM32MP13 one by enabling
or disabling sp

plat-stm32mp1: conf: introduce STM32MP13 configuration

This change introduces STM32MP13 minimal configuration and
differentiates STM32MP15 platform from the STM32MP13 one by enabling
or disabling specific switches.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: CFG_TZSRAM_START may not be defined

STM32MP13 SoCs do not use internal RAM to run OP-TEE hence do not
define CFG_TZSRAM_START/SIZE for that platform.

Signed-off-by: Gatien Chevallier

plat-stm32mp1: CFG_TZSRAM_START may not be defined

STM32MP13 SoCs do not use internal RAM to run OP-TEE hence do not
define CFG_TZSRAM_START/SIZE for that platform.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: conf: set variant config before common default configs

Moves definition of variant config (MP15/MP13) to conf.mk file top,
before common switches default initialization. This is more

plat-stm32mp1: conf: set variant config before common default configs

Moves definition of variant config (MP15/MP13) to conf.mk file top,
before common switches default initialization. This is more flexible
to define target specific configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: conf: implement switch list for CFG_STM32MP15|13

CFG_STM32MP15 and CFG_STM32MP13 are part of a configuration choice list,
one and one only of the items shall be enabled.

Highlight th

plat-stm32mp1: conf: implement switch list for CFG_STM32MP15|13

CFG_STM32MP15 and CFG_STM32MP13 are part of a configuration choice list,
one and one only of the items shall be enabled.

Highlight that with an inline comment and some logic. The default target
is CFG_STM32MP15 for backward compatibility.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: conf: introduce STM32MP1 flavorlists

Add flavorlist-MP13 to list boards currently supported for the
STM32MP13 SoC.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Re

plat-stm32mp1: conf: introduce STM32MP1 flavorlists

Add flavorlist-MP13 to list boards currently supported for the
STM32MP13 SoC.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: support STM32MP13 gpio bank resources

STM32MP13 platform does not support the same amount of GPIO bank.

Always define the util functions. Support STM32MP13 and STM32MP15.

Signed-off

plat-stm32mp1: support STM32MP13 gpio bank resources

STM32MP13 platform does not support the same amount of GPIO bank.

Always define the util functions. Support STM32MP13 and STM32MP15.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: scmi_server update for STM32MP13

Update the SCMI server to support STM32MP13 and its SCMI domains: clock,
reset and voltage.

This change also remove the '0' index to the SCMI domains

plat-stm32mp1: scmi_server update for STM32MP13

Update the SCMI server to support STM32MP13 and its SCMI domains: clock,
reset and voltage.

This change also remove the '0' index to the SCMI domains in order to
align with Linux kernel.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: add initial support of STM32MP135F-DK board

Add support of STM32MP135F discovery board (part number:
STM32MP135F-DK) that integrates a STM32MP135F SoC with 512 MB of DDR3.

The board pro

dts: stm32: add initial support of STM32MP135F-DK board

Add support of STM32MP135F discovery board (part number:
STM32MP135F-DK) that integrates a STM32MP135F SoC with 512 MB of DDR3.

The board provides SDcard and USB mass storage as persistent storage
device interfaces.

Co-developed-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: add STM32MP13 SoCs support

Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is
composed by:
- STM32MP131:
-core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX
-st

dts: stm32: add STM32MP13 SoCs support

Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is
composed by:
- STM32MP131:
-core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX
-storage: 3*SDMCC, 1*QSPI, FMC
-com: USB (OHCI/EHCI, OTG), 5*I2C, 5*SPI/I2S, 8*U(S)ART
-audio: 2*SAI
-network: 1*ETH(GMAC)
-STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
-STM32MP135: STM32MP133 + DCMIPP, LTDC

Co-developed-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Disable SA2UL RNG driver on unsupported flavors

Only enable the SA2UL TRNG on platform flavors that are currently
supported. This can be relaxed for platforms as support is verifie

plat-k3: drivers: Disable SA2UL RNG driver on unsupported flavors

Only enable the SA2UL TRNG on platform flavors that are currently
supported. This can be relaxed for platforms as support is verified.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: kernel: fix rpc shm free when prealloc is disable

Fixes commit [1] that changed implementation of the standard invocation
SMC command to introduce invocation with RPC shared memory refere

core: arm: kernel: fix rpc shm free when prealloc is disable

Fixes commit [1] that changed implementation of the standard invocation
SMC command to introduce invocation with RPC shared memory reference.
A wrong logic was implemented to free RPC buffer on standard invocation
completion. This change fixes that by freeing the cached shared memory
when pre-allocation is disable by config switch or runtime service.

Fixes: feb290a51087 ("core: add OPTEE_SMC_CALL_WITH_RPC_ARG")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: plat-ls: correct expression CFG_NUM_THREADS ?= CFG_TEE_CORE_NB_CORE

There was no parenthesis around CFG_TEE_CORE_NB_CORE
when assigning it to CFG_NUM_THREADS, so corrected it.

Signed-off-by:

core: plat-ls: correct expression CFG_NUM_THREADS ?= CFG_TEE_CORE_NB_CORE

There was no parenthesis around CFG_TEE_CORE_NB_CORE
when assigning it to CFG_NUM_THREADS, so corrected it.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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