plat-k3: drivers: ti-sci: Add support for setting device state

This adds support for the TI-SCI TI_SCI_MSG_SET_DEVICE_STATE message.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Foriss

plat-k3: drivers: ti-sci: Add support for setting device state

This adds support for the TI-SCI TI_SCI_MSG_SET_DEVICE_STATE message.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: clk: remove stm32_clock_*() helpers

Removes function that were deprecated: stm32_clock_is_enabled(),
stm32_clock_enable(), stm32_clock_disable() and stm32_clock_get_rate().

Signed-off-by:

drivers: clk: remove stm32_clock_*() helpers

Removes function that were deprecated: stm32_clock_is_enabled(),
stm32_clock_enable(), stm32_clock_disable() and stm32_clock_get_rate().

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: armv7: fix ASLR error

With commit 528dabb28254 ("core: suppress text relocation on
stack_tmp_export") the stack pointer is calculated using a relative
address instead of based on an absolute a

core: armv7: fix ASLR error

With commit 528dabb28254 ("core: suppress text relocation on
stack_tmp_export") the stack pointer is calculated using a relative
address instead of based on an absolute address which is relocated with
ASLR enabled.

Prior to this on Armv7 we compensate for a relocation update for
stack_tmp_export_rel in reset_secondary() just after the stack pointer
was initialized. So now when the relocation update of stack_tmp_export_rel
is gone remove the compensating code too.

Fixes: 528dabb28254 ("core: suppress text relocation on stack_tmp_export")
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: sp: handle memory regions w/o base address

The FF-A spec states that in the SP manifest a base address is not
mandatory for memory regions. If the field is not present, the specified
memory re

core: sp: handle memory regions w/o base address

The FF-A spec states that in the SP manifest a base address is not
mandatory for memory regions. If the field is not present, the specified
memory region must be allocated by the SPMC and mapped to the SP's
context.

A copy of the SP manifest fdt is used for passing the memory region
virtual addresses to the SP. Additional space is allocated when copying
the fdt so the originally not present base address fields can be added
later.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
[jf: edit description to avoid checkpatch spelling warning]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: sp: map memory regions from SP manifest

Currently the SP manifest processing only handles the device regions,
add support to handle the normal memory regions too.

Note: if the region's base a

core: sp: map memory regions from SP manifest

Currently the SP manifest processing only handles the device regions,
add support to handle the normal memory regions too.

Note: if the region's base address is a PA, according to the FF-A spec
it has to be identity mapped to the same VA. This requirement will be
removed in the spec's next version, so the current implementation should
be acceptable.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: sp: refactor manifest attribute checks

Simplify memory access attribute checks when parsing the SP manifest.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <e

core: sp: refactor manifest attribute checks

Simplify memory access attribute checks when parsing the SP manifest.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: sp: reorganize init functions

Move some of the SP init functions to prepare for the needed order in
the upcoming patches. This change doesn't modify functionality.

Acked-by: Jens Wiklander <j

core: sp: reorganize init functions

Move some of the SP init functions to prepare for the needed order in
the upcoming patches. This change doesn't modify functionality.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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plat-rockchip: rk3399: set CFG_CRYPTO_WITH_CE ?= y

Enables Arm Cryptography Extensions by default for the rk3399 SoC since
they are supported [1].

Link: [1] http://opensource.rock-chips.com/images/

plat-rockchip: rk3399: set CFG_CRYPTO_WITH_CE ?= y

Enables Arm Cryptography Extensions by default for the rk3399 SoC since
they are supported [1].

Link: [1] http://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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zynqmp: platform: provide uart configuration during compilation

Add possibility to provide UART configuration as a compile
flag (CFG_UART_BASE, CFG_UART_IT, CFG_UART_CLK_HZ).

Acked-by: Jerome Foris

zynqmp: platform: provide uart configuration during compilation

Add possibility to provide UART configuration as a compile
flag (CFG_UART_BASE, CFG_UART_IT, CFG_UART_CLK_HZ).

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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plat-vexpress: juno: default enable hwrng from smccc trng interface

Changes juno default configuration to get random bytes from TF-A
SMCCC TRNG interface instead of the pseudo-RNG support form OP-TE

plat-vexpress: juno: default enable hwrng from smccc trng interface

Changes juno default configuration to get random bytes from TF-A
SMCCC TRNG interface instead of the pseudo-RNG support form OP-TEE.

Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: declare struct mobj in thread_arch.h

Adds missing declaration of struct mobj in arm/kernel/thread_arch.h.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne C

core: arm: declare struct mobj in thread_arch.h

Adds missing declaration of struct mobj in arm/kernel/thread_arch.h.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-sam: enable CFG_ATMEL_TCB

Enable CFG_ATMEL_TCB to use the TCB as a time source instead of
CFG_SECURE_TIME_SOURCE_REE.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Cl

plat-sam: enable CFG_ATMEL_TCB

Enable CFG_ATMEL_TCB to use the TCB as a time source instead of
CFG_SECURE_TIME_SOURCE_REE.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-ti: Remove extra license text as we have SPDX

No functional change here.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

plat-sam: enable CFG_ATMEL_PIOBU by default

By default, enable CFG_ATMEL_PIOBU driver on plat-sam.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.foriss

plat-sam: enable CFG_ATMEL_PIOBU by default

By default, enable CFG_ATMEL_PIOBU driver on plat-sam.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-ti: Enable hardware RNG PTA

When the hardware RNG is available we should also enable
the HWRNG PTA so we can use it from the REE.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklan

plat-ti: Enable hardware RNG PTA

When the hardware RNG is available we should also enable
the HWRNG PTA so we can use it from the REE.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-ti: Add SM handler for setting AMBA IF in the WUGEN

This mirrors what is available as a ROM API. We implement this here as
OP-TEE's monitor replaces the ROM's monitor functions and we would lik

plat-ti: Add SM handler for setting AMBA IF in the WUGEN

This mirrors what is available as a ROM API. We implement this here as
OP-TEE's monitor replaces the ROM's monitor functions and we would like
to keep feature parity.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: SP: Add dump state

Add dump state for SPs. This will make it possible for the symbolize
script to print SP call stack on a panic,

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Acked-by: Jens

core: SP: Add dump state

Add dump state for SPs. This will make it possible for the symbolize
script to print SP call stack on a panic,

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-k3: Add DDR setup in k3 platform

This patch introduces DDR setup for possible use of
CFG_CORE_DYN_SHM/dynamic shared memory on k3 platform.

Acked-by: Jerome Forissier <jerome.forissier@linaro.

plat-k3: Add DDR setup in k3 platform

This patch introduces DDR setup for possible use of
CFG_CORE_DYN_SHM/dynamic shared memory on k3 platform.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Ivan Mikhaylov <ivan.mikhaylov@siemens.com>

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plat-stm32mp1: conf: enable SCMI with MSG header

Changes stm32mp1 platform configuration to default enable
CFG_SCMI_MSG_SHM_MSG and not mandate SMT message header protocol support
when SCMI PTA serv

plat-stm32mp1: conf: enable SCMI with MSG header

Changes stm32mp1 platform configuration to default enable
CFG_SCMI_MSG_SHM_MSG and not mandate SMT message header protocol support
when SCMI PTA service are embedded. The reason is that SCMI client
using threaded execution of SCMI messages, through the SCMI PTA service,
may use TEE shared memory and MSG header to transfer SCMI messages
instead of SMT header messages over IOMEM shared memory.

CFG_SCMI_MSG_SMT must be enabled when using SCMI SIP SMC services which
uses IOMEM shared memory only.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat: imx: enable SNVS driver by default

Enable SNVS driver by default for the following platforms:
* imx6
* imx7
* imx8m

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Fo

plat: imx: enable SNVS driver by default

Enable SNVS driver by default for the following platforms:
* imx6
* imx7
* imx8m

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: force CFG_IMX_UART to y for all imx6/7 and imx8m

Force the CFG_IMX_UART compilation flag to 'y' for all imx6/7 platforms
and imx8m platforms.
CFG_IMX_UART=n is an invalid configuration an

core: imx: force CFG_IMX_UART to y for all imx6/7 and imx8m

Force the CFG_IMX_UART compilation flag to 'y' for all imx6/7 platforms
and imx8m platforms.
CFG_IMX_UART=n is an invalid configuration and triggers a link error:
LD out/arm-plat-imx/core/all_objs.o
arm-none-linux-gnueabihf-ld.bfd: out/arm-plat-imx/core/arch/arm/plat-imx/main.o: in function `console_init'
core/arch/arm/plat-imx/main.c:113: undefined reference to `imx_uart_init'

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx8m: add SNVS_SIZE value

Add SNVS_SIZE value for all imx8m platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

plat: imx7: add SNVS_SIZE value

Add SNVS_SIZE value for imx7 platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: imx6: add SNVS_SIZE value

Add SNVS_SIZE for all imx6 platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: drivers: merge i.MX SNVS driver files

Move the implementation of plat_rpmb_key_is_ready() from
plat-imx/drivers/imx_snvs.c to drivers/imx_snvs.c

Signed-off-by: Clement Faure <clement.faure@nx

core: drivers: merge i.MX SNVS driver files

Move the implementation of plat_rpmb_key_is_ready() from
plat-imx/drivers/imx_snvs.c to drivers/imx_snvs.c

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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