1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017-2019 NXP 4 */ 5 6 #ifndef __IMX8M_H__ 7 #define __IMX8M_H__ 8 9 #include <registers/imx8m-crm.h> 10 11 #define GICD_BASE 0x38800000 12 #define GICR_BASE 0x38880000 13 #define UART1_BASE 0x30860000 14 #define UART2_BASE 0x30890000 15 #define UART3_BASE 0x30880000 16 #define UART4_BASE 0x30A60000 17 #define TZASC_BASE 0x32F80000 18 #define TZASC_SIZE 0x10000 19 #define CAAM_BASE 0x30900000 20 #define CCM_BASE 0x30380000 21 #define CCM_SIZE 0x10000 22 #define ANATOP_BASE 0x30360000 23 #define IOMUXC_BASE 0x30330000 24 #define OCOTP_BASE 0x30350000 25 #define OCOTP_SIZE 0x10000 26 #define SNVS_BASE 0x30370000 27 #define SNVS_SIZE 0x10000 28 29 #ifdef CFG_MX8MQ 30 #define DIGPROG_OFFSET 0x06c 31 #define OCOTP_SW_INFO_B1 0x40 32 #define OCOTP_SW_MAGIC_B1 0xFF0055AA 33 #endif 34 #if defined(CFG_MX8MM) || defined(CFG_MX8MN) || defined(CFG_MX8MP) 35 #define DIGPROG_OFFSET 0x800 36 #endif 37 38 #if defined(CFG_MX8MM) || defined(CFG_MX8MQ) 39 #define I2C1_BASE 0x30a20000 40 #define I2C2_BASE 0x30a30000 41 #define I2C3_BASE 0x30a40000 42 #define I2C4_BASE 0x30a50000 43 44 #define IOMUXC_I2C1_SCL_CFG_OFF 0x47C 45 #define IOMUXC_I2C1_SDA_CFG_OFF 0x480 46 #define IOMUXC_I2C1_SCL_MUX_OFF 0x214 47 #define IOMUXC_I2C1_SDA_MUX_OFF 0x218 48 #endif 49 50 #if defined(CFG_MX8MP) 51 #define I2C1_BASE 0x30a20000 52 #define I2C2_BASE 0x30a30000 53 #define I2C3_BASE 0x30a40000 54 #define I2C4_BASE 0x30a50000 55 #define I2C5_BASE 0x30ad0000 56 #define I2C6_BASE 0x30ae0000 57 58 #define IOMUXC_I2C1_SCL_CFG_OFF 0x460 59 #define IOMUXC_I2C1_SDA_CFG_OFF 0x464 60 #define IOMUXC_I2C1_SCL_MUX_OFF 0x200 61 #define IOMUXC_I2C1_SDA_MUX_OFF 0x204 62 #endif 63 64 #endif /* __IMX8M_H__ */ 65