core: driver: add common i.MX MU driver

Add a common MU driver for i.MX platforms. This MU driver is used to
communicate with external security controllers.

This driver includes a generic part and

core: driver: add common i.MX MU driver

Add a common MU driver for i.MX platforms. This MU driver is used to
communicate with external security controllers.

This driver includes a generic part and an hardware abstraction layer
for low level MU functions.

The MU driver implements the HAL for the following platforms:
- mx8ulpevk
- mx8qmmek/imx8qxpmek

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat: rcar: fix core pos calculation for H3 boards

Due to mistake, cluster position wasn't shifted left if chip is not
M3W. This led to erroneous core ID calculation on chips that are not
M3W. Actua

plat: rcar: fix core pos calculation for H3 boards

Due to mistake, cluster position wasn't shifted left if chip is not
M3W. This led to erroneous core ID calculation on chips that are not
M3W. Actually, this affected only H3, as only this chip has two
clusters.

Fix this by always shifting x1 (cluster ID) to the left, before doing
one additional shift for non-M3W chips.

Fixes: 572afdce53ea ("plat: rcar: Derive core map from PRR")

Reported-by: Oleksandr Grytsov <oleksandr_grytsov@epam.com>
Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (R-Car M3)
Tested-by: Oleksandr Grytsov <oleksandr_grytsov@epam.com> (R-Car H3)
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: imx-i2c: add support for imx8mn

Add i2c support for imx8mn platforms

Signed-off-by: Gerard Koskamp <gerard.koskamp@nedap.com>
Reviewed-by: Robert Krikke <robert.krikke@nedap.com>
Acked-by:

drivers: imx-i2c: add support for imx8mn

Add i2c support for imx8mn platforms

Signed-off-by: Gerard Koskamp <gerard.koskamp@nedap.com>
Reviewed-by: Robert Krikke <robert.krikke@nedap.com>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

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core: plat-ls: remove OP-TEE support for LS1021A-QDS platform

LS1021A-QDS does not support OP-TEE anymore, removing its
support.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jer

core: plat-ls: remove OP-TEE support for LS1021A-QDS platform

LS1021A-QDS does not support OP-TEE anymore, removing its
support.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: plat-ls: remove OP-TEE support for LS1021A-TWR platform

LS1021A-TWR does not support OP-TEE anymore, removing its
support.
Since LS1021A-TWR was default platform for LS, updating default
platf

core: plat-ls: remove OP-TEE support for LS1021A-TWR platform

LS1021A-TWR does not support OP-TEE anymore, removing its
support.
Since LS1021A-TWR was default platform for LS, updating default
platform also to LS1012A-RDB

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp1: fix use of pointer after free

Fix the following with gcc12:

| In file included from lib/libutils/isoc/include/assert.h:9,
| from core/include/drivers/serial.h:8,
|

plat-stm32mp1: fix use of pointer after free

Fix the following with gcc12:

| In file included from lib/libutils/isoc/include/assert.h:9,
| from core/include/drivers/serial.h:8,
| from core/include/drivers/stm32_uart.h:10,
| from core/arch/arm/plat-stm32mp1/main.c:14:
| core/arch/arm/plat-stm32mp1/main.c: In function 'init_console_from_dt':
| core/arch/arm/plat-stm32mp1/main.c:141:50: error: pointer 'pd' used after 'free' [-Werror=use-after-free]
| 141 | IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-");
| | ~~^~~~~~~~
| lib/libutils/ext/include/trace.h:41:22: note: in definition of macro 'trace_printf_helper'
| 41 | __VA_ARGS__)
| | ^~~~~~~~~~~
| core/arch/arm/plat-stm32mp1/main.c:141:9: note: in expansion of macro 'IMSG'
| 141 | IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-");
| | ^~~~
| core/arch/arm/plat-stm32mp1/main.c:139:9: note: call to 'free' here
| 139 | free(pd);
| | ^~~~~~~~

Signed-off-by: Jose Quaresma <jose.quaresma@foundries.io>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: zynqmp_huk: Add AES eFuse and HUK seed support

When AES eFuse is used to encrypt boot loaders and bitstreams then PUF
functionality is not available for use. When AES eFuse based encryption

drivers: zynqmp_huk: Add AES eFuse and HUK seed support

When AES eFuse is used to encrypt boot loaders and bitstreams then PUF
functionality is not available for use. When AES eFuse based encryption is
in use AES eFuse key becomes device key instead of PUF generated key.

In order to re-plenish additional device specific entropy that PUF would
provide utilize selected set of User programmable eFuses.

Selected user eFuses should be programmed during device manufacturing with
cryptographically good random numbers.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core, ldelf: link: add --no-warn-execstack

When building for arm32 with GNU binutils 2.39, the linker outputs
warnings when generating some TEE core binaries (all_obj.o, init.o,
unpaged.o and tee.el

core, ldelf: link: add --no-warn-execstack

When building for arm32 with GNU binutils 2.39, the linker outputs
warnings when generating some TEE core binaries (all_obj.o, init.o,
unpaged.o and tee.elf) as well as ldelf.elf:

arm-poky-linux-gnueabi-ld.bfd: warning: atomic_a32.o: missing .note.GNU-stack section implies executable stack
arm-poky-linux-gnueabi-ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker

The permissions used when mapping the TEE core stacks do not depend on
any metadata found in the ELF file. Similarly when the TEE core loads
ldelf it already creates a non-executable stack regardless of ELF
information. Therefore we can safely ignore the warnings. This is done
by adding the '--no-warn-execstack' option.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix handling of CFG_STACK_THREAD_EXTRA and CFG_STACK_TMP_EXTRA

CFG_STACK_THREAD_EXTRA and CFG_STACK_TMP_EXTRA should be included in
STACK_THREAD_SIZE and STACK_TMP_SIZE, respectively, because

core: fix handling of CFG_STACK_THREAD_EXTRA and CFG_STACK_TMP_EXTRA

CFG_STACK_THREAD_EXTRA and CFG_STACK_TMP_EXTRA should be included in
STACK_THREAD_SIZE and STACK_TMP_SIZE, respectively, because not doing so
creates inconsistencies where some places use e.g., (STACK_THREAD_SIZE +
CFG_STACK_THREAD_EXTRA) while others use STACK_THREAD_SIZE only. Note
for example the discrepancy between the stack declaration:

DECLARE_STACK(stack_thread, CFG_NUM_THREADS,
STACK_THREAD_SIZE + CFG_STACK_THREAD_EXTRA, static);

...and the thread_stack_start() function:

vaddr_t thread_stack_start(void)
{
/* ... */

return thr->stack_va_end - STACK_THREAD_SIZE;
}

With this change, the _EXTRA values should also be properly taken into
account when pager is enabled, which was not the case before.

Fixes: cca7b5ebeb9b ("core: configuration switches to tune stack sizes")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jorge Ramirez-Ortiz <jorge@foundries.io> (STM32MP1, SE050, pager)

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arm: cache_helpers.h: Add cache_get_max_line_size()

Add helper for querying outer cache line size in bytes.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Jens Wiklan

arm: cache_helpers.h: Add cache_get_max_line_size()

Add helper for querying outer cache line size in bytes.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm.mk: Added CFG_MAX_CACHE_LINE_SHIFT for maximum cache line size

When sharing memory between CPU and peripherals it is important that data
is accurate for all parties.

Today's CPU's has multiple

arm.mk: Added CFG_MAX_CACHE_LINE_SHIFT for maximum cache line size

When sharing memory between CPU and peripherals it is important that data
is accurate for all parties.

Today's CPU's has multiple levels for caches and their sizes are platform
specific. As there is no auto detectable way to determine cache line size
during runtime so it must be defined during compilation time.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: Add high DDR memory region

K3 devices support more than 2GB of DRAM, the extra is placed at a highmem
address of 0x880000000. If memory from this area is passed to OP-TEE
one will get the f

plat-k3: Add high DDR memory region

K3 devices support more than 2GB of DRAM, the extra is placed at a highmem
address of 0x880000000. If memory from this area is passed to OP-TEE
one will get the following error:

E/TC:1 0 std_entry_with_parg:235 Bad arg address 0x881585000

Add the highmem area to fix this.

Fixes: dfd994436ac3 ("plat-k3: Add DDR setup in k3 platform")
Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-k3: Enable ARMv8 Crypto Extensions support by default

All of the currently supported K3 platforms support ARM CE, enable this
by default so it does not have to be enabled in the build command.

plat-k3: Enable ARMv8 Crypto Extensions support by default

All of the currently supported K3 platforms support ARM CE, enable this
by default so it does not have to be enabled in the build command.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-k3: drivers: Reverse RNG disabling logic

We want to be able to disable SA2UL from the command line and only be
able to enable it for supported platforms. Right now we force it on
for supported

plat-k3: drivers: Reverse RNG disabling logic

We want to be able to disable SA2UL from the command line and only be
able to enable it for supported platforms. Right now we force it on
for supported platforms and allow it to be enabled still on unsupported
ones. Reverse this.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-k3: drivers: ti-sci: Do not print error when message not acknowledged

When the system controller firmware denies a request, we are informed
of this by the lack of an acknowledge flag in the res

plat-k3: drivers: ti-sci: Do not print error when message not acknowledged

When the system controller firmware denies a request, we are informed
of this by the lack of an acknowledge flag in the response. This is
not always an error in cases when we are only testing for permissions.
Do not print error messages in this path. The TI-SCI API caller will
still print the appropriate message if needed.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-k3: drivers: Set SA2UL firewall region addresses

This firewall region is normally already set to cover our RNG, but that
is not guaranteed. To ensure we actually protect the RNG with this regio

plat-k3: drivers: Set SA2UL firewall region addresses

This firewall region is normally already set to cover our RNG, but that
is not guaranteed. To ensure we actually protect the RNG with this region,
explicitly set the address here to the RNG start and end addresses.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: enable the CAAM driver on mx7ulpevk

Enable the CAAM for mx7ulpevk.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: imx: crypto_conf: set CAAM configuration for mx7ulpevk

Set CAAM configuration for the mx7ulp platform.
On mx7ulp, JRs share the same interrupt line. To avoid conflict with the
non-secure world

core: imx: crypto_conf: set CAAM configuration for mx7ulpevk

Set CAAM configuration for the mx7ulp platform.
On mx7ulp, JRs share the same interrupt line. To avoid conflict with the
non-secure world, disable the use of JR interrupt in OPTEE.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: add support imx93evk platform

Add the support for imx93evk platform.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-b

core: imx: add support imx93evk platform

Add the support for imx93evk platform.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add imx93 SoC ID

Add the imx93 SoC ID.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklan

core: imx: add imx93 SoC ID

Add the imx93 SoC ID.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add imx93 registers

Add the imx93 registers.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.

core: imx: add imx93 registers

Add the imx93 registers.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: simplify the error macro message

Simplify the error macro message for less maintenance when it comes to
introduce new platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Revi

core: imx: simplify the error macro message

Simplify the error macro message for less maintenance when it comes to
introduce new platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-corstone1000: add corstone1000 platform

These changes are to add corstone1000 platform to optee
core.
arch/arm/plat-vexpress is taken as a reference to make
these changes.

Signed-off-by: Vishn

plat-corstone1000: add corstone1000 platform

These changes are to add corstone1000 platform to optee
core.
arch/arm/plat-vexpress is taken as a reference to make
these changes.

Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: link: add --no-warn-rwx-segments

binutils ld.bfd generates one RWX LOAD segment by merging several sections
with mixed R/W/X attributes (.text, .rodata, .data). After version 2.38 it
also warn

core: link: add --no-warn-rwx-segments

binutils ld.bfd generates one RWX LOAD segment by merging several sections
with mixed R/W/X attributes (.text, .rodata, .data). After version 2.38 it
also warns by default when that happens [1], which breaks the build due to
--fatal-warnings. The RWX segment is not a problem for the TEE core, since
that information is not used to set memory permissions. Therefore, silence
the warning.

Link: [1] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ba951afb99912da01a6e8434126b8fac7aa75107
Link: https://sourceware.org/bugzilla/show_bug.cgi?id=29448
Reported-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-bcm: remove virtual address lookup from main_init_gic()

- Commit 60801696667d ("plat: arm: refactor GIC initialization")
refactored GIC initialization to have gic_init_base_addr() take

core: plat-bcm: remove virtual address lookup from main_init_gic()

- Commit 60801696667d ("plat: arm: refactor GIC initialization")
refactored GIC initialization to have gic_init_base_addr() take in a
physical address instead of a virtual one, meaning that a virtual
address lookup is no longer necessary within a platform's gic_init().
- BCM's main_init_gic() would still perform a virtual memory lookup and
hand over its virtual address instead of the expected physical one.
This caused the lookup in gic_init_base_addr() to fail and panic.
- This new commit removes the virtual memory lookup from BCM's
main_gic_init() and instead hands gic_init_base_addr() a physical
address.

Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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