core: ls: add CAAM_SIZE values for LS platforms

Add CAAM_SIZE values for all LS platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

core: imx: add CAAM_SIZE values for i.MX platforms

Add CAAM_SIZE values for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.

core: imx: add CAAM_SIZE values for i.MX platforms

Add CAAM_SIZE values for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: sama5d2: Set tcb1 as secure

Add missing status-okay line to enable tcb1 for OP-TEE usage. Indeed,
the TCB block is used to provide a secure time source to OP-TEE TA.

Signed-off-by: Clément Lég

dts: sama5d2: Set tcb1 as secure

Add missing status-okay line to enable tcb1 for OP-TEE usage. Indeed,
the TCB block is used to provide a secure time source to OP-TEE TA.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: make sure build date is always in English

Setting LANG=C before invoking the date command doesn't always result in
the "C" (English) locale being selected. The correct way is to set
LC_ALL. As

core: make sure build date is always in English

Setting LANG=C before invoking the date command doesn't always result in
the "C" (English) locale being selected. The correct way is to set
LC_ALL. As explained in the locale(7) man page:

If the second argument to setlocale(3) is an empty string, "", for the
default locale, it is determined using the following steps:

1. If there is a non-null environment variable LC_ALL, the value of
LC_ALL is used.

2. If an environment variable with the same name as one of the
categories above exists and is non-null, its value is used for that
category.

3. If there is a non-null environment variable LANG, the value of LANG
is used.

Fixes: 3e2b963515c1 ("core: use C locale when generating the build date")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Tested-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: remove SCMI0 channel index

Removes index 0 from SCMI DT binding ID macros and driver labels to
synchronize with Linux kernel 5.18 that considers a single SCMI
channel, see [1] and [2]

plat-stm32mp1: remove SCMI0 channel index

Removes index 0 from SCMI DT binding ID macros and driver labels to
synchronize with Linux kernel 5.18 that considers a single SCMI
channel, see [1] and [2].

Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-4-alexandre.torgue@foss.st.com
Link: [2] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-5-alexandre.torgue@foss.st.com
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: scmi_server: removed unused channel SCMI1

Remove this SCMI channel from DT bindings and platform driver as it is
unused.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.c

plat-stm32mp1: scmi_server: removed unused channel SCMI1

Remove this SCMI channel from DT bindings and platform driver as it is
unused.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: use helper header file stm32mp_dt_bindings.h

Changes plat-stm32mp1 and its drivers to rely on stm32mp_dt_bindings.h
which simplifies support of both variants STM32MP15 and STM32MP13 t

plat-stm32mp1: use helper header file stm32mp_dt_bindings.h

Changes plat-stm32mp1 and its drivers to rely on stm32mp_dt_bindings.h
which simplifies support of both variants STM32MP15 and STM32MP13 that
will use each specific DT bindings.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: default disable ASLR

Default disable CFG_CORE_ASLR on stm32mp1. The platform memory
firewall does not allow secure world to access external DTB in
non-secure memory when MMU is

plat-stm32mp1: conf: default disable ASLR

Default disable CFG_CORE_ASLR on stm32mp1. The platform memory
firewall does not allow secure world to access external DTB in
non-secure memory when MMU is OFF, which is what the software attempts
to do when CFG_CORE_ASLR=y.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: update RAM configuration

Align platform RAM configuration with TF-A.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.car

plat-stm32mp1: conf: update RAM configuration

Align platform RAM configuration with TF-A.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: default heap size to 48kB when pager is on

Changes default heap size from 64kB to 48kB when pager is enabled.
The saved physical pages are assigned to pager pool.

Signed-off-by

plat-stm32mp1: conf: default heap size to 48kB when pager is on

Changes default heap size from 64kB to 48kB when pager is enabled.
The saved physical pages are assigned to pager pool.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: allow BSEC writing in debug mode

Default embed support for burning fuses when in debug build configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Rev

plat-stm32mp1: conf: allow BSEC writing in debug mode

Default embed support for burning fuses when in debug build configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: disable TA compression when pager is on

Disable CFG_EARLY_TA_COMPRESS when CFG_WITH_PAGER is enabled. With this
change, the TAs will not be compressed into the TEE binary. Now,

plat-stm32mp1: conf: disable TA compression when pager is on

Disable CFG_EARLY_TA_COMPRESS when CFG_WITH_PAGER is enabled. With this
change, the TAs will not be compressed into the TEE binary. Now, core
heap can be smaller than 64kB and platform can leverage that to assign
more physical pages in the pager pool.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: remove shared memory configuration

This change fully removes the reserved static shared memory
(CFG_SHMEM_START/CFG_SHMEM_SIZE) that is no more needed since U-Boot
and Linux bot

plat-stm32mp1: conf: remove shared memory configuration

This change fully removes the reserved static shared memory
(CFG_SHMEM_START/CFG_SHMEM_SIZE) that is no more needed since U-Boot
and Linux both use their standard system memory as TEE shared memory.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: plat-spike: console driver based on host-target interface

Spike doesn't yet model a UART but relies on RISC-V Host-Target Interface
(HTIF) to perform all I/O. It is a protocol allowing

core: riscv: plat-spike: console driver based on host-target interface

Spike doesn't yet model a UART but relies on RISC-V Host-Target Interface
(HTIF) to perform all I/O. It is a protocol allowing the target to access
host to perform console, storage etc. It requires special ELF symbols
tohost and fromhost. HTIF base address is set to 0x40008000.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
[jf: remove useless line continuation; initialize base to 0]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: add stmm and sp prototypes

Provide a declaration of functions is_sp_ctx(), is_stmm_ctx(), to_sp_ctx()
and to_stmm_ctx() to avoid build errors.

Signed-off-by: Marouene Boubakri <marouen

core: riscv: add stmm and sp prototypes

Provide a declaration of functions is_sp_ctx(), is_stmm_ctx(), to_sp_ctx()
and to_stmm_ctx() to avoid build errors.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: generic_ram_layout.h: ram layout configuration directives

The RAM layout is similar to the original one, use TD(D|S)RAM instead of
TZ(D|S)RAM referring to Trusted Domain (TD).
Keep the

core: riscv: generic_ram_layout.h: ram layout configuration directives

The RAM layout is similar to the original one, use TD(D|S)RAM instead of
TZ(D|S)RAM referring to Trusted Domain (TD).
Keep the directives for secure data path. SDP could be achieved later
using IOPMP.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: spinlock.c: implement spin-locking primitives

Implement __cpu_spin_lock(), __cpu_spin_unlock() and __cpu_spin_trylock()
Use atomic-instruction amoswap in "A" extension for locks and ens

core: riscv: spinlock.c: implement spin-locking primitives

Implement __cpu_spin_lock(), __cpu_spin_unlock() and __cpu_spin_trylock()
Use atomic-instruction amoswap in "A" extension for locks and ensure memory
ordering using fence instruction.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: add tlb_helpers.h

The tlbi_asid() function is required by core/mm/vm.c
and tlbi_all() function is required by core/mm/core_mmu.c
Declare them in core/arch/riscv/include/kernel/tlb_helpe

core: riscv: add tlb_helpers.h

The tlbi_asid() function is required by core/mm/vm.c
and tlbi_all() function is required by core/mm/core_mmu.c
Declare them in core/arch/riscv/include/kernel/tlb_helpers.h

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: plat-spike: add platform configuration header file

Introduces a minimalist platform_config.h to be used by linker scripts.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>

core: riscv: plat-spike: add platform configuration header file

Introduces a minimalist platform_config.h to be used by linker scripts.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: riscv.mk: setup compiler for the RISC-V core module

Setup compiler for the risc-v core module on 32 and 64 bits definitions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com

core: riscv: riscv.mk: setup compiler for the RISC-V core module

Setup compiler for the risc-v core module on 32 and 64 bits definitions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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riscv: create makefiles and directories tree for riscv

This commits creates the very first makefiles, directories and
subdirectories for RISC-V port. It also creates a new platform flavor
named plat

riscv: create makefiles and directories tree for riscv

This commits creates the very first makefiles, directories and
subdirectories for RISC-V port. It also creates a new platform flavor
named plat-spike. Spike is a reference functional RISC-V ISA simulator
which provides full system emulation and it is developed alongside the
RISC-V toolchain.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-k3: drivers: Fix SA2UL background firewall size

For GP devices this first firewall region should be a background region
that spans the whole address space managed by this firewall. This allows

plat-k3: drivers: Fix SA2UL background firewall size

For GP devices this first firewall region should be a background region
that spans the whole address space managed by this firewall. This allows
normal use of devices behind it even when not explicitly permitted.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-k3: drivers: Add SA2UL RNG driver

TI K3 family devices contain a set of crypto accelerators under
the umbrella device SA2UL. Add support for setting up the power
and firewalls for this device.

plat-k3: drivers: Add SA2UL RNG driver

TI K3 family devices contain a set of crypto accelerators under
the umbrella device SA2UL. Add support for setting up the power
and firewalls for this device. Then add support for the TRNG
sub-device.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-k3: Move TI-SCI setup out of HUK function

The TI-SCI components are used for more than just the hardware
unique key, move the setup out into a service_init so it is
not tied to just HUK.

While

plat-k3: Move TI-SCI setup out of HUK function

The TI-SCI components are used for more than just the hardware
unique key, move the setup out into a service_init so it is
not tied to just HUK.

While here remove the device check for HUK, it works on all
supported K3 devices.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-k3: drivers: ti-sci: Add support for setting firewall state

This adds support for the TI-SCI firewall messages:
* TI_SCI_MSG_FWL_SET
* TI_SCI_MSG_FWL_GET
* TI_SCI_MSG_FWL_CHANGE_OWNER

Signe

plat-k3: drivers: ti-sci: Add support for setting firewall state

This adds support for the TI-SCI firewall messages:
* TI_SCI_MSG_FWL_SET
* TI_SCI_MSG_FWL_GET
* TI_SCI_MSG_FWL_CHANGE_OWNER

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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