versal: enable the crypto driver

The crypto driver API provides an extra indirection level to enable
different ciphers.

Since Versal ACAP supports acipher and authenc, enable them.

Falling-back to

versal: enable the crypto driver

The crypto driver API provides an extra indirection level to enable
different ciphers.

Since Versal ACAP supports acipher and authenc, enable them.

Falling-back to software operations (RSA sign/verify) triggers a
fault detection; we will disable this config while a solution is
found.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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versal: increase CFG_CORE_HEAP_SIZE

Empirically incrementing limit to avoid OOM when executing xtests.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.for

versal: increase CFG_CORE_HEAP_SIZE

Empirically incrementing limit to avoid OOM when executing xtests.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: kernel: move ldelf_loader.c to core/kernel

Make other architecture implementations benefit from ldelf_loader.c,
therefore move it from core/arch/arm/kernel to core/kernel.
The header file is a

core: kernel: move ldelf_loader.c to core/kernel

Make other architecture implementations benefit from ldelf_loader.c,
therefore move it from core/arch/arm/kernel to core/kernel.
The header file is already located outside the arch folder.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: provide cache_helpers_rv.S

Simple implementation of instruction cache and data cache operations
that relies on RISC-V's fence and fence.i instructions.

Signed-off-by: Marouene Boubakri

core: riscv: provide cache_helpers_rv.S

Simple implementation of instruction cache and data cache operations
that relies on RISC-V's fence and fence.i instructions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: provide arch_scall_rv.S

Provide an implementation of scall_do_call(), syscall_sys_return()
and syscall_panic().

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: J

core: riscv: provide arch_scall_rv.S

Provide an implementation of scall_do_call(), syscall_sys_return()
and syscall_panic().

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: arch_scall.c: implement scall_save_panic_stack()

Provide an implementation of scall_save_panic_stack() needed by
scall_sys_return_helper().

Signed-off-by: Marouene Boubakri <marouene.b

core: riscv: arch_scall.c: implement scall_save_panic_stack()

Provide an implementation of scall_save_panic_stack() needed by
scall_sys_return_helper().

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: provide arch_scall.h

Specifies what registers from thread_scall_regs are used for system calls.
The syscall number is provided in t0 register. The syscall max args is
provided in t1 reg

core: riscv: provide arch_scall.h

Specifies what registers from thread_scall_regs are used for system calls.
The syscall number is provided in t0 register. The syscall max args is
provided in t1 register. The return value is provided in a0 register.
The panic and panic code are provided respectively in a1 and a2 registers.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: implement thread management routines in thread_arch.c

This commit implements an initial thread management for RISC-V. It covers
the following routines:

- Exceptions un/masking
- Trap h

core: riscv: implement thread management routines in thread_arch.c

This commit implements an initial thread management for RISC-V. It covers
the following routines:

- Exceptions un/masking
- Trap handling, including syscalls handling.
- Thread allocation, execution, suspension, freeing with slight changes
to set RISC-V registers such as CSRs.
- RPC.

Pending routines:
- Floatting point support F/D/Q/L extensions and software FP.
- Abort mode.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: provide abort.c

Initial implementation of abort handler for RISC-V.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

core: riscv: add thread manager assembly code in thread_rv.S

This commit implements:
- An entry point of trap handler in non-vectored mode.
- thread_unwind_user_mode() and thread_exit_user_mode()
to

core: riscv: add thread manager assembly code in thread_rv.S

This commit implements:
- An entry point of trap handler in non-vectored mode.
- thread_unwind_user_mode() and thread_exit_user_mode()
to return from U-Mode.
- __thread_enter_user_mode() to jump to U-Mode from S-Mode or M-Mode.
- thread_std_smc_entry(), thread_resume() and thread_rpc().

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: riscv.h: bind registers to their ABI names

For better readability of code, allow using register ABI names
in ASM sources to match registers declarations in C files.

Signed-off-by: Maro

core: riscv: riscv.h: bind registers to their ABI names

For better readability of code, allow using register ABI names
in ASM sources to match registers declarations in C files.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: asm-defines.c: create and populate with thread-related defines

Create core/arch/riscv/kernel/asm-defines.c and add defines for thread_ctx,
thread_core_local, thread_ctx_regs, thread_use

core: riscv: asm-defines.c: create and populate with thread-related defines

Create core/arch/riscv/kernel/asm-defines.c and add defines for thread_ctx,
thread_core_local, thread_ctx_regs, thread_user_mode_rec, thread_trap_regs
and thread_scall_regs.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: kernel: add several modifications to thread_arch.h

This commits:
- Adds 4 trampoline registers to thread_core_local to store arguments of
__thread_enter_user_mode before jumping to U-Mo

core: riscv: kernel: add several modifications to thread_arch.h

This commits:
- Adds 4 trampoline registers to thread_core_local to store arguments of
__thread_enter_user_mode before jumping to U-Mode to be restored later
after exiting U-Mode.
- Populates thread_trap_regs with all registers available on RV 64/32,
this holds the trap frame for trap handling.
- Populates thread_ctx_regs with general purpose registers.
- Makes generic definition of THREAD_EXCP_FOREIGN_INTR and
THREAD_EXCP_NATIVE_INTR to work both on S-Mode and M-Mode.
- Adds prototypes for Soft FP (to be implemented later) and RPC caches.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: kernel: add thread_private_arch.h

Declares stacks sizes, thread_user_mode_rec structure to restore
context after exiting from U-Mode. It also adds prototypes for
thread_rv.s and thread_

core: riscv: kernel: add thread_private_arch.h

Declares stacks sizes, thread_user_mode_rec structure to restore
context after exiting from U-Mode. It also adds prototypes for
thread_rv.s and thread_arch.c

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: riscv.h: define generic CSRs to handle traps

Added xSTATUS and xIE related fields and flags for traps
handling.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: J

core: riscv: riscv.h: define generic CSRs to handle traps

Added xSTATUS and xIE related fields and flags for traps
handling.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: riscv_macros.S: add load_xregs and save_xregs macros

Introduce helper macros to load/store a range registers from/to a base
register at a given offset. It uses LDR and STR macros define

core: riscv: riscv_macros.S: add load_xregs and save_xregs macros

Introduce helper macros to load/store a range registers from/to a base
register at a given offset. It uses LDR and STR macros defined in riscv.h
for respectively RV32 and RV64. Offsets are shifted by RISCV_XLEN_BYTES.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: add support for hafnium interrupt controller

Enables support for the Hafnium interrupt controller if configured with
CFG_CORE_HAFNIUM_INTC=y.

Acked-by: Jerome Forissier <jerome.foris

plat-vexpress: add support for hafnium interrupt controller

Enables support for the Hafnium interrupt controller if configured with
CFG_CORE_HAFNIUM_INTC=y.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add driver for hafnium interrupt controller

Adds a driver for the paravirtualized interrupt controller provided by
Hafnium at S-EL2. The driver is enabled with CFG_CORE_HAFNIUM_INTC=y.

The in

core: add driver for hafnium interrupt controller

Adds a driver for the paravirtualized interrupt controller provided by
Hafnium at S-EL2. The driver is enabled with CFG_CORE_HAFNIUM_INTC=y.

The interrupt controller is limited compared to the GIC and only works
with interrupt ids which are already added in the SP manifest or as
predefined reserved interrupt ids.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add CFG_CORE_IRQ_IS_NATIVE_INTR

Adds CFG_CORE_IRQ_IS_NATIVE_INTR to configure how native and foreign are
signalled.
Selects if IRQ is used to signal native interrupt
if CFG_CORE_IRQ_IS_NATIVE_

core: add CFG_CORE_IRQ_IS_NATIVE_INTR

Adds CFG_CORE_IRQ_IS_NATIVE_INTR to configure how native and foreign are
signalled.
Selects if IRQ is used to signal native interrupt
if CFG_CORE_IRQ_IS_NATIVE_INTR == y:
IRQ signals a native interrupt pending
FIQ signals a foreign non-secure interrupt or a managed exit pending
else: (vice versa)
IRQ signals a foreign non-secure interrupt or a managed exit pending
FIQ signals a native interrupt pending

CFG_CORE_IRQ_IS_NATIVE_INTR replaces the places in the code where
CFG_ARM_GICV3 was used to configure how FIQ and IRQ was treated.

CFG_CORE_IRQ_IS_NATIVE_INTR is automatically configured according to
CFG_ARM_GICV3 if CFG_GIC == y. This prepares for other interrupt
controllers where it doesn't make sense to use CFG_ARM_GICV3.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: S-EL2 SPMC: update for hafnium

Updates needed to run with Hafnium as S-EL2 SPMC on QEMU. GIC and
reserved (static) shared is not supported, so disable it for
CFG_CORE_SEL2_SPMC=y.

Wi

plat-vexpress: S-EL2 SPMC: update for hafnium

Updates needed to run with Hafnium as S-EL2 SPMC on QEMU. GIC and
reserved (static) shared is not supported, so disable it for
CFG_CORE_SEL2_SPMC=y.

With S-EL2 on QEMU some secure memory must be set aside for Hafnium.
Since this depends on how Hafnium is compiled etc don't assume which
address range can be used by OP-TEE, instead leave that as an open
configuration option.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: add thread_hvc()

Adds thread_hvc() which is the same as thread_smc() except that it uses
the HVC instruction instead of the SMC instruction. This is useful where
an SPMC at S-EL2 expects

core: arm: add thread_hvc()

Adds thread_hvc() which is the same as thread_smc() except that it uses
the HVC instruction instead of the SMC instruction. This is useful where
an SPMC at S-EL2 expects and HVC instead of SMC for certain functions.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mobj_ffa_add_pages_at() trust addresses from SPMC

mobj_ffa_add_pages_at() checks that a supplied physical address is
non-secure. This check is not needed with an SPMC at S-EL2 as we can
trust

core: mobj_ffa_add_pages_at() trust addresses from SPMC

mobj_ffa_add_pages_at() checks that a supplied physical address is
non-secure. This check is not needed with an SPMC at S-EL2 as we can
trust that to only provide verified addresses. So disable the check for
non-secure memory in that case, this has also the advantage that OP-TEE
no longer need to know the valid ranges of non-secure memory.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: S-EL1 SPMC: fix handling of fragmented memory descriptors

Prior to this commit there was a misunderstanding of how fragmented
memory descriptors are handled. FFA_MEM_SHARE returned FFA_SU

core: arm: S-EL1 SPMC: fix handling of fragmented memory descriptors

Prior to this commit there was a misunderstanding of how fragmented
memory descriptors are handled. FFA_MEM_SHARE returned FFA_SUCCESS even
when another fragment was expected. FFA_MEM_FRAG_TX returned
FFA_MEM_FRAG_RX even after the last fragment was received.

Fix this by only return FFA_SUCCESS from FFA_MEM_SHARE if the entire
descriptor has been received. If only the first fragment has been
received return FFA_MEM_FRAG_RX instead. Only return FFA_MEM_FRAG_RX
from FFA_MEM_FRAG_TX if further fragments are expected. Return
FFA_SUCCESS from FFA_MEM_FRAG_RX when then entire descriptor has been
received.

Fixes: 1b302ac09816 ("core: enable FF-A with SPM Core at S-EL1")
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: S-EL1 SPMC: boot ABI update

Updates the boot ABI for S-EL1 SPMC to align better with other SPMCs,
like Hafnium, but also with the non-FF-A configuration.

Register usage:
X0 - TOS FW conf

core: arm: S-EL1 SPMC: boot ABI update

Updates the boot ABI for S-EL1 SPMC to align better with other SPMCs,
like Hafnium, but also with the non-FF-A configuration.

Register usage:
X0 - TOS FW config [1] address, if not NULL
X2 - System DTB, if not NULL

Adds check in the default get_aslr_seed() to see if the system DTB is
present before trying to read kaslr-seed from secure-chosen.

Note that this is an incompatible change and requires corresponding
change in TF-A ("feat(qemu): update abi between spmd and spmc") [2].

[1] A TF-A concept: TOS_FW_CONFIG - Trusted OS Firmware configuration
file. Used by Trusted OS (BL32), that is, OP-TEE in this case
Link: [2] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=25ae7ad1878244f78206cc7c91f7bdbd267331a1

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: remove unused pin description for uart8

Uart8 was removed. Removes unused pin description for this peripheral.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by:

dts: stm32: remove unused pin description for uart8

Uart8 was removed. Removes unused pin description for this peripheral.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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