dts: stm32: add RTC RIF configuration for the stm32mp257f-ev1 board

Add the RTC RIF configuration for the stm32mp257f-ev1 board.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Revi

dts: stm32: add RTC RIF configuration for the stm32mp257f-ev1 board

Add the RTC RIF configuration for the stm32mp257f-ev1 board.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

drivers: stm32_rtc: add the capability to wakeup the platform

During probe, we look for the property "wakeup-source" that
will trigger the feature "RTC_WAKEUP_ALARM" which will
be send to the caller

drivers: stm32_rtc: add the capability to wakeup the platform

During probe, we look for the property "wakeup-source" that
will trigger the feature "RTC_WAKEUP_ALARM" which will
be send to the callers of the framework `rtc_get_info()` PTA.

We also register the `stm32_rtc_alarm_wake_set_status()` callback.
This callback should be called when the callers knows that the platform
will go in sleep mode.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

drivers: stm32_rtc: add init configuration function

The init function aims to contains init configurations of the RTC
peripheral such as prescalers, config or calibration registers.
Add "CFG_STM32_H

drivers: stm32_rtc: add init configuration function

The init function aims to contains init configurations of the RTC
peripheral such as prescalers, config or calibration registers.
Add "CFG_STM32_HIGH_ACCURACY" (default to no) config to enable the
high accuracy mode which allow the highest refresh rate of the subsecond
register.
Also merge the functions `stm32_rtc_wait_sync()` with
`stm32_exit_init_mode()` as every stm32 exit init mode was followed
by a wait sync.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

plat-stm32mp2: enable async notif with GIC PPI 15

Enables OP-TEE async notif (asynchronous notification from OP-TEE
to the non-secure world) using GIC PPI 15 (GIC interrupt line 31).

Signed-off-by:

plat-stm32mp2: enable async notif with GIC PPI 15

Enables OP-TEE async notif (asynchronous notification from OP-TEE
to the non-secure world) using GIC PPI 15 (GIC interrupt line 31).

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

plat-stm32mp2: add support for RTC PTA

Compile the RTC PTA and the RTC driver if the RTC driver for stm32 is
enabled.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Et

plat-stm32mp2: add support for RTC PTA

Compile the RTC PTA and the RTC driver if the RTC driver for stm32 is
enabled.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

plat-stm32mp1: add support for RTC PTA

Compile the RTC PTA and the RTC driver if the RTC driver for stm32 is
enabled.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Et

plat-stm32mp1: add support for RTC PTA

Compile the RTC PTA and the RTC driver if the RTC driver for stm32 is
enabled.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

plat-marvell: Add support for CN20K SoCs

Add support for Octeon20(CN20K) SoCs from Marvell.

Only tested 64-bit mode with default configurations:

1. Build command
make PLATFORM=marvell-cn20ka
mak

plat-marvell: Add support for CN20K SoCs

Add support for Octeon20(CN20K) SoCs from Marvell.

Only tested 64-bit mode with default configurations:

1. Build command
make PLATFORM=marvell-cn20ka
make PLATFORM=marvell-cnf20ka
2. Passed xtest

Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

Revert "plat-rockchip: rk3399: remove GIC configuration"

With commit 4cb77793842a ("irqchip/gic-v3: Fix rk3399 workaround when
secure interrupts are enabled") in the Linux kernel OP-TEE panics after

Revert "plat-rockchip: rk3399: remove GIC configuration"

With commit 4cb77793842a ("irqchip/gic-v3: Fix rk3399 workaround when
secure interrupts are enabled") in the Linux kernel OP-TEE panics after
the kernel has booted with:
E/TC:3 0 Panic 'Secure interrupt handler not defined' at core/kernel/interrupt.c:105 <interrupt_main_handler>

So for kernels after v6.14 we need another workaround. The easiest is to
revert commit 447c5f6bc49ff5408c0543ceaaabf0cb8f23804d. The GIC is still
broken, but the device is still usable in other aspects.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (rockchip-rk3399) (Rockpi4B)
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

plat-corstone1000: increase CFG_TZDRAM_SIZE

TZDRAM is a 4MB SRAM in Corstone-1000. Its start address is `0x0200_0000`
but the first 0x2000 bytes are reserved for future use. `CFG_TZDRAM_SIZE`
can be

plat-corstone1000: increase CFG_TZDRAM_SIZE

TZDRAM is a 4MB SRAM in Corstone-1000. Its start address is `0x0200_0000`
but the first 0x2000 bytes are reserved for future use. `CFG_TZDRAM_SIZE`
can be increased to `0x360000` so OP-TEE has more RAM.

Signed-off-by: Bence Balogh <bence.balogh@arm.com>
Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

dts: stm32: remove activation of RTC nodes at board level

Remove unnecessary activation of RTC in stm32mp15xxdkx.dtsi and
stm32mp135f-dk.dts.
RTC node is default enabled in stm32mp131.dtsi and stm32

dts: stm32: remove activation of RTC nodes at board level

Remove unnecessary activation of RTC in stm32mp15xxdkx.dtsi and
stm32mp135f-dk.dts.
RTC node is default enabled in stm32mp131.dtsi and stm32mp151.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dts: stm32: default enable RTC on stm32mp1

TAMP peripheral has a dependency on RTC.
Since TAMP is enable by default in stm32mp131.dtsi and stm32mp151.dtsi.
Default probe RTC to solve TAMP's dependen

dts: stm32: default enable RTC on stm32mp1

TAMP peripheral has a dependency on RTC.
Since TAMP is enable by default in stm32mp131.dtsi and stm32mp151.dtsi.
Default probe RTC to solve TAMP's dependency on it.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dts: stm32: enable Reset and Clock Controller for stm32mp215f-dk

Add device tree files for stm32mp215f-dk board.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Etienne C

dts: stm32: enable Reset and Clock Controller for stm32mp215f-dk

Add device tree files for stm32mp215f-dk board.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

plat-stm32mp2: update reset and clocks driver flags for STM32MP21

Add CFG_STM32MP21_CLK and CFG_STM32MP21_RSTCTRL flags to enable
RCC drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@fo

plat-stm32mp2: update reset and clocks driver flags for STM32MP21

Add CFG_STM32MP21_CLK and CFG_STM32MP21_RSTCTRL flags to enable
RCC drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

plat-vexpress: qemu_v8: support EL1 physical timer interrupt

Add support to configure the timer callout service based on interrupt
from the EL1 physical timer when configuration with SPMC at S-EL2
(

plat-vexpress: qemu_v8: support EL1 physical timer interrupt

Add support to configure the timer callout service based on interrupt
from the EL1 physical timer when configuration with SPMC at S-EL2
(CFG_CORE_SEL2_SPMC=y).

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

core: arm: support EL1 physical timer

When configured with an SPMC at S-EL2 (CFG_CORE_SEL2_SPMC=y) use the
(emulated) EL1 physical timer instead of the EL3 physical timer since
the latter then is us

core: arm: support EL1 physical timer

When configured with an SPMC at S-EL2 (CFG_CORE_SEL2_SPMC=y) use the
(emulated) EL1 physical timer instead of the EL3 physical timer since
the latter then is used by S-EL2.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

core: arm64.h: add {read,write}_cntp_{ct,tva,cva}l()

Add wrapper functions to read and write to the EL1 physical timer
registers cntp_ctl_el0, cntp_tval_el0, and cntp_cval_el0. These
registers are u

core: arm64.h: add {read,write}_cntp_{ct,tva,cva}l()

Add wrapper functions to read and write to the EL1 physical timer
registers cntp_ctl_el0, cntp_tval_el0, and cntp_cval_el0. These
registers are used when using the Arm Generic Timer with
CFG_CORE_SEL2_SPMC=y (Hafnium as SPMC at S-EL2).

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

plat-versal2: conf: Add maximum size of the DTB

The DTB size for the AMD platform is larger and does not fit into the
default size, leading to failure or panic at boot time due to size
issues.

Thus

plat-versal2: conf: Add maximum size of the DTB

The DTB size for the AMD platform is larger and does not fit into the
default size, leading to failure or panic at boot time due to size
issues.

Thus setting an explicit maximum size for the Device Tree Blob to
allow safe modifications. This ensures there is enough space when
appending or editing nodes/properties in the DTB.

Signed-off-by: Amey Avinash Raghatate <AmeyAvinash.Raghatate@amd.com>
Acked-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

dts: stm32: add missing i2c1 and i2c2 instances in stm32mp131.dtsi

i2c1 and i2c2 instances were missing within the stm32mp131.dtsi file
hence add them to have complete description of the stm32mp131

dts: stm32: add missing i2c1 and i2c2 instances in stm32mp131.dtsi

i2c1 and i2c2 instances were missing within the stm32mp131.dtsi file
hence add them to have complete description of the stm32mp131 i2c
controllers.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dts: stm32: align DMA channel for QSPI in stm32mp151.dtsi

Fix indentation of DMA channel definition for QSPI node in
stm32mp151.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Re

dts: stm32: align DMA channel for QSPI in stm32mp151.dtsi

Fix indentation of DMA channel definition for QSPI node in
stm32mp151.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-stm32mp1: stm32mp1_pwr: fix compatible

Remove the unexpected comma in compatible name "st,stm32mp1,pwr-reg"

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas

plat-stm32mp1: stm32mp1_pwr: fix compatible

Remove the unexpected comma in compatible name "st,stm32mp1,pwr-reg"

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

treewide: dts: stm32: remove deprecated pins-are-numbered in device tree

Align the binding and the stm32mp device tree with Linux kernel,
remove the deprecated properties pins-are-numbered.

No func

treewide: dts: stm32: remove deprecated pins-are-numbered in device tree

Align the binding and the stm32mp device tree with Linux kernel,
remove the deprecated properties pins-are-numbered.

No functional impact as it is not used in code.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz

When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
becau

clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz

When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
because the clkext2f frequency of 400MHz is not supported.

This patch also rename the function stm32mp2_a35_ss_on_hsi to
stm32mp2_a35_ss_on_bypass to be aligned with reference manual.

Fixes: 28c10f9efa6a ("clk: stm32mp25: Introduce STM32MP25 clocks platform")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

dts: stm32: add tamper event detection configuration for stm32mp257f-ev1

Add and default enable support for the TAMP button present on the
stm32mp257f-ev1 board. It relies on the external tamper 1.

dts: stm32: add tamper event detection configuration for stm32mp257f-ev1

Add and default enable support for the TAMP button present on the
stm32mp257f-ev1 board. It relies on the external tamper 1.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dts: stm32: use EXTI event instead of GIC SPI for TAMP in stm32mp251.dtsi

Rely on EXTI event for the tamper event detection instead of the GIC line.
The EXTI makes the link with the GIC and provides

dts: stm32: use EXTI event instead of GIC SPI for TAMP in stm32mp251.dtsi

Rely on EXTI event for the tamper event detection instead of the GIC line.
The EXTI makes the link with the GIC and provides wakeup capabilities.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dts: stm32: add tamper event detection configuration for stm32mp135f-dk

Add and default enable support for the TAMP button present on the
stm32mp135f-dk board. It relies on the external tamper 2.
Se

dts: stm32: add tamper event detection configuration for stm32mp135f-dk

Add and default enable support for the TAMP button present on the
stm32mp135f-dk board. It relies on the external tamper 2.
Set GPIOA6 as secure as it now serve this purpose.

Add and default disable support for a test setup of an active tamper
event detection that is feasible with the GPIO expansion present on the
stm32mp135f-dk board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...