core: arm: refactor RD-1AE and RD-Aspen into automotive_rd flavors

This change moves RD-1AE and RD-Aspen under a single
automotive_rd platform with per-flavor configuration.

Key updates:
- Introduc

core: arm: refactor RD-1AE and RD-Aspen into automotive_rd flavors

This change moves RD-1AE and RD-Aspen under a single
automotive_rd platform with per-flavor configuration.

Key updates:
- Introduce plat-automotive_rd/ with shared main.c,
platform_config.h and Makefiles.
- Define RD-1AE and RD-Aspen are selected
via PLATFORM_FLAVOR rd1ae or rdaspen.
- Merge flavor settings (UART/GIC/DRAM/topology)
into platform_config.h and conf.mk files.
- Use default get_core_pos_mpidr() by setting appropriate
CFG_CORE_CLUSTER_SHIFT / CFG_CORE_THREAD_SHIFT for rdaspen,
eliminating custom assembly where not required.

Benefits:
- Consistent with OP-TEE’s platform/variant framework.
- Reduces code duplication between RD-1AE and RD-Aspen.
- Simplifies adding new automotive reference design flavors
in the future.

Usage:
- Set PLATFORM=automotive_rd
- Set PLATFORM_FLAVOR to rdaspen or rd1ae

Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: stmm_sp: return FFA_NOT_SUPPORTED for undefined FFA functions

edk2's patch ("ArmFfaLib: Add Rx/Tx support for Stmm secure partition") [0]
added Rx/Tx buffer mapping support to ArmFfaStand

core: arm: stmm_sp: return FFA_NOT_SUPPORTED for undefined FFA functions

edk2's patch ("ArmFfaLib: Add Rx/Tx support for Stmm secure partition") [0]
added Rx/Tx buffer mapping support to ArmFfaStandaloneMm(Core)Lib.

However, stmm_sp does not require Rx/Tx buffer mapping and
its SVC handler is lightweight. Therefore, when it receives
an undefined FFA function, it is sufficient to return FFA_NOT_SUPPORTED to
StandaloneMm instead of panicking.

This also aligns with the FF-A specification, which requires returning
FFA_NOT_SUPPORTED when an unimplemented function ID is received.

If StandaloneMm fails to initialize, it will return FFA_ERROR.
In this case, there is no way to keep the stmm_sp TA alive,
so panic is called.
Otherwise, StandaloneMm will return with DIRECT_MSG_RESP.

Link: https://github.com/tianocore/edk2/pull/11080/commits/75ca159e57dbe081b89373046280f34d67571852 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Mikko Rapeli <mikko.rapeli@linaro.org>

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plat-vexpress: add QEMU sbsa-ref platform

Add support for the QEMU sbsa-ref platform. This platform is similar to
the QEMU virt platform, but with different memory configuration and
device addresses

plat-vexpress: add QEMU sbsa-ref platform

Add support for the QEMU sbsa-ref platform. This platform is similar to
the QEMU virt platform, but with different memory configuration and
device addresses.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: boot: fix TPM log area mapping to use correct device tree source

Change the conditional compilation for TPM log area mapping from
CFG_CORE_SEL1_SPMC to CFG_CORE_FFA. This ensures the correct d

core: boot: fix TPM log area mapping to use correct device tree source

Change the conditional compilation for TPM log area mapping from
CFG_CORE_SEL1_SPMC to CFG_CORE_FFA. This ensures the correct device
tree source is used:

- When CFG_CORE_FFA is enabled: use manifest DT (get_manifest_dt())
- When CFG_CORE_FFA is disabled: use external DT (get_external_dt())

The fix aligns the device tree source selection with the broader FFA
configuration, ensuring TPM log area mapping works correctly across
all FFA-enabled platforms regardless of the specific SPMC variant
(S-EL1, S-EL2, or EL3).

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: mx8mp_phyboard_pollux: reduce DDR_SIZE

Set pollux CFG_DDR_SIZE to 1GiB to let the conf.mk automatically set the
TZDRAM_START (to a valid address for 1GiB variants).

Acked-by: Sahil Malho

core: imx: mx8mp_phyboard_pollux: reduce DDR_SIZE

Set pollux CFG_DDR_SIZE to 1GiB to let the conf.mk automatically set the
TZDRAM_START (to a valid address for 1GiB variants).

Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>

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core: imx: add imx8mp-libra-fpsc

The Libra i.MX 8M Plus FPSC is a development board utilizing the FPSC
standard paired with the i.MX 8M Plus FPSC System-on-Module [1].
It shares RAM configuration wi

core: imx: add imx8mp-libra-fpsc

The Libra i.MX 8M Plus FPSC is a development board utilizing the FPSC
standard paired with the i.MX 8M Plus FPSC System-on-Module [1].
It shares RAM configuration with the phyBOARD-Pollux i.MX 8M Plus of
1-4GiB.
Set pollux CFG_DDR_SIZE to 1GiB to let the conf.mk automatically set the
TZDRAM_START (to a valid address for 1GiB variants).

Link: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/ [1]
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>

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plat-imx: add phytec imx8mm based boards

phyGATE-Tauri-L i.MX 8M Mini [1] and phyBOARD-Polis i.MX8M Mini [2] are
SBCs based on the i.MX 8M Mini SoC. Add the boards to the
mx8mm-flavorlist and set bo

plat-imx: add phytec imx8mm based boards

phyGATE-Tauri-L i.MX 8M Mini [1] and phyBOARD-Polis i.MX8M Mini [2] are
SBCs based on the i.MX 8M Mini SoC. Add the boards to the
mx8mm-flavorlist and set board specific configs.
phyGATE-Tauri-L has 2 GiB of main memory, while phyBOARD-Polis has
1-4GiB depending on variant of the System-on-Module populated on the
board.

Link: https://www.phytec.eu/en/produkte/fertige-geraete-oem/phygate-tauri-l/ [1]
Link: https://www.phytec.eu/en/produkte/single-board-computer/phyboard-polis-imx8m-mini/ [2]
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>

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plat-k3: drivers: Add TRNG driver support in AM62L

AM62L contains the EIP76D TRNG IP which was also present in the previous
K3 devices inside the SA2UL accelerator, so the same driver is being
re-us

plat-k3: drivers: Add TRNG driver support in AM62L

AM62L contains the EIP76D TRNG IP which was also present in the previous
K3 devices inside the SA2UL accelerator, so the same driver is being
re-used here. But the AM62L does not have SA2UL. The SoC specific
configurations are being set here for AM62L for enabling TRNG.

Signed-off-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Move RNG platform error from SA2UL to RNG defines

The error define for RNG base address being not defined for a platform
when software PRNG is disabled, is currently handled as a c

plat-k3: drivers: Move RNG platform error from SA2UL to RNG defines

The error define for RNG base address being not defined for a platform
when software PRNG is disabled, is currently handled as a case with
SA2UL platform config definitions. This is not appropriate as RNG is not
needed to be tied up to SA2UL. Moving it to be placed with RNG platform
configs where it is more apt.

Signed-off-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Refactor SA2UL driver

The EIP76D TRNG IP being used in current K3 devices is not unique to
SA2UL/SA3UL. The RNG driver can be reused in other devices containing
the same TRNG IP ou

plat-k3: drivers: Refactor SA2UL driver

The EIP76D TRNG IP being used in current K3 devices is not unique to
SA2UL/SA3UL. The RNG driver can be reused in other devices containing
the same TRNG IP outside of SA2UL/SA3UL.

Refactor the SA2UL and RNG driver to make EIP76D TRNG driver independent
of SA2UL.

Signed-off-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: qemu-v8: fix CFG_CORE_CLUSTER_SHIFT

QEMU virt puts 8 or 16 CPUs in each cluster, depending on the GIC
configuration [1]. So set CFG_CORE_CLUSTER_SHIFT to match the GIC
configuration t

plat-vexpress: qemu-v8: fix CFG_CORE_CLUSTER_SHIFT

QEMU virt puts 8 or 16 CPUs in each cluster, depending on the GIC
configuration [1]. So set CFG_CORE_CLUSTER_SHIFT to match the GIC
configuration to calculate core position correctly for more than 16
CPUs.

Link: https://gitlab.com/qemu-project/qemu/-/blob/v10.0.0/hw/arm/virt.c?ref_type=tags#L1785-1789 [1]
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)

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dts: stm32: add stm32mp257f-dk board support

Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC,
with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo,
DSI HDMI, LV

dts: stm32: add stm32mp257f-dk board support

Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC,
with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo,
DSI HDMI, LVDS connector ...

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: conf: add stm32mp257f-dk board support

Add support for the stm32mp257f-dk board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thom

plat-stm32mp2: conf: add stm32mp257f-dk board support

Add support for the stm32mp257f-dk board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: enable watchdog SMC service

Enable Arm watchdog SMC service using function ID 0xbc000000.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Gof

plat-stm32mp2: enable watchdog SMC service

Enable Arm watchdog SMC service using function ID 0xbc000000.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: conf: default enable CFG_STM32_IWDG

Default enable STM32 IWDG driver on STM32MP2 platforms.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le G

plat-stm32mp2: conf: default enable CFG_STM32_IWDG

Default enable STM32 IWDG driver on STM32MP2 platforms.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: enable IWDG1 on stm32mp215f-dk board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevall

dts: stm32: enable IWDG1 on stm32mp215f-dk board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: enable IWDG1 on stm32mp257f-ev1 board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.cheval

dts: stm32: enable IWDG1 on stm32mp257f-ev1 board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add IWDG[1-2] nodes in stm32mp21x soc device-tree

Add support for IWDG[1-2] in stm32mp21x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gat

dts: stm32: add IWDG[1-2] nodes in stm32mp21x soc device-tree

Add support for IWDG[1-2] in stm32mp21x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add IWDG[1-2] nodes in stm32mp25x soc device-tree

Add support for IWDG[1-2] in stm32mp25x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gat

dts: stm32: add IWDG[1-2] nodes in stm32mp25x soc device-tree

Add support for IWDG[1-2] in stm32mp25x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-versal2: use auto PA bit discovery

Removes hardcoded configuration for large physical address and
ARM64 PA bits, enabling automatic discovery of the maximal PA
supported by the hardware.

Signe

plat-versal2: use auto PA bit discovery

Removes hardcoded configuration for large physical address and
ARM64 PA bits, enabling automatic discovery of the maximal PA
supported by the hardware.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat: stm32mp2: sysconf: fix CA35SS register names

Align register names with the reference manuel for Arm Cortex-A35 (CA35SS)
- CA35SS SYSCFG registers (with 0x2000 offset)
- CA35SS Standardized sta

plat: stm32mp2: sysconf: fix CA35SS register names

Align register names with the reference manuel for Arm Cortex-A35 (CA35SS)
- CA35SS SYSCFG registers (with 0x2000 offset)
- CA35SS Standardized status and control (SSC) registers

This path removes the confusion between SSC and subsystem (SS).

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Co-developed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: sysconfig: fix ordering of SYSCFG defines

Reorder SYSCFG defines to prepare renaming so the defines use the same
name as the one in the reference manual.

Signed-off-by: Thomas Bourgo

plat-stm32mp2: sysconfig: fix ordering of SYSCFG defines

Reorder SYSCFG defines to prepare renaming so the defines use the same
name as the one in the reference manual.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: implement do_reset() API to force a system reset

Implement the do_reset() API that traps all cores if the SoC has multiple
cores, then prints a message and forces a system reset.

Sig

plat-stm32mp1: implement do_reset() API to force a system reset

Implement the do_reset() API that traps all cores if the SoC has multiple
cores, then prints a message and forces a system reset.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: implement do_reset() API to force a system reset

Implement the do_reset() API that traps all cores if the SoC has multiple
cores, then prints a message and forces a system reset.

Sig

plat-stm32mp2: implement do_reset() API to force a system reset

Implement the do_reset() API that traps all cores if the SoC has multiple
cores, then prints a message and forces a system reset.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: panic: allow core halting on SGI in other cases than panic()

There may be cases where we want to halt several cores outside of a
panic() sequence.

Therefore, add CFG_MULTI_CORE_HALTING switch

core: panic: allow core halting on SGI in other cases than panic()

There may be cases where we want to halt several cores outside of a
panic() sequence.

Therefore, add CFG_MULTI_CORE_HALTING switch that allows to register
an interrupt handler for the CFG_HALT_CORES_SGI that is dedicated to
halt other cores.

This reduces the scope of CFG_HALT_CORES_ON_PANIC that is now used only
for halting other cores in a panic() sequence.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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