xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision 86d405901e96ec82b8b23b623cebdbafcaacae4d) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8	mx6ulccbv2 \
9
10mx6ull-flavorlist = \
11	mx6ullevk \
12	mx6ulzevk \
13
14mx6q-flavorlist = \
15	mx6qsabrelite \
16	mx6qsabreauto \
17	mx6qsabresd \
18	mx6qhmbedge \
19	mx6qapalis \
20
21mx6qp-flavorlist = \
22	mx6qpsabreauto \
23	mx6qpsabresd \
24
25mx6sl-flavorlist = \
26	mx6slevk
27
28mx6sll-flavorlist = \
29	mx6sllevk
30
31mx6sx-flavorlist = \
32	mx6sxsabreauto \
33	mx6sxsabresd \
34	mx6sxudooneofull \
35
36mx6d-flavorlist = \
37	mx6dhmbedge \
38	mx6dapalis \
39
40mx6dl-flavorlist = \
41	mx6dlsabreauto \
42	mx6dlsabresd \
43	mx6dlhmbedge \
44
45mx6s-flavorlist = \
46	mx6shmbedge \
47	mx6solosabresd \
48	mx6solosabreauto \
49
50mx7d-flavorlist = \
51	mx7dsabresd \
52	mx7dpico_mbl \
53	mx7dclsom \
54
55mx7s-flavorlist = \
56	mx7swarp7 \
57	mx7swarp7_mbl \
58
59mx7ulp-flavorlist = \
60	mx7ulpevk
61
62mx8mq-flavorlist = \
63	mx8mqevk
64
65mx8mm-flavorlist = \
66	mx8mmevk \
67	mx8mm_cl_iot_gate \
68	mx8mm_phyboard_polis \
69	mx8mm_phygate_tauri_l
70
71mx8mn-flavorlist = \
72	mx8mnevk
73
74mx8mp-flavorlist = \
75	mx8mpevk \
76	mx8mp_rsb3720_6g \
77	mx8mp_phyboard_pollux
78
79mx8qm-flavorlist = \
80	mx8qmmek \
81
82mx8qx-flavorlist = \
83	mx8qxpmek \
84	mx8dxmek \
85
86mx8dxl-flavorlist = \
87	mx8dxlevk \
88
89mx8ulp-flavorlist = \
90	mx8ulpevk \
91
92mx93-flavorlist = \
93	mx93evk \
94
95mx95-flavorlist = \
96	mx95evk \
97
98mx91-flavorlist = \
99	mx91evk \
100
101ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
102$(call force,CFG_MX6,y)
103$(call force,CFG_MX6UL,y)
104$(call force,CFG_TEE_CORE_NB_CORE,1)
105$(call force,CFG_TZC380,y)
106include core/arch/arm/cpu/cortex-a7.mk
107else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
108$(call force,CFG_MX6,y)
109$(call force,CFG_MX6ULL,y)
110$(call force,CFG_TEE_CORE_NB_CORE,1)
111$(call force,CFG_TZC380,y)
112$(call force,CFG_IMX_CAAM,n)
113$(call force,CFG_NXP_CAAM,n)
114$(call force,CFG_IMX_DCP,y)
115include core/arch/arm/cpu/cortex-a7.mk
116else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
117$(call force,CFG_MX6,y)
118$(call force,CFG_MX6Q,y)
119$(call force,CFG_TEE_CORE_NB_CORE,4)
120$(call force,CFG_TZC380,y)
121else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
122$(call force,CFG_MX6,y)
123$(call force,CFG_MX6QP,y)
124$(call force,CFG_TEE_CORE_NB_CORE,4)
125else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
126$(call force,CFG_MX6,y)
127$(call force,CFG_MX6D,y)
128$(call force,CFG_TEE_CORE_NB_CORE,2)
129$(call force,CFG_TZC380,y)
130else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
131$(call force,CFG_MX6,y)
132$(call force,CFG_MX6DL,y)
133$(call force,CFG_TEE_CORE_NB_CORE,2)
134$(call force,CFG_TZC380,y)
135else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
136$(call force,CFG_MX6,y)
137$(call force,CFG_MX6S,y)
138$(call force,CFG_TEE_CORE_NB_CORE,1)
139else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
140$(call force,CFG_MX6,y)
141$(call force,CFG_MX6SL,y)
142$(call force,CFG_TEE_CORE_NB_CORE,1)
143$(call force,CFG_IMX_CAAM,n)
144$(call force,CFG_NXP_CAAM,n)
145$(call force,CFG_IMX_DCP,y)
146else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
147$(call force,CFG_MX6,y)
148$(call force,CFG_MX6SLL,y)
149$(call force,CFG_TEE_CORE_NB_CORE,1)
150$(call force,CFG_IMX_CAAM,n)
151$(call force,CFG_NXP_CAAM,n)
152$(call force,CFG_IMX_DCP,y)
153$(call force,CFG_NO_SMP,y)
154else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
155$(call force,CFG_MX6,y)
156$(call force,CFG_MX6SX,y)
157$(call force,CFG_TEE_CORE_NB_CORE,1)
158else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
159$(call force,CFG_MX7,y)
160$(call force,CFG_TEE_CORE_NB_CORE,1)
161include core/arch/arm/cpu/cortex-a7.mk
162else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
163$(call force,CFG_MX7,y)
164$(call force,CFG_TEE_CORE_NB_CORE,2)
165include core/arch/arm/cpu/cortex-a7.mk
166else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
167$(call force,CFG_MX7ULP,y)
168$(call force,CFG_TEE_CORE_NB_CORE,1)
169$(call force,CFG_TZC380,n)
170$(call force,CFG_IMX_CSU,n)
171include core/arch/arm/cpu/cortex-a7.mk
172else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
173$(call force,CFG_MX8MQ,y)
174$(call force,CFG_MX8M,y)
175$(call force,CFG_ARM64_core,y)
176$(call force,CFG_TZC380,y)
177CFG_DRAM_BASE ?= 0x40000000
178CFG_TEE_CORE_NB_CORE ?= 4
179else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
180$(call force,CFG_MX8MM,y)
181$(call force,CFG_MX8M,y)
182$(call force,CFG_ARM64_core,y)
183$(call force,CFG_TZC380,y)
184CFG_DRAM_BASE ?= 0x40000000
185CFG_TEE_CORE_NB_CORE ?= 4
186else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
187$(call force,CFG_MX8MN,y)
188$(call force,CFG_MX8M,y)
189$(call force,CFG_ARM64_core,y)
190$(call force,CFG_TZC380,y)
191CFG_DRAM_BASE ?= 0x40000000
192CFG_TEE_CORE_NB_CORE ?= 4
193else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
194$(call force,CFG_MX8MP,y)
195$(call force,CFG_MX8M,y)
196$(call force,CFG_ARM64_core,y)
197$(call force,CFG_TZC380,y)
198CFG_DRAM_BASE ?= 0x40000000
199CFG_TEE_CORE_NB_CORE ?= 4
200else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
201$(call force,CFG_MX8QM,y)
202$(call force,CFG_ARM64_core,y)
203$(call force,CFG_IMX_SNVS,n)
204CFG_IMX_LPUART ?= y
205CFG_DRAM_BASE ?= 0x80000000
206CFG_TEE_CORE_NB_CORE ?= 6
207$(call force,CFG_IMX_OCOTP,n)
208else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
209$(call force,CFG_MX8QX,y)
210$(call force,CFG_ARM64_core,y)
211$(call force,CFG_IMX_SNVS,n)
212CFG_IMX_LPUART ?= y
213CFG_DRAM_BASE ?= 0x80000000
214CFG_TEE_CORE_NB_CORE ?= 4
215$(call force,CFG_IMX_OCOTP,n)
216else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8dxl-flavorlist)))
217$(call force,CFG_MX8DXL,y)
218$(call force,CFG_ARM64_core,y)
219$(call force,CFG_IMX_SNVS,n)
220CFG_IMX_LPUART ?= y
221CFG_DRAM_BASE ?= 0x80000000
222$(call force,CFG_TEE_CORE_NB_CORE,2)
223$(call force,CFG_IMX_OCOTP,n)
224else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8ulp-flavorlist)))
225$(call force,CFG_MX8ULP,y)
226$(call force,CFG_ARM64_core,y)
227CFG_IMX_LPUART ?= y
228CFG_DRAM_BASE ?= 0x80000000
229CFG_TEE_CORE_NB_CORE ?= 2
230$(call force,CFG_NXP_SNVS,n)
231$(call force,CFG_IMX_OCOTP,n)
232CFG_IMX_MU ?= y
233CFG_IMX_ELE ?= n
234else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx93-flavorlist)))
235$(call force,CFG_MX93,y)
236$(call force,CFG_ARM64_core,y)
237CFG_IMX_LPUART ?= y
238CFG_DRAM_BASE ?= 0x80000000
239CFG_TEE_CORE_NB_CORE ?= 2
240$(call force,CFG_NXP_SNVS,n)
241$(call force,CFG_IMX_OCOTP,n)
242$(call force,CFG_TZC380,n)
243$(call force,CFG_CRYPTO_DRIVER,n)
244$(call force,CFG_NXP_CAAM,n)
245CFG_IMX_MU ?= y
246CFG_IMX_ELE ?= y
247else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx95-flavorlist)))
248$(call force,CFG_MX95,y)
249$(call force,CFG_ARM64_core,y)
250CFG_IMX_LPUART ?= y
251CFG_DRAM_BASE ?= 0x80000000
252CFG_TEE_CORE_NB_CORE ?= 6
253$(call force,CFG_NXP_SNVS,n)
254$(call force,CFG_IMX_OCOTP,n)
255$(call force,CFG_TZC380,n)
256$(call force,CFG_NXP_CAAM,n)
257else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx91-flavorlist)))
258$(call force,CFG_MX91,y)
259$(call force,CFG_ARM64_core,y)
260CFG_IMX_LPUART ?= y
261CFG_DRAM_BASE ?= 0x80000000
262CFG_TEE_CORE_NB_CORE ?= 1
263$(call force,CFG_NXP_SNVS,n)
264$(call force,CFG_IMX_OCOTP,n)
265$(call force,CFG_TZC380,n)
266$(call force,CFG_NXP_CAAM,n)
267CFG_IMX_MU ?= y
268CFG_IMX_ELE ?= y
269else
270$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
271endif
272
273ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
274CFG_DDR_SIZE ?= 0x40000000
275CFG_NS_ENTRY_ADDR ?= 0x80800000
276CFG_IMX_WDOG_EXT_RESET ?= y
277endif
278
279ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
280CFG_DDR_SIZE ?= 0x40000000
281CFG_UART_BASE ?= UART1_BASE
282CFG_IMX_WDOG_EXT_RESET ?= y
283endif
284
285ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
286CFG_DDR_SIZE ?= 0x20000000
287CFG_NS_ENTRY_ADDR ?= 0x87800000
288CFG_DT_ADDR ?= 0x83100000
289CFG_UART_BASE ?= UART5_BASE
290CFG_BOOT_SECONDARY_REQUEST ?= n
291CFG_EXTERNAL_DTB_OVERLAY ?= y
292CFG_IMX_WDOG_EXT_RESET ?= y
293endif
294
295ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
296CFG_DDR_SIZE ?= 0x20000000
297CFG_NS_ENTRY_ADDR ?= 0x80800000
298CFG_BOOT_SECONDARY_REQUEST ?= n
299endif
300
301ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
302CFG_DDR_SIZE ?= 0x20000000
303CFG_NS_ENTRY_ADDR ?= 0x87800000
304CFG_DT_ADDR ?= 0x83100000
305CFG_BOOT_SECONDARY_REQUEST ?= n
306CFG_EXTERNAL_DTB_OVERLAY = y
307CFG_IMX_WDOG_EXT_RESET = y
308endif
309
310ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
311CFG_DDR_SIZE ?= 0x40000000
312CFG_NS_ENTRY_ADDR ?= 0x60800000
313CFG_UART_BASE ?= UART4_BASE
314endif
315
316ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
317	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
318	mx6dapalis mx6qapalis))
319CFG_DDR_SIZE ?= 0x40000000
320CFG_NS_ENTRY_ADDR ?= 0x12000000
321endif
322
323ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
324	mx6dlsabreauto mx6solosabreauto))
325CFG_DDR_SIZE ?= 0x80000000
326CFG_NS_ENTRY_ADDR ?= 0x12000000
327CFG_UART_BASE ?= UART4_BASE
328endif
329
330ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
331CFG_DDR_SIZE ?= 0x80000000
332CFG_UART_BASE ?= UART1_BASE
333endif
334
335ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
336CFG_DDR_SIZE ?= 0x40000000
337CFG_NS_ENTRY_ADDR ?= 0x12000000
338endif
339
340ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
341CFG_DDR_SIZE ?= 0x40000000
342CFG_NS_ENTRY_ADDR ?= 0x12000000
343CFG_UART_BASE ?= UART2_BASE
344endif
345
346ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
347CFG_NS_ENTRY_ADDR ?= 0x80800000
348CFG_DDR_SIZE ?= 0x40000000
349endif
350
351ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
352CFG_NS_ENTRY_ADDR ?= 0x80800000
353CFG_DDR_SIZE ?= 0x80000000
354endif
355
356ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
357CFG_DDR_SIZE ?= 0x80000000
358CFG_NS_ENTRY_ADDR ?= 0x80800000
359endif
360
361ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
362CFG_DDR_SIZE ?= 0x40000000
363CFG_NS_ENTRY_ADDR ?= 0x80800000
364endif
365
366ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
367CFG_DDR_SIZE ?= 0x40000000
368CFG_UART_BASE ?= UART1_BASE
369endif
370
371ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
372CFG_DDR_SIZE ?= 0x20000000
373CFG_NS_ENTRY_ADDR ?= 0x80800000
374endif
375
376ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
377CFG_DDR_SIZE ?= 0x10000000
378CFG_NS_ENTRY_ADDR ?= 0x80800000
379CFG_UART_BASE ?= UART5_BASE
380endif
381
382ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
383CFG_DDR_SIZE ?= 0x10000000
384CFG_NS_ENTRY_ADDR ?= 0x80800000
385endif
386
387ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
388CFG_DDR_SIZE ?= 0x10000000
389CFG_UART_BASE ?= UART7_BASE
390endif
391
392ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
393CFG_DDR_SIZE ?= 0xc0000000
394CFG_UART_BASE ?= UART1_BASE
395endif
396
397ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
398CFG_DDR_SIZE ?= 0x80000000
399CFG_UART_BASE ?= UART2_BASE
400endif
401
402ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_cl_iot_gate))
403CFG_DDR_SIZE ?= 0x40000000
404CFG_UART_BASE ?= UART3_BASE
405CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
406CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
407endif
408
409ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phyboard_polis))
410CFG_DDR_SIZE ?= 0x40000000
411CFG_UART_BASE ?= UART3_BASE
412$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
413$(call force,CFG_CORE_ARM64_PA_BITS,36)
414endif
415
416ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phygate_tauri_l))
417CFG_DDR_SIZE ?= 0x80000000
418CFG_UART_BASE ?= UART3_BASE
419$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
420$(call force,CFG_CORE_ARM64_PA_BITS,36)
421endif
422
423ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
424CFG_DDR_SIZE ?= 0x80000000
425CFG_UART_BASE ?= UART2_BASE
426endif
427
428ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
429CFG_DDR_SIZE ?= UL(0x180000000)
430CFG_UART_BASE ?= UART2_BASE
431$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
432$(call force,CFG_CORE_ARM64_PA_BITS,36)
433endif
434
435ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_phyboard_pollux))
436CFG_DDR_SIZE ?= 0x80000000
437CFG_UART_BASE ?= UART1_BASE
438$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
439$(call force,CFG_CORE_ARM64_PA_BITS,36)
440endif
441
442ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_rsb3720_6g))
443CFG_DDR_SIZE ?= UL(0x180000000)
444CFG_UART_BASE ?= UART3_BASE
445CFG_TZDRAM_START ?= 0x56000000
446$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
447$(call force,CFG_CORE_ARM64_PA_BITS,36)
448endif
449
450ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
451CFG_DDR_SIZE ?= 0x80000000
452CFG_UART_BASE ?= UART0_BASE
453CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
454CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
455CFG_CORE_ARM64_PA_BITS ?= 40
456endif
457
458ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxmek))
459CFG_DDR_SIZE ?= 0x40000000
460CFG_UART_BASE ?= UART0_BASE
461$(call force,CFG_MX8DX,y)
462endif
463
464ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxlevk))
465CFG_DDR_SIZE ?= 0x40000000
466CFG_UART_BASE ?= UART0_BASE
467CFG_NSEC_DDR_1_BASE ?= 0x800000000UL
468CFG_NSEC_DDR_1_SIZE ?= 0x400000000UL
469CFG_CORE_ARM64_PA_BITS ?= 40
470endif
471
472ifneq (,$(filter $(PLATFORM_FLAVOR),mx8ulpevk))
473CFG_DDR_SIZE ?= 0x80000000
474CFG_UART_BASE ?= UART5_BASE
475endif
476
477ifneq (,$(filter $(PLATFORM_FLAVOR),mx93evk mx91evk))
478CFG_DDR_SIZE ?= 0x80000000
479CFG_UART_BASE ?= UART1_BASE
480endif
481
482ifneq (,$(filter $(PLATFORM_FLAVOR),mx95evk))
483CFG_DDR_SIZE ?= 0x80000000
484CFG_UART_BASE ?= UART1_BASE
485CFG_NSEC_DDR_1_BASE ?= 0x100000000UL
486CFG_NSEC_DDR_1_SIZE ?= 0x380000000UL
487CFG_CORE_ARM64_PA_BITS ?= 40
488endif
489
490# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
491ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
492	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
493include core/arch/arm/cpu/cortex-a9.mk
494
495$(call force,CFG_PL310,y)
496
497CFG_PL310_LOCKED ?= y
498CFG_ENABLE_SCTLR_RR ?= y
499CFG_IMX_SCU ?= y
500endif
501
502ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
503CFG_DRAM_BASE ?= 0x10000000
504endif
505
506ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
507	$(CFG_MX6SX)))
508CFG_DRAM_BASE ?= 0x80000000
509endif
510
511ifeq ($(filter y, $(CFG_MX7)), y)
512CFG_INIT_CNTVOFF ?= y
513CFG_DRAM_BASE ?= 0x80000000
514endif
515
516ifeq ($(filter y, $(CFG_MX7ULP)), y)
517CFG_INIT_CNTVOFF ?= y
518CFG_DRAM_BASE ?= UL(0x60000000)
519$(call force,CFG_IMX_LPUART,y)
520$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
521endif
522
523ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
524$(call force,CFG_GIC,y)
525
526CFG_BOOT_SECONDARY_REQUEST ?= y
527CFG_DT ?= y
528CFG_DTB_MAX_SIZE ?= 0x20000
529CFG_PAGEABLE_ADDR ?= 0
530CFG_PSCI_ARM32 ?= y
531CFG_SECURE_TIME_SOURCE_REE ?= y
532CFG_UART_BASE ?= UART1_BASE
533endif
534
535ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8M)))
536$(call force,CFG_IMX_UART,y)
537CFG_IMX_SNVS ?= y
538endif
539
540ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
541CFG_IMX_CSU ?= y
542endif
543
544ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
545CFG_HWSUPP_MEM_PERM_WXN = n
546CFG_IMX_WDOG ?= y
547endif
548
549ifeq ($(CFG_ARM64_core),y)
550# arm-v8 platforms
551include core/arch/arm/cpu/cortex-armv8-0.mk
552$(call force,CFG_ARM_GICV3,y)
553$(call force,CFG_GIC,y)
554$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
555$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
556
557CFG_CRYPTO_WITH_CE ?= y
558
559supported-ta-targets = ta_arm64
560endif
561
562CFG_TZDRAM_SIZE ?= 0x01e00000
563CFG_SHMEM_SIZE ?= 0x00200000
564CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - $(CFG_TZDRAM_SIZE) - $(CFG_SHMEM_SIZE) + $(CFG_DDR_SIZE))
565CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
566
567# Enable embedded tests by default
568CFG_ENABLE_EMBEDDED_TESTS ?= y
569CFG_ATTESTATION_PTA ?= y
570
571# Set default heap size for imx platforms to 128k
572CFG_CORE_HEAP_SIZE ?= 131072
573
574CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
575CFG_MMAP_REGIONS ?= 24
576
577# SE05X and OCOTP both implement tee_otp_get_die_id()
578ifeq ($(CFG_NXP_SE05X),y)
579$(call force,CFG_IMX_OCOTP,n)
580$(call force,CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID,n)
581endif
582CFG_IMX_OCOTP ?= y
583CFG_IMX_DIGPROG ?= y
584CFG_PKCS11_TA ?= y
585CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID ?= y
586
587# Almost all platforms include CAAM HW Modules, except the
588# ones forced to be disabled
589CFG_NXP_CAAM ?= n
590
591ifeq ($(CFG_NXP_CAAM),y)
592ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX) $(CFG_MX8DXL)), y)
593CFG_IMX_SC ?= y
594CFG_IMX_MU ?= y
595endif
596
597else
598
599ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
600CFG_IMX_CAAM ?= y
601endif
602
603endif
604